CN112996183A

CN112996183A - LED control IC single-wire cascade data communication method

Info

Publication number: CN112996183A
Application number: CN202110374853.1A
Authority: CN
Inventors: 尹华平
Original assignee: Dongguan Huacaiwei Technology Co ltd
Current assignee: Dongguan Huacaiwei Technology Co ltd
Priority date: 2021-04-08
Filing date: 2021-04-08
Publication date: 2021-06-18
Anticipated expiration: 2041-04-08
Also published as: CN112996183B

Abstract

The invention discloses a single-wire cascade data communication method of an LED control IC. The method is used for the LED control IC in single-wire cascade connection, and data coding signals are input through an input end DIN of the control IC and output through an output end DOUT and are output to an input end DIN of a next-stage control IC; the time width of a high-level signal in each data coding signal is determined through a clock period in a control IC during transmission to define a 0 code and a 1 code in data coding, a coding period synchronous with an input end is kept when the data coding is output, meanwhile, the input data coding is judged, the coding period of the input data coding is fixedly kept unchanged, and the high-level signal corresponding to each data coding is shaped to a length convenient for the control IC to identify in cascade in a time synchronization mode. The invention adopts a single oscillator structure, and simultaneously adds waveform width range identification, thereby greatly reducing the error rate even in a longer cascade transmission process.

Description

LED control IC single-wire cascade data communication method

Technical Field

The invention relates to the technical field of LED control, in particular to a single-wire cascade data communication method for an LED control IC.

Background

In the current serial cascade LED product, each LED is integrated with a control IC. And controlling the RGB color and lighting or not of the corresponding LED chip by the control IC. The single-wire cascade data communication mode is a control mode adopted by the current serial cascade LED product, and the principle is as follows: 2 oscillators are used in the control IC, wherein one oscillator is used to keep the data refresh of the RGB port continuously and to detect the state of the data input DIN, and when a high signal is detected at the input DIN, the other oscillator is woken up to generate an oscillation waveform, which is compared with the high signal of DIN to identify code 0 and code 1. At the same time, the 0 code and 1 code of the cycle number waveform set in the control IC are output to the next cascade control IC, so-called 0 code and 1 code shaping is generated. Because the serially cascaded LED forms a data code by the control signal when in work, the data code is a group of code groups consisting of a plurality of 0 code 1 codes, so that different code groups correspond to different control instructions, and the serially cascaded LED lamp string generates corresponding light-emitting effect.

The above method is simple to control, but has many disadvantages. First, when noise interference occurs on the control signal line, if it cannot be filtered, it is mistaken for the encoded signal, and a 0-code or 1-code error may be formed. Next, in encoding, the 0 code and the 1 code are discriminated by waveforms corresponding to the number of cycles, but discrimination errors are liable to occur in the critical states of both codes. Finally, because two oscillators are integrated in the control IC, a lot of clutter noises are easily generated, the requirement on the power supply filter capacitance of the control IC is high, but if a single oscillator is adopted, the dual-core work of RGB port line brushing and real-time monitoring and judgment of the cascade input data signals cannot be considered at the same time.

In view of the above problems, the present inventors provide the following technical solutions.

Disclosure of Invention

The invention aims to solve the technical problem of overcoming the defects in the prior art and provides a single-wire cascade data communication method for an LED control IC.

In order to solve the technical problems, the invention adopts the following technical scheme: a single-wire cascade data communication method of LED control ICs is used in the LED control ICs of single-wire cascade, the data-encoded signal is input via the input DIN of the control IC and output via the output DOUT of the control IC, and output to the input DIN of the next control IC, the data coding signal is transmitted in communication, the time width of the high level signal in each data-encoded signal is determined by the clock period in the control IC, to define a code 0 and a code 1 in the data code, which is output from the output terminal DOUT, for a code period which is kept in synchronism with the input terminal DIN, and meanwhile, the input data codes are judged, the coding period of the input data codes is fixedly kept unchanged by controlling the data codes input by the IC synchronous shaping input end DIN, and the high-level signal corresponding to each data code is subjected to time synchronous shaping to the length convenient for the control IC to identify in cascade connection.

Further, in the above technical solution, in the data encoding communication transmission, the time width of the high level signal in each data encoding signal corresponds to different clock cycles to define a 0 code and a 1 code in the encoding, and when defining the encoding, the minimum clock cycle and the maximum clock cycle are determined, and for the encoding signal in which the high level time in the data encoding is less than the minimum clock cycle and greater than the maximum clock cycle, the encoding signal is directly output without controlling the IC identification process.

Furthermore, in the above technical solution, an intermediate clock cycle is taken between the minimum clock cycle and the maximum clock cycle, and for the coded signal in the data coding, in which the high level time is greater than the minimum clock cycle and less than the intermediate clock cycle, the coded signal is identified as a 0 code or a 1 code by the control IC; for the coded signals with high level time larger than the middle clock period and smaller than the maximum clock period in the data coding, the control IC recognizes the coded signals as 1 code or 0 code.

Furthermore, in the above technical solution, an interval clock cycle is taken between the minimum clock cycle and the maximum cycle, and for the coded signal with the high level time greater than the minimum clock cycle and less than the interval cycle in the data coding, the controlled IC recognizes the coded signal as a 0 code or a 1 code; for the coded signal with high level time larger than interval clock period and smaller than maximum clock period in the data coding, the coded signal is identified as 1 code or 0 code by the control IC; for the coded signal of high level time in interval clock cycle in data coding, it is directly output without control IC identification process.

Further, in the above technical solution, the manner of shaping the high level signal corresponding to each data code to a length convenient for identification of the control IC in the cascade in time synchronization is as follows: (1) for the coded signal with high level time width less than N1 clock cycles in the input data code, the coded signal is directly output without being identified and processed by the control IC; (2) for the coded signal whose high level time width is greater than N1 clock cycles and less than N2 clock cycles in the input data code, the synchronous shaping process is processed into coded signal whose width is N2 cycles, then the coded signal is output, and at the same time the coded signal is recognized as 0 code or 1 code by the control IC; (3) for the input data coding, the high-level time width is more than N2 clock cycles, and the coded signal less than N3 clock cycles is directly output without shaping and is simultaneously identified as 0 code or 1 code by the control IC; (4) for the input data coding, the high level time width is larger than N3 clock cycles, and the coded signal which is smaller than N4 clock cycles is synchronously shaped into a signal with the width of N4 cycles and then output; and simultaneously identified as 1 code or 0 code by the control IC chip; for the input data coding, the high-level time width is larger than N4 clock cycles, and the coded signals smaller than N5 clock cycles are synchronously output without shaping; and is recognized as 1 code or 0 code by the control IC; the data with more than N5 clock cycles in the input data codes are directly output without being identified and processed by the control IC; n1, N2, N3, N4 and N5 are clock cycles corresponding to the definition of encoding by clock cycles, wherein N1 is the minimum number of clock cycles, N5 is the maximum number of clock cycles, N1, N2, N3, N4 and N5 are natural numbers, and N1< N2< N3< N4< N5.

Further, in the above technical solution, the manner of synchronously shaping the signal width corresponding to each code in the data codes to the length convenient for identification of the control IC in the cascade is as follows: (1) for the coded signal with high level time width less than N1 clock cycles in the input data code, the coded signal is directly output without being identified and processed by the control IC; (2) for the input data coding, the high level time width is larger than N1 clock cycles, and the synchronous shaping of the coded signal smaller than N2 clock cycles is processed into the coded signal with the width of N2 cycles, then the coded signal is output, and the coded signal is identified as 0 code or 1 code by the control IC; (3) for the input data coding, the high-level time width is more than N2 clock cycles, and the coded signal less than N3 clock cycles is directly output without shaping and is simultaneously identified as 0 code or 1 code by the control IC; (4) for the input data coding, the high-level time width is more than N3 clock cycles, and the coding signal less than N4 clock cycles is directly output without being identified and processed by the control IC; (5) for the input data coding, the high level time width is larger than N4 clock cycles, and the coded signal which is smaller than N5 clock cycles is synchronously shaped into a signal with the width of N5 cycles and then output; and simultaneously identified as 1 code or 0 code by the control IC chip; (6) for the input data coding, the high-level time width is larger than N5 clock cycles, and the coded signals smaller than N6 clock cycles are synchronously output without shaping; and is recognized as 1 code or 0 code by the control IC; (7) for data with high level time width larger than N6 clock periods in the input data codes, the data are directly output without being identified and processed by the control IC; n1, N2, N3, N4, N5 and N6 in the above description are clock cycles corresponding to the definition of encoding by clock cycles, where N1 is the minimum number of clock cycles, N6 is the maximum number of clock cycles, N1, N2, N3, N4, N5 and N6 in the above description are natural numbers, and N1< N2< N3< N4< N5< N6.

Further, in the above technical solution, after the invention adopts the above technical solution, the invention adopts a single oscillator structure, and through an innovative circuit structure, the invention also considers the real-time refresh without stopping of the RGB port, and ensures real-time monitoring of the cascaded DIN signal without loss. Meanwhile, the waveform width range identification is added, so that interference signals which do not meet the time sequence requirement can not be identified by mistake. The IC has an internal single-oscillator structure, and internally generated noise is low. The performance is more stable and reliable, and be favorable to energy-conservation, chip size miniaturization, can utilize the latest chip to make technology and integrate the electric capacity to the chip inside simultaneously, need not external electric capacity, the integrated level can increase substantially.

Drawings

FIG. 1 is a waveform diagram illustrating a first condition according to a first embodiment of the present invention;

FIG. 2 is a waveform diagram illustrating a second scenario in accordance with one embodiment of the present invention;

FIG. 3 is a waveform diagram illustrating a third situation according to a first embodiment of the present invention;

FIG. 4 is a waveform diagram illustrating a fourth scenario in accordance with a first embodiment of the present invention;

FIG. 5 is a waveform diagram illustrating a fifth scenario in accordance with the first embodiment of the present invention;

fig. 6 is a logic circuit diagram according to an embodiment of the invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

The invention relates to a single-wire cascade data communication method of an LED control IC, which is used in the single-wire cascade LED control IC, wherein a data coding signal is input through an input end DIN of the control IC, is output through an output end DOUT of the control IC and is output to an input end DIN of a next-stage control IC.

In the communication transmission of data code signals, each data code corresponds to one code period. The coding period is composed of a high level signal and a low level signal, and the control IC determines whether the data code corresponds to a 0 code or a 1 code by judging the time of the high level signal. For example, when the time of the high level signal is in a certain time range, the control IC recognizes it as a 0 code; when the time of the high level signal is in another time range, the control IC recognizes it as the 1 code.

In order to ensure that data encoding signals are not identified incorrectly due to signal attenuation and interference during transmission, the current practice is: the time of the data-encoded input high-level signal is fixed. The high time of the signal thus synchronously output is determined by each control IC itself, and the low time is determined by the input DIN. This results in that the coding period of each data-coding signal input by the input DIN is not synchronized with the coding period of each data-coding signal output by the output DOUT. The invention synchronizes the data coding, i.e. maintains a coding period that is synchronized with the input DIN when the data coding is output by the output DOUT. The complete high-low level period in the coding period of each data code is determined by the input end DIN, and the high-low level duty ratio is determined by each control IC through judging the state of the input end DIN. Therefore, the whole coding period of the data transmitted by data coding is unchanged, each cascaded control IC does not need a synchronous oscillator, and the single-oscillator can be adopted in the invention.

The present invention will be described in detail below. Assuming that N is defined as the number of clock cycles in the control IC, N may be any natural number. The "0" code and the "1" code are defined by taking the corresponding clock cycle signals between N1-N5, where N5> N3> N1. N1 is the clock cycle defining the smallest clock cycle of the 0 code and the 1 code in encoding, and N5 is the clock cycle defining the largest clock cycle of the 0 code and the 1 code in encoding. One intermediate clock cycle N3 is taken between the minimum clock cycle and the maximum clock cycle. For the data coding signals with high level time larger than the minimum clock period and smaller than the middle clock period in the data coding, the control IC identifies the data coding signals as 0 codes or 1 codes; for the coded signals with high level time larger than the middle clock period and smaller than the maximum clock period in the data coding, the control IC recognizes the coded signals as 1 code or 0 code. For example, the definition may be: signals of N1-N3 clock cycles are positioned as "0" codes and signals of N3-N5 clock cycles are positioned as "1" codes. Each data code is in this way recognized by the control IC. For the coded signals with the clock period less than N1 or greater than N5, the signals exceed the defined range and can be directly output without processing and IC identification control. For example, assuming that N1 is 2, N3 is 8, and N5 is 16, a signal greater than 2 and less than 8 clock cycles is set as a "0" code, and a signal greater than 8 clock cycles and less than 16 clock cycles is set as a "1" code. The data code is positioned as a corresponding "0" code or "1" code according to the clock cycle corresponding to the high level in the data code signal at the input DIN. Of course, the "0" code and the "1" code may be defined in reverse. The specific clock period can be determined according to the actual data encoding cycle time and the clock period time in the control IC, without any limitation.

When the data codes are output by the output end DOUT, the synchronous coding period with the input end DIN is kept, meanwhile, the input data codes are judged, and the input data coding period is fixedly kept unchanged by controlling the IC to synchronously shape the data codes input by the input end DIN. Meanwhile, in order to facilitate the control of IC identification data codes, the high-level signal corresponding to each data code is shaped to the length convenient for the control of IC identification in cascade connection in a time synchronization manner. The invention optimizes the duty ratio of 0 code and 1 code in the input coding data, but the cycle of the input data code is not changed, and synchronously shapes the data code with non-optimal high-level signal time to the most appropriate time width, thereby being convenient for controlling IC identification and processing, greatly reducing the error code rate during long-distance transmission and greatly improving the fault-tolerant rate.

The time synchronization shaping method of the data encoding according to the present invention will be described in detail below based on the waveform of the corresponding data encoded signal.

Example one

For convenience of illustration, in the first embodiment, the input data coding at the input end DIN has a high level time TH and a low level time TL, and the data coding at the input end DIN has a whole period time T, where T is TH + TL. Clock cycle by defining N as the number of cycles of a clock cycle, N can be any natural number. The "0" code and the "1" code are defined by taking the corresponding clock cycle signals between N1-N5. In the first embodiment, N1 is 2; n2 is 6; n3 is 8; n4 is 12; n5 is 16. Signals with a high signal time at the input DIN of more than N1 and less than N3 clock cycles are designated as "0" codes, and signals with more than N3 and less than N5 clock cycles are designated as "1" codes. Of course, the specific value of N may be set as needed or the time of the clock cycle.

The first embodiment includes the following cases.

In the first case: the coded signal with high level time less than N1 clock cycles in the input data coding is directly output without being identified and processed by the control IC.

As shown in fig. 1, this is a waveform diagram of the first case in the first embodiment. At this time, the coding period signal inputted from the input terminal DIN is T1, wherein the time of high level is T11, the time of low level is T12, and T11 is less than two clock periods. For the condition that the high level signal of the input end DIN is less than 2 clock cycles, the invention does not process and directly outputs the signal. Since generally, as long as the signal at the input DIN is strictly limited, no high-level signal with a period less than 2 clock cycles will occur, because external noise or interference noise, which is a transmission signal that is not needed to be used, must be a very narrow pulse signal with a high level. For such high level signals less than 2 clock cycles, the control IC may not need to identify such abnormal signals, avoiding the generation of interference effects. Meanwhile, the invention does not carry out any synchronization on the abnormal signal and outputs the abnormal signal, thus allowing the occurrence of glitch pulse in the whole cascade connection without any influence on the whole signal transmission. The narrow pulse signals with less than 2 clock cycles are synchronously output without processing, and the post-stage control IC can not identify during cascade connection, so that some interference and noise can be identified more easily and eliminated during post-processing.

In the above case, since the encoded signal is directly output without any shaping of the data code whose high level time is less than N1, the encoded period signal output from the output terminal DOUT is still T1, and the encoded period is maintained in synchronization with the input terminal DIN.

In the second case: for the input data coding high level time is more than N1 clock cycles and less than N2 clock cycles coding signal, the synchronous shaping is processed into N2 clock cycles coding signal and then output, and at the same time, the control IC recognizes as 0 code.

See fig. 2, which is a waveform diagram of the second case in the first embodiment. At this time, the coding period signal inputted from the input terminal DIN is T2, wherein the high level is T21 and the low level is T22. As shown in fig. 2, at this time N1< T21< N2. For the encoded signal with the input DIN high level signal time longer than N1 clock cycles and shorter than N2 clock cycles, the present invention will process the input encoded signal high level synchronization into N2 cycles, which is equivalent to lengthening the synchronization shaping of the short high level input signal, i.e. making T21 equal to N2. So that the input signal, its corresponding "0" code, is relatively easily recognized by the control IC.

Since the time of T21 is lengthened by the shaping, in order to keep the entire data encoding period still following the input terminal DIN, still T2, the time of the corresponding low level T22 needs to be shortened, so that the entire data encoding period is kept synchronized with the input terminal DIN at the time of output.

After processing in this way, the high level signal corresponding to the data code is time-synchronously shaped to a length convenient for the control IC in the cascade, so that in a long cascade application, even after the signal at the input end DIN is attenuated, the high level signal in the data code is still synchronized and restored to a length of 6 clock cycles (N2), and thus is effectively recognized as a "0" code.

In the third case: the high level time in the input data coding is more than N2 clock cycles and less than N3 clock cycles, and the coded signals are directly output without shaping and are simultaneously identified as 0 codes by the control IC.

See fig. 3, which is a waveform diagram of the third case of the first embodiment. At this time, the coding period signal inputted from the input terminal DIN is T3, wherein the high level is T31 and the low level is T32. As shown in fig. 3, at this time N2< T31< N3. For such encoded signals with input DIN high signal times greater than N1 clock cycles and less than N2 clock cycles, the present invention does not deal with this because the input signal width is long enough to be easily recognized. The output signal of the output terminal DOUT is completely consistent with the DIN period and the duty ratio. Even in a long cascade application, when the signal is attenuated and the whole input signal is gradually less than N2 clock cycles, the situation of the above 2 is entered, and the signal is still synchronized and restored to be an effective "0" code signal according to the processing manner of the situation of the 2, and the period is kept unchanged from the input end DIN, and the high level width of N2 clock cycles.

In a fourth case: for the coded signals with high level time which is more than N3 clock cycles and less than N4 clock cycles in the input data codes, the coded signals are synchronously shaped into coded signals with the width of N4 cycles and then output; and is simultaneously recognized as a 1 code by the control IC chip.

See fig. 4, which is a waveform diagram of the fourth case in the first embodiment. At this time, the coding period signal inputted from the input terminal DIN is T4, wherein the high level is T41 and the low level is T42. As shown in fig. 4, at this time N3< T41< N4. For the encoded signal with the input DIN high signal time longer than N3 clock cycles and shorter than N4 clock cycles, the present invention processes the input encoded signal high level synchronization into N4 cycles, which is equivalent to lengthening the shaping of the high level input signal synchronization, i.e. making T41 equal to N4. So that the input signal, its corresponding "1" code, is relatively easily recognized by the control IC. Similarly, since the time of T41 is lengthened by the shaping, in order to keep the whole data encoding period still following the input terminal DIN, and still being T4, the time of the corresponding low level T42 needs to be shortened, so that the whole data encoding period is kept synchronized with the input terminal DIN at the time of output.

After processing in this way, the output signal at the output terminal Dout has a period identical to that of the input terminal DIN. Thus, in a long cascade application, after the signal is attenuated, the signal can still be synchronized and restored to be an effective "1" code signal, with a high level width of N4 clock cycles.

In the fifth case, the high level time in the input data encoding is more than N4 clock cycles, and the encoding signal less than N5 clock cycles is synchronously output without shaping; and is simultaneously recognized as a 1 code by the control IC.

As shown in fig. 5, this is a waveform diagram of the fifth case in the first embodiment. At this time, the coding period signal inputted from the input terminal DIN is T5, wherein the high level is T51 and the low level is T52. As shown in fig. 5, at this time N4< T51< N5. For such encoded signals with input DIN high signal times greater than N4 clock cycles and less than N5 clock cycles, the present invention does not deal with this because the input signal width is long enough to be easily recognized. The period and the duty ratio of the output signal of the output terminal Dout are completely consistent with those of the input terminal DIN. Thus, in a long cascade application, even if the entire input signal is gradually less than N4 clock cycles after the signal attenuation, the signal is still synchronized and restored to an effective "1" code signal, a high level width of 12 clock cycles, and the period remains unchanged from the input DIN.

In the sixth case, the high level time in the input data encoding is longer than N5 clock cycles, and the high level time is directly output without being recognized and processed by the control IC.

In short, the communication method adopted in the data coding communication transmission process can be briefly summarized as follows:

1. for the coded signals with high level time less than the minimum clock period (N1) and greater than the maximum clock period (N5) in data coding, the coded signals belong to invalid coded signals and are directly output without controlling IC identification processing.

2. For an encoding signal in which a high level time is greater than a minimum clock period (N1) and less than an intermediate clock period signal (N3) in data encoding, the control IC recognizes a 0 code (or 1 code). In this case, the following situations are again to be considered: when the high level time in the data coding is close to the minimum clock period (N1), such a coded signal should be recognized as 0 code by the control IC, but due to the short waveform width of the signal, erroneous judgment may occur during the control IC recognition, and meanwhile, in the subsequent long cascade transmission process, as the signal is attenuated, the subsequent control IC may not be correctly recognized, so that the coded signal needs to be output after being processed into coded signals with widths of N2 periods by synchronous shaping, and simultaneously recognized as 0 code by the present control IC. N2 is a value between N1 and N3, for the coded signal which is larger than N1 and smaller than N2 clock cycles, the coded signal is synchronously shaped and processed into coded signals with N2 cycle widths, and then the coded signals are output and are simultaneously identified as 0 code by the control IC; for the coded signal which is larger than N2 and smaller than N3 clock cycles, the signal width is long enough to be effectively identified by the control IC, so the coded signal is directly output without shaping and is simultaneously identified as 0 code by the control IC.

3. For an encoding signal in which a high level time is longer than the intermediate clock period signal (N3) and shorter than the maximum clock period signal (N5) in data encoding, the control IC recognizes 1-code (or 0-code). The following needs to be considered in this case: when the high level time in the data coding is close to the middle clock period (N3), such a coded signal should be recognized as 1 code by the control IC, but due to the short waveform width of the signal, erroneous judgment may occur during the control IC recognition, and meanwhile, in the subsequent long cascade transmission process, as the signal is attenuated, the subsequent control IC may not be correctly recognized, so that the coded signal needs to be synchronously shaped and processed into coded signals with widths of N4 periods, and then output, and simultaneously recognized as 1 code by the present control IC. N4 is a value between N3 and N5, for the coded signal which is larger than N3 and smaller than N4 clock cycles, the coded signal is synchronously shaped and processed into coded signals with N4 cycle widths, and then the coded signals are output and are simultaneously identified as 1 code by the control IC; for the coded signal which is larger than N4 and smaller than N5 clock cycles, the signal width is long enough to be effectively identified by the control IC, so the coded signal is directly output without shaping and is simultaneously identified as 1 code by the control IC.

In the above embodiment, N3 belongs to the threshold values for identifying the 0 code and the 1 code, and the coded signal close to the threshold values is likely to be erroneously determined by the control IC.

In the second embodiment, an interval clock cycle is taken between the minimum clock cycle and the maximum cycle, and the coded signals with high level time greater than the minimum clock cycle and less than the interval cycle in the data coding are identified as 0 codes or 1 codes by the control IC; for the coded signal with high level time larger than interval clock period and smaller than maximum clock period in the data coding, the coded signal is identified as 1 code or 0 code by the control IC; for the coded signal of high level time in interval clock cycle in data coding, it is directly output without control IC identification process. The section clock cycle described here is a buffer section, and the encoded signal having a waveform width in the buffer section is regarded as invalid data and is directly output without control of the IC identification process. Thus, no erroneous judgment exists.

The second embodiment will be described with reference to the first embodiment.

(1) The coded signal with high level time width smaller than N1 clock cycles in the input data coding is directly output without being identified and processed by the control IC.

(2) For the coded signal whose high level time width is greater than N1 clock cycles and less than N2 clock cycles in the input data code, the synchronous shaping process is processed into coded signal whose width is N2 cycles, then the coded signal is output, and at the same time the coded signal is recognized as 0 code or 1 code by the control IC;

(3) for the input data coding, the high-level time width is more than N2 clock cycles, and the coded signal less than N3 clock cycles is directly output without shaping and is simultaneously identified as 0 code or 1 code by the control IC;

(4) for the input data coding, the high-level time width is more than N3 clock cycles, and the coding signal less than N4 clock cycles is directly output without being identified and processed by the control IC;

(5) for the input data coding, the high level time width is larger than N4 clock cycles, and the coded signal which is smaller than N5 clock cycles is synchronously shaped into a signal with the width of N5 cycles and then output; and simultaneously identified as 1 code or 0 code by the control IC chip;

(6) for the input data coding, the high-level time width is larger than N5 clock cycles, and the coded signals smaller than N6 clock cycles are synchronously output without shaping; and is recognized as 1 code or 0 code by the control IC;

(7) for data with high level time width larger than N6 clock periods in the input data codes, the data are directly output without being identified and processed by the control IC;

n1, N2, N3, N4, N5 and N6 in the above description are clock cycles corresponding to the definition of encoding by clock cycles, where N1 is the minimum number of clock cycles, N6 is the maximum number of clock cycles, N1, N2, N3, N4, N5 and N6 in the above description are natural numbers, and N1< N2< N3< N4< N5< N6.

In the second embodiment, the coded signal with the high level time width between N3 and N4 in the data coding is used as the buffer section, and the coded signal with the waveform width in the buffer section is regarded as invalid data and is directly output without controlling the IC identification processing. Therefore, no misjudgment exists, and other processing modes are the same as the first embodiment.

The invention has the following advantages after adopting the mode.

1. The output DOUT synchronizes the output signal coding, keeping the same period as the input DIN, which is essentially different from the present approach. As described in the background, in the prior art, a fixed high level is adopted, and a low level is kept as same as the output terminal DIN, and the signal periods of the output terminal DOUT and the input terminal DIN are different.

2. The state of the input DIN signal is judged, the duty ratio of the codes is selectively changed in a fixed period of the input DIN signal, the unsafe codes are considered to be synchronously processed if attenuation exists, and the codes which are enough safe are not processed if attenuation does not exist.

3. For the inevitable glitch signal at the input DIN, the decoding process is not performed in the control IC by the judgment, and the output is performed without any process.

4. The invention adopts the mode without a synchronous oscillator, only one oscillator structure is needed for processing data refreshing, and all synchronous signal periods are generated by the signal of the input end DIN, thus avoiding the defects generated by double oscillators.

5. The invention has strong anti-interference performance, neglects transmission noise from the source, is very safe and efficient when in cascade use, and greatly reduces the error rate even in the longer cascade transmission process.

The synchronous counter adopted in the invention mainly comprises two modules, one is a common 16-system counter and is controlled by a logic circuit. In conjunction with the first embodiment described above, the logic control circuit operates as follows. As shown in fig. 6, the logic control circuit is explained according to the first embodiment:

the input DIN inputs a high-level pulse signal, and a data code formed by clock cycle definition coding is output from the output DOUT. As shown in connection with the above specific embodiments,

the counter detects the input high level signal time, when the clock period CNT corresponding to the input high level signal time is 8-11, the rising edge falls (i.e. ends) at the 12 th clock period, and when CNT is 12, the B terminal generates a high level pulse.

When the input high level signal time corresponds to the clock period CNT of 2-6, the rising edge falls at the 6 th clock period, and when the input high level signal time corresponds to CNT of 6, the end C generates a high level pulse.

When the clock period CNT corresponding to the input signal is 0, 1, 6, 12, 13, 14, 15, 16, a high-level pulse is generated directly at the D terminal.

It should be understood that the above description is only exemplary of the present invention, and is not intended to limit the scope of the present invention, which is defined by the appended claims.

Claims

1. A single-wire cascade data communication method of an LED control IC is used in the LED control IC of single-wire cascade, a data coding signal is input through an input end DIN of the control IC, is output by an output end DOUT of the control IC and is output to an input end DIN of a next-stage control IC, the data coding signal determines the time width of a high-level signal in each data coding signal through a clock period in the control IC in communication transmission so as to define 0 code and 1 code in data coding, and the method is characterized in that:

when the data codes are output by the output end DOUT, the code period synchronous with the input end DIN is kept, meanwhile, the input data codes are judged, the code period of the input data codes is fixedly kept unchanged by controlling the data codes input by the IC synchronous shaping input end DIN, and the high-level signals corresponding to each data code are shaped to the length convenient for the control IC to identify in cascade in a time synchronous manner.

2. The LED control IC single-wire cascade data communication method according to claim 1, characterized in that: in the data coding communication transmission, the time width of a high-level signal in each data coding signal corresponds to a 0 code and a 1 code in the coding; when defining the code, determining the minimum time width of the high level signal and the maximum time width of the high level signal, and directly outputting the code signal with the high level time smaller than the minimum time width and larger than the maximum time width in the data code without controlling IC identification processing.

3. The LED control IC single-wire cascade data communication method according to claim 2, characterized in that: taking an intermediate critical value between the time width of the minimum high-level signal and the time width of the maximum high-level signal, and identifying the coded signal with the high-level time larger than the minimum time width and smaller than the intermediate critical value in the data coding as a 0 code or a 1 code by the control IC; the control IC recognizes the code signal having a high level time greater than the intermediate threshold value and less than the time width of the maximum high level signal as a 1 code or a 0 code in the data coding.

4. The LED control IC single-wire cascade data communication method according to claim 2, characterized in that: taking an interval time between the time width of the minimum high-level signal and the time width of the maximum high-level signal, and identifying the coded signal with the high-level time larger than the minimum clock width and smaller than the interval time in data coding as a 0 code or a 1 code by the control IC; for the coded signal whose high level time is greater than interval time and less than maximum time width in data coding, the control IC recognizes it as 1 code or 0 code; the coded signal of high level time in interval time in data coding is directly output without controlling IC identification processing.

5. The LED control IC single-wire cascade data communication method according to any one of claims 1 to 4, characterized in that: the method for synchronously shaping the high-level signal corresponding to each data code to the length convenient for the control IC to identify in the cascade adopts the following steps:

(1) for the coded signal with high level time width less than N1 clock cycles in the input data code, the coded signal is directly output without being identified and processed by the control IC;

(4) for the input data coding, the high level time width is larger than N3 clock cycles, and the coded signal which is smaller than N4 clock cycles is synchronously shaped into a signal with the width of N4 cycles and then output; and simultaneously identified as 1 code or 0 code by the control IC chip;

(5) for the input data coding, the high-level time width is larger than N4 clock cycles, and the coded signals smaller than N5 clock cycles are synchronously output without shaping; and is recognized as 1 code or 0 code by the control IC;

(6) the data with more than N5 clock cycles in the input data codes are directly output without being identified and processed by the control IC;

n1, N2, N3, N4 and N5 are clock cycles corresponding to the definition of encoding by clock cycles, wherein N1 is the minimum number of clock cycles, N5 is the maximum number of clock cycles, N1, N2, N3, N4 and N5 are natural numbers, and N1< N2< N3< N4< N5.

6. The LED control IC single-wire cascade data communication method according to any one of claims 1 to 4, characterized in that: the method for synchronously shaping the signal width corresponding to each code in the data codes to the length convenient for control IC identification in cascade adopts the following steps:

(2) for the input data coding, the high level time width is larger than N1 clock cycles, and the synchronous shaping of the coded signal smaller than N2 clock cycles is processed into the coded signal with the width of N2 cycles, then the coded signal is output, and the coded signal is identified as 0 code or 1 code by the control IC;