CN112987690B - Espi controller verification system and method - Google Patents
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
The invention discloses a system and a method for verifying an espi controller, wherein the system comprises an on-chip host, a controller module and a communication model for simulating an off-chip host, the controller module comprises at least one espi controller, and the method comprises the following steps: the communication model is to: generating corresponding communication data based on a preset communication handshake protocol; the on-chip host is used for: processing the communication data based on the communication handshake protocol to obtain corresponding result data; the controller module is configured to: and transmitting the communication data generated by the communication model to the on-chip host, and returning result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data. The method and the device can avoid the situation that normal data interaction cannot be realized by the on-chip host and the off-chip host due to the fact that the controller module has faults.
Description
Technical Field
The invention relates to the technical field of device function verification, in particular to an espi controller verification system and method.
Background
In the prior art, for an espi controller that implements espi (enhanced serial peripheral interface) bus control, it is generally required to receive communication data of an off-chip host, transmit the received communication data to an on-chip host through an espi bus for processing, and transmit result data obtained by the on-chip host processing the communication data to the off-chip host through the espi bus to complete data interaction between the off-chip host and the on-chip host. Therefore, if the espi controller fails, it may cause the off-chip host and the on-chip host to fail to realize normal data interaction through the espi controller.
Disclosure of Invention
The invention aims to provide an espi controller verification system and method, which can avoid the situation that normal data interaction cannot be realized by an on-chip host and an off-chip host due to the fact that a controller module has a fault, and can simulate a communication interface part of the on-chip host and the off-chip host only through a communication model without depending on or constructing a complex off-chip host model, so that the complexity of the whole simulation system is reduced.
In order to achieve the above purpose, the invention provides the following technical scheme:
an espi controller validation system comprising an on-chip host, a controller module, and a communication model that simulates an off-chip host, the controller module comprising at least one espi controller, wherein:
the communication model is to: generating corresponding communication data based on a preset communication handshake protocol;
the on-chip host is used for: processing the communication data based on the communication handshake protocol to obtain corresponding result data;
the controller module is configured to: and transmitting the communication data generated by the communication model to the on-chip host, and returning result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data.
Preferably, the controller module includes a first epsilon controller and a second espi controller, an espi bus output of the first espi controller is connected to an espi bus input of the second espi controller, and an espi bus input of the first espi controller is connected to an espi bus output of the second espi controller, wherein:
the first espi controller to: outputting the communication data to the second espi controller via an espi bus, and transmitting the result data to the communication model;
the second espi controller to: and outputting the result data to the first espi controller through an espi bus, and transmitting the communication data to the on-chip host.
Preferably, the first espi controller and the second espi controller are the same espi controller with the function to be verified.
Preferably, the first espi controller or the second espi controller is an espi controller of a function to be verified.
Preferably, the communication model and the first espi controller, and the on-chip host and the second espi controller are connected by an AHB bus, so as to realize corresponding data transmission based on the AHB bus.
Preferably, the communication model, the on-chip host and the controller module are all included in the same bare metal program.
Preferably, the on-chip host is an ARM.
An espi controller verification method is applied to an espi controller verification system, the espi controller verification system comprises an on-chip host, a controller module and a communication model for simulating an off-chip host, and the controller module comprises at least one espi controller; the method comprises the following steps:
the communication model generates corresponding communication data based on a preset communication handshake protocol, and the controller module transmits the communication data generated by the communication model to the on-chip host;
the on-chip host processes the communication data based on the communication handshake protocol to obtain corresponding result data, and the controller module returns the result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data and the corresponding result data generated by the communication model.
The invention provides an espi controller verification system and a method, the system comprises an on-chip host, a controller module and a communication model for simulating an off-chip host, the controller module comprises at least one espi controller, wherein: the communication model is to: generating corresponding communication data based on a preset communication handshake protocol; the on-chip host is used for: processing the communication data based on the communication handshake protocol to obtain corresponding result data; the controller module is configured to: and transmitting the communication data generated by the communication model to the on-chip host, and returning result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data. The method comprises an on-chip host, a controller module containing an espi controller to be subjected to functional verification and a communication model simulating an off-chip host, wherein the controller module can realize data interaction between the on-chip host and the communication model, so that the functional verification of the controller module is realized through a data interaction result, and whether the controller module has a fault is determined, so that the data interaction of the on-chip host and the off-chip host in practical application is realized based on the controller module when the controller module has no fault, the condition that the on-chip host and the off-chip host cannot realize normal data interaction due to the fault of the controller module is avoided, a complex off-chip host model does not need to be relied or constructed, only a communication interface part of the off-chip host and the on-chip host is simulated through the communication model, and the complexity of the whole simulation system is reduced.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a first structure of an esii controller verification system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a second structure of an esii controller verification system according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for verifying an espi controller according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an espi controller verification system, as shown in fig. 1, which may include an on-chip host 11, a controller module 12, and a communication model 13 simulating an off-chip host, where the controller module 12 includes at least one espi controller, where:
a communication model 13 for: generating corresponding communication data based on a preset communication handshake protocol;
an on-chip host 11 configured to: processing the communication data based on a communication handshake protocol to obtain corresponding result data;
a controller module 12 for: and transmitting the communication data generated by the communication model 13 to the on-chip host 11, and returning result data obtained by the on-chip host 11 to the communication model 13 so as to realize the functional verification of the controller module 12 based on the communication data generated by the communication model 13 and the corresponding result data.
The off-chip host generally refers to an off-chip Central Processing Unit (CPU), and the corresponding on-chip host generally refers to an on-chip CPU, and data interaction between the two is realized through an espi controller. In order to avoid the problem that the data interaction between the on-chip host and the off-chip host cannot be normally realized due to the failure of the controller module, before the data interaction between the on-chip host and the off-chip host is realized by the controller module, the application can verify whether the controller module can normally realize the function which the controller module needs, namely the function of the data interaction between the on-chip host and the off-chip host, specifically, the application can set a communication model which can simulate the off-chip host, the communication model can be realized by a program and only needs to generate communication data based on a communication handshake protocol, transmit the communication data to the controller module and receive result data returned by the controller module, wherein the communication handshake protocol has the same principle with the corresponding concept in the prior art, and simply speaking, the transmission of any actual application information between communication devices is always accompanied with the transmission of some control information, the communication equipment comprises an on-chip host and a communication model, after the communication handshake protocol required to be followed between the on-chip host and the communication model is determined, the communication model can generate an address and data required to be sent to the on-chip and an instruction code indicating corresponding operation based on the communication handshake protocol, namely communication data, and the on-chip host can process the communication data according to the communication handshake protocol after receiving the communication data to obtain corresponding data as result data, if the result data finally returned to the communication model is the same as the data obtained by processing the communication data according to the communication handshake protocol, and if the controller module is determined to have a fault, the controller module is determined to pass the functional verification, the controller module does not have a fault, and data interaction between the on-chip host and the off-chip host can be realized based on the controller module, otherwise, the controller module has a fault, data interaction between the on-chip host and the off-chip host cannot be realized based on the controller module, and corresponding prompt information can be output after the controller module is determined to have a fault, so that external personnel can be instructed to intervene and carry out corresponding operations such as fault repair.
The method comprises an on-chip host, a controller module containing an espi controller to be subjected to function verification and a communication model simulating an off-chip host, wherein the controller module can realize data interaction between the on-chip host and the communication model, so that the function verification of the controller module is realized through a data interaction result, and whether the controller module has a fault is determined.
In the esii controller verification system provided in the embodiment of the present invention, the controller module may include a first epsilon controller and a second esii controller, an esii bus output of the first esii controller is connected to an esii bus input of the second esii controller, an esii bus input of the first esii controller is connected to an esii bus output of the second esii controller, where:
a first espi controller to: outputting the communication data to a second espi controller through the espi bus, and transmitting the result data to the communication model;
a second espi controller to: and outputting the result data to the first espi controller through the espi bus, and transmitting the communication data to the on-chip host.
The controller module in the application can comprise two espi controllers which are respectively called a first espi controller (espi controller 1) and a second espi controller (espi controller 2), the espi bus of the espi controller 1 is in cross connection with the espi bus of the espi controller 2, namely the espi bus output of the espi controller 1 is connected with the espi bus input of the espi controller 2, and meanwhile, the espi bus input of the espi controller 1 is connected with the espi bus output of the espi controller 2 so as to be connected, namely communication data generated by the communication model is sent to the on-chip host computer, and result data returned by the on-chip host computer is also sent to the communication model; specifically, communication data generated by the communication model is written into an espi controller 1, the espi controller 1 sends the communication data out of an espi bus, an espi controller 2 receives the communication data of the espi bus, an on-chip host receives the communication data and generates result data according to a communication handshake protocol of the communication model, the result data is written into the espi controller 2, and the espi controller 2 analyzes the result data and sends the result data to the espi controller 1 through the espi bus to provide the result data for the communication model, so that a preliminary handshake communication signal between the communication model and the on-chip host is completed, and the functions and the time sequence of verifying interfaces of the espi controller and the espi bus are achieved. The communication data may include an address, data, and an instruction code, and the corresponding espi controller 1 may parse the address, data, and instruction code from the espi bus. According to the method and the device, the two espi controllers are connected in a cross mode, and the corresponding data can be transmitted quickly. In addition, to ensure differentiation of different espi controllers, different espi controllers have different base addresses.
It should be noted that, in the embodiment of the present application, the first espi controller and the second espi controller may be identical espi controllers with functions to be verified, at this time, if the function verification of the controller module passes, it is indicated that both the two espi controllers included in the controller module can normally realize corresponding functions, and otherwise, it is indicated that at least one espi controller included in the controller module cannot normally realize corresponding functions; in an embodiment, the first espi controller or the second espi controller in the controller module may be set as the espi controller with the function to be verified, and the other espi controller is the espi controller determined not to have a fault, at this time, if the function verification of the controller module passes, it indicates that the espi controller with the function to be verified included in the controller module can normally realize the corresponding function, otherwise, it indicates that the espi controller with the function to be verified included in the controller module cannot normally realize the corresponding function. Therefore, the flexible setting of the controller modules can be realized according to different requirements in different scenes, the scene requirements are met, and the functional verification of the corresponding espi controller is effectively realized.
In the esii controller verification system provided in the embodiment of the present invention, the communication model and the first esii controller, and the on-chip host and the second esii controller may be connected by an AHB (Advanced High Performance Bus, which is used for Bus interconnection between different modules in a chip) Bus, so as to implement corresponding data transmission based on the AHB Bus; specifically, the communication model can write the generated communication data into the espi controller 1 through the AHB bus, and after the on-chip host generates the result data, the result data can be written into the espi controller 2 through the AHB bus, so that the reliable transmission of the corresponding data can be realized through the AHB bus. In addition, the on-chip host can be specifically an Advanced RISC Machine (RISC microprocessor), so that various functions required to be realized by the on-chip host can be effectively realized.
It should be noted that, in the embodiment of the present application, the communication model, the on-chip host, and the controller module may all be included in the same bare metal program, so that data interaction among the communication model, the on-chip host, and the controller module can be achieved with the highest efficiency.
In a specific implementation manner, a schematic structural diagram of the esii controller verification system provided in the embodiment of the present invention may be as shown in fig. 2 (an on-chip CPU is an on-chip host), and a specific implementation process may include:
1: in the same bare computer program, a communication model simulating an off-chip host is realized, the communication model generates an address, data and a corresponding instruction code which are sent to the on-chip according to a communication handshake protocol of the off-chip host and the on-chip host to be communication data, the generated communication data is written into an espi controller 1 through an AHB bus, and the espi controller 1 analyzes the address, the data and the instruction code and sends the address, the data and the instruction code out of the espi bus;
2: the espi bus of the espi controller 1 is in cross connection with the espi bus of the espi controller 2, namely the espi bus output of the espi controller 1 is connected with the espi bus input of the espi controller 2, and meanwhile, the espi bus input of the espi controller 1 is connected with the espi bus output of the espi controller 2, so that connection is realized, that is, the data of the off-chip host is sent to the on-chip host, and the data returned by the on-chip host is also sent to the off-chip host;
3: the espi controller 2 receives espi bus data, the on-chip host receives communication data through an AHB bus, corresponding result data are generated according to a communication handshake protocol with the off-chip host, the result data are written into the espi controller 2 through the AHB bus, the espi controller 2 sends the result data to the espi controller 1 through the espi bus after being analyzed, and therefore preliminary handshake communication signals between the external host and the internal host are completed, and functions and time sequences of the espi controller and an espi bus interface are verified.
The espi controller receives communication data of the off-chip host and transmits the communication data to the on-chip host for processing; meanwhile, result data generated by the on-chip host is sent to the off-chip host through an espi bus, and data interaction between the off-chip host and the on-chip host is completed; in the simulation environment, an off-chip host communication model is needed to simulate a physical off-chip host to complete the sending of communication data of the host, namely, the functions of generating the communication data and sending the communication data to an espi bus and the like are realized, further, the communication with the on-chip host is realized, and the function of the espi controller is verified. Specifically, the method adopts a communication model simulating an off-chip host in the same bare computer program, generates sent communication data, analyzes the communication data through an espi controller and sends the communication data to an espi bus, simulates a bus interface signal on the side of the off-chip host, cross-interconnects the bus interface signal with the on-chip espi bus and sends the bus interface signal to the on-chip host for receiving and processing, so as to simulate the communication of the on-chip and the off-chip hosts, thereby verifying the function and the interface signal (espi bus interface function) of the espi controller in a simulation environment, and simulating actual physical communication in the simulation environment to achieve the purpose of function simulation.
The embodiment of the invention also provides an espi controller verification method which is applied to an espi controller verification system, wherein the espi controller verification system comprises an on-chip host, a controller module and a communication model for simulating the off-chip host, and the controller module comprises at least one espi controller; as shown in fig. 3, the espi controller validation method may include:
s11: the communication model generates corresponding communication data based on a preset communication handshake protocol, and the controller module transmits the communication data generated by the communication model to the on-chip host;
s12: the on-chip host processes the communication data based on the communication handshake protocol to obtain corresponding result data, and the controller module returns the result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data.
It should be noted that for the description of the relevant parts in the esi controller verification method provided in the embodiment of the present invention, reference is made to the detailed description of the corresponding parts in the esi controller verification system provided in the embodiment of the present invention, and details are not described herein again. In addition, parts of the technical solutions provided in the embodiments of the present invention that are consistent with the implementation principles of the corresponding technical solutions in the prior art are not described in detail, so as to avoid redundant description.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. An espi controller validation system comprising an on-chip host, a controller module and a communication model that simulates an off-chip host, the controller module comprising at least one espi controller, wherein:
the communication model is to: generating corresponding communication data based on a preset communication handshake protocol;
the on-chip host is used for: processing the communication data based on the communication handshake protocol to obtain corresponding result data;
the controller module is configured to: transmitting the communication data generated by the communication model to the on-chip host, and returning result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data;
the controller module comprises a first epsilon controller and a second espi controller, an espi bus output of the first espi controller is connected with an espi bus input of the second espi controller, and an espi bus input of the first espi controller is connected with an espi bus output of the second espi controller, wherein:
the first espi controller to: outputting the communication data to the second espi controller via an espi bus, and transmitting the result data to the communication model;
the second espi controller to: outputting the result data to the first espi controller through an espi bus, and transmitting the communication data to the on-chip host;
the communication model and the first espi controller and the on-chip host and the second espi controller are connected through an AHB bus so as to realize corresponding data transmission based on the AHB bus;
the communication model, the on-chip host and the controller module are all included in the same bare metal program;
the process of the controller module for realizing the function verification specifically comprises the following steps: in the same bare computer program, a communication model generates an address, data and a corresponding command code which are sent to the chip according to a communication handshake protocol of an off-chip host and an on-chip host as communication data, the generated communication data is written into a first espi controller through an AHB bus, the first espi controller analyzes the address, the data and the corresponding command code and sends the communication data from the espi bus, a second espi controller receives the communication data of the espi bus, the on-chip host receives the communication data through the AHB bus between the on-chip host and the second espi controller, the second espi controller sends the communication data to the first espi controller, generates corresponding result data according to the communication handshake protocol of the off-chip host and writes the result data into the second espi controller through the AHB bus, the second espi controller analyzes the result data and sends the result data to the first espi controller through the espi bus to finish a primary handshake communication signal between the external host and the internal host, the function and the time sequence of the espi controller and the espi bus interface are verified.
2. The system of claim 1, wherein the first espi controller and the second espi controller are the same function-to-be-verified espi controller.
3. The system of claim 1, wherein the first espi controller or the second espi controller is an espi controller of a function to be verified.
4. The system of claim 2 or 3, wherein the on-chip host is an ARM.
5. The espi controller verification method is applied to an espi controller verification system, the espi controller verification system comprises an on-chip host, a controller module and a communication model for simulating an off-chip host, and the controller module comprises at least one espi controller; the method comprises the following steps:
the communication model generates corresponding communication data based on a preset communication handshake protocol, and the controller module transmits the communication data generated by the communication model to the on-chip host;
the on-chip host processes the communication data based on the communication handshake protocol to obtain corresponding result data, and the controller module returns the result data obtained by the on-chip host to the communication model so as to realize the functional verification of the controller module based on the communication data generated by the communication model and the corresponding result data;
the controller module comprises a first epsilon controller and a second espi controller, an espi bus output of the first espi controller is connected with an espi bus input of the second espi controller, and an espi bus input of the first espi controller is connected with an espi bus output of the second espi controller, wherein: the first espi controller is used for outputting the communication data to the second espi controller through an espi bus and transmitting the result data to the communication model; the second espi controller is used for outputting the result data to the first espi controller through an espi bus and transmitting the communication data to the on-chip host;
the communication model and the first espi controller and the on-chip host and the second espi controller are connected through an AHB bus so as to realize corresponding data transmission based on the AHB bus; and the communication model, the on-chip host and the controller module are all included in the same bare metal program;
the implementation process of the functional verification specifically includes: in the same bare computer program, a communication model generates an address, data and a corresponding command code which are sent to the chip according to a communication handshake protocol of an off-chip host and an on-chip host as communication data, the generated communication data is written into a first espi controller through an AHB bus, the first espi controller analyzes the address, the data and the corresponding command code and sends the communication data from the espi bus, a second espi controller receives the communication data of the espi bus, the on-chip host receives the communication data through the AHB bus between the on-chip host and the second espi controller, the second espi controller sends the communication data to the first espi controller, generates corresponding result data according to the communication handshake protocol of the off-chip host and writes the result data into the second espi controller through the AHB bus, the second espi controller analyzes the result data and sends the result data to the first espi controller through the espi bus to finish a primary handshake communication signal between the external host and the internal host, the function and timing of verifying the espi controller and the espi bus interface are achieved.
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| CN111198832A (en) * | 2020-01-02 | 2020-05-26 | 联想(北京)有限公司 | Processing method and electronic equipment |
| CN211124025U (en) * | 2020-03-17 | 2020-07-28 | 北京国科天迅科技有限公司 | Multi-protocol simulation simulator |
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