CN112953535B - Gain error calibration device and method for analog-digital converter with segmented structure - Google Patents
Gain error calibration device and method for analog-digital converter with segmented structure Download PDFInfo
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Abstract
A gain error calibration device and method for an analog-to-digital converter with a segmented structure comprises the following steps: flash type analog-to-digital converter, electric capacity type digital-to-analog converter, dynamic comparator and successive approximation type analog-to-digital converter, wherein: the input end of the flash analog-to-digital converter receives an input signal and outputs a thermometer code quantization result to the capacitive analog-to-digital converter, the capacitive analog-to-digital converter outputs a residual voltage to the dynamic comparator after being set, the dynamic comparator outputs a comparison result to the successive approximation analog-to-digital converter after comparing the input voltage with the reference voltage, and digital-to-analog conversion codes, namely final calibration control words, are obtained after multiple approximation. The invention shares a core module with the main circuit and automatically adjusts the reference voltage value in the Flash ADC according to the actual size of the parasitic capacitance; and when the power is on, the calibration mode is enabled, and two direct current calibration signals are input, so that the calibration can be completed, and the operation is simple.
Description
Technical Field
The invention relates to the technology in the field of analog-to-digital converters, in particular to gain error calibration of a segmented structure analog-to-digital converter (Subranging ADC).
Background
The traditional Flash analog-to-digital converter (Flash ADC) has the characteristic of high speed, but the precision is limited, and the power consumption and the area are exponentially increased along with the increase of the precision due to the full parallel mode of the Flash ADC. Successive approximation analog-to-digital converter (SAR ADC) has the characteristics of higher energy efficiency, smaller area and higher precision, but has lower speed. The segmented structure analog-to-digital converter is generally composed of two stages of ADCs, a Flash ADC and an SAR ADC are respectively used as a first-stage coarse quantizer and a second-stage fine quantizer, the characteristics of the first-stage coarse quantizer and the second-stage fine quantizer are combined, and high-precision high-speed analog-to-digital conversion and a large dynamic range are achieved with low power consumption. However, in the Subranging ADC, after the quantization result obtained by the first-stage Flash ADC is set, the residual voltage may exceed the quantization range of the second-stage SAR ADC due to the existence of the gain error, so that the quantization result of the SAR ADC is affected, and the overall performance of the ADC is reduced.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a device and a method for calibrating the gain error of an analog-digital converter with a segmented structure, wherein the device and the method share a core module with a main circuit and automatically adjust the reference voltage value in a Flash ADC according to the actual size of a parasitic capacitor; and when the power is on, the calibration mode is enabled, and two direct current calibration signals are input, so that the calibration can be completed, and the operation is simple.
The invention is realized by the following technical scheme:
the invention relates to a gain error calibration device of an analog-digital converter with a segmented structure, which comprises: flash type analog-to-digital converter, capacitive type digital-to-analog converter (CDAC), dynamic comparator and successive approximation type analog-to-digital converter, wherein: the input end of the flash analog-to-digital converter receives an input signal and outputs a thermometer code quantization result to the capacitive analog-to-digital converter, the capacitive analog-to-digital converter outputs a residual voltage to the dynamic comparator after being set, the dynamic comparator outputs a comparison result to the successive approximation analog-to-digital converter after comparing the input voltage with the reference voltage, and digital-to-analog conversion codes, namely final calibration control words, are obtained after multiple approximation.
The capacitance type digital-to-analog converter comprises: a Most Significant Bit (MSB) portion and a Least Significant Bit (LSB) portion, wherein: MSB is controlled by the quantized result of thermometer code and each bit has a capacitance of C F Total capacitance of M x C F (ii) a LSB is controlled by D/A conversion code and total capacitance is C s The total capacitance of the capacitive digital-to-analog converter is C tot ＝M*C F +C s 。
The resistor R in the resistor string for generating reference voltage by the flash analog-to-digital converter 1 /R 2 Ratio of C F /C S 。
The invention relates to a method for calibrating gain error of an analog-digital converter with a segmented structure based on the device, which feeds back and calibrates a Flash ADC reference voltage value through a setting result of a high-order capacitor controlled by a Flash ADC output result in a capacitor array, and specifically comprises the following steps: after the ADC samples and calibrates an input signal, the Flash ADC starts to work firstly, and an M-bit thermometer code is generated and fed back to a CDAC set; and then the SAR ADC starts to work, and calibration control words are generated by comparing the reference voltage output by the resistor string with the residual voltage of the CDAC through the SAR logic module, so that the reference voltage in the Flash ADC is adjusted to realize error calibration.
Technical effects
The invention integrally solves the problem that the second-stage ADC cannot work normally due to gain errors caused by parasitic capacitance of the CDAC output end in the Subranging ADC. Due to the fact that parasitic capacitance of the CDAC output end changes under different processes and in layout design, and a certain difference exists between parasitic capacitance values of simulation and a chip circuit, a determined value cannot be obtained. Therefore, the dynamic calibration scheme of the present invention can achieve calibration within a large reasonable range.
Compared with the prior art, the invention has the advantages that the CDAC module, the dynamic comparator module and the SAR logic module of the main circuit are uniquely multiplexed, the area of the calibration circuit is greatly reduced, and the calibration can be realized only by adding two additional resistor strings and a small amount of digital circuits, so that the additional area and the power consumption are reduced to the lowest.
Drawings
FIG. 1 is a schematic diagram of the present invention;
FIG. 2 is a schematic diagram of a basic architecture of a conventional FLASH-SAR Subranging ADC;
in the figure: (a) is a traditional FLASH ADC, (b) is a structural diagram of a Subranging ADC;
FIG. 3 is a schematic illustration of errors in the CDAC build;
FIG. 4 is a digital logic diagram illustrating calibration mode LSB set hold;
FIG. 5 is a graph of signal change during calibration;
FIG. 6 is a graph of ADC output spectrum results before and after calibration;
(a) is the ADC output spectrum before calibration, and (b) is the ADC output spectrum after calibration.
Detailed Description
As shown in fig. 1 and fig. 2, the present embodiment relates to a gain error calibration apparatus for an analog-to-digital converter with a segmented structure, which includes: 3-bit flash analog-to-digital converter, 11-bit successive approximation analog-to-digital converter, sampling switch, capacitance type digital-to-analog converter (CDAC) and dynamic comparator, wherein: the input end of the flash analog-to-digital converter receives an input signal and outputs a 7-bit thermometer code quantization result to the capacitive analog-to-digital converter, the capacitive analog-to-digital converter outputs a residual voltage to the dynamic comparator after being set, the dynamic comparator outputs a comparison result to the successive approximation analog-to-digital converter after comparing the input voltage with the reference voltage, and digital-to-analog conversion codes, namely final calibration control words, are obtained after multiple approximation.
The capacitance digital-to-analog converter, the dynamic comparator and the successive approximation logic module are core modules shared with the main circuit.
Each bit capacitor C of the Most Significant Bit (MSB) part in the capacitor type digital-to-analog converter F Total capacitance C of the lowest order (LSB) part of 2080Cu S ＝2240Cu。
In the resistance string for generating the reference voltage in the flash type analog-to-digital converter, the resistance ratio is 13R/14R.
The embodiment relates to a gain error calibration method of the device, which comprises the following steps:
enabling a calibration signal cali _ en, enabling the chip to enter a calibration mode, and inputting full swing amplitude VDD and GND signals at an ADC differential input end. The dynamic comparator in the successive approximation type analog-to-digital converter SAR ADC has two pairs of inputs, one pair of inputs is connected to CDAC, the other pair of inputs is connected to GND when cali _ en is not enabled, a reference voltage value generated by a resistor string is switched in after the cali _ en is enabled, and the value ratio of the resistor string is the same as the ratio of the resistor string used in the Flash ADC.
The resistance value in the resistor string only needs to satisfy the proportionality coefficient of the quantization ranges of the Flash ADC and the SAR ADC, and corresponding adjustment can be made in consideration of the overall power consumption and the speed of the system.
Step two, the Flash ADC logic module outputs a setting control word, the MSB capacitor at the positive end is set to GND from the reference voltage VREF, and the MSB capacitor at the negative end is set from GNDTo VREF, the voltage variation at two ends is theoretically
However, because of the parasitic capacitance of CDAC, as shown in FIG. 3, the actual voltage variation is
I.e. the variation is smaller than the theoretical calculation.
Step three, as shown in fig. 5, the SAR ADC portion starts to work, and the dynamic comparator will compare the CDAC output signal with the magnitude of the accessed reference voltage value. As described in step two, because of the influence of the parasitic capacitance, the initial state of the CDAC output signal is certainly smaller than the reference voltage, so the comparator outputs a high level in the first comparison period, and at the same time, the SAR logic stores the comparison result and feeds the comparison result back to the variable resistor array Rvar, and a resistor is connected to the original resistor string to reduce the output reference voltage. In addition, the LSB partial capacitance setting is guaranteed to be kept unchanged through the calibration logic module, and the CDAC output is kept unchanged.
And step four, in the second comparison period, the dynamic comparator compares the adjusted new reference voltage value with the magnitude of the CDAC output signal. The invention multiplexes the sequential logic circuit of the main circuit, so 13 comparison periods are total, the three operations of the steps are repeated, when the SAR logic output is high, a resistor is continuously connected for adjusting the reference voltage, the cycle is repeated until the reference voltage value is less than the CDAC output voltage, the SAR logic output is low, and the calibration is finished.
Because the error range can be actually estimated, taking this description as an example, the range of the adjusting resistor calculated according to the redundant bit range and the parasitic capacitance value of the SAR is approximately 18.4R-21.6R, so that more accurate calibration can be completed by adjusting the resistance values of Rv1-Rv5 resistors (12R/4R/2R/1R/0.5R) in the resistor array and using 6-bit control words; under other occasions, the output control digit number of the calibration circuit can be adjusted according to actual requirements, and the resistance value in the variable resistor array is adjusted to realize calibration with different accuracies and calibration ranges.
Preferably, before the SAR logic is reset, the output is saved in a register, and the output of the register is used for controlling a variable resistor array in the Flash ADC and adjusting the output reference voltage. Therefore, the foreground calibration is completed, the calibration mode can be closed, the test signal is input, and the ADC works normally.
Through simulation comparison, as shown in fig. 6, the realizability and correctness of the calibration scheme can be verified, for the 14-bit Subranging ADC in fig. 2, without calibration, the SNDR is 26.45dB, the SFDR is 33.14dB, the valid bit is 4.1bit, and a large number of harmonics exist, after calibration, the SNDR is 79.93dB, the SFDR is 91.29dB, and the valid bit is 12.98 bit. The comparison shows that before the calibration is not carried out, only the Flash ADC works normally, the output of the SAR ADC is basically wrong, the whole ADC works in an abnormal state, and the function of the ADC is recovered to be normal after the calibration.
According to the calibration circuit structure of the segmented analog-to-digital converter, calibration signals are input, and according to the setting condition that the first-stage Flash ADC outputs feedback to the CDAC, calibration control words are obtained by means of a circuit module of the second-stage SAR ADC, so that the calibration of gain errors is achieved.
After the Cadence simulation, the power-on, calibration and working stages of the slave chip are simulated, so that the SNDR of the calibrated ADC performance is 79.93dB, and the SFDR is 91.29 dB. According to the method, two important indexes, namely SNDR and SFDR, of the ADC with the segmented structure are improved through on-chip calibration, so that the calibration complexity is reduced, and the calibration effectiveness is improved.
The foregoing embodiments may be modified in many different ways by those skilled in the art without departing from the spirit and scope of the invention, which is defined by the appended claims and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (4)
1. A gain error calibration apparatus for an analog-to-digital converter with a segmented structure, comprising: flash type analog-to-digital converter, electric capacity type digital-to-analog converter, dynamic comparator and successive approximation type analog-to-digital converter, wherein: the input end of the flash analog-to-digital converter receives an input signal and outputs a thermometer code quantization result to the capacitive analog-to-digital converter, the capacitive analog-to-digital converter outputs a residual voltage to the dynamic comparator after being set, the dynamic comparator compares the input voltage with a reference voltage and outputs a comparison result to the successive approximation analog-to-digital converter, and digital-to-analog conversion codes, namely final calibration control words, are obtained after multiple approximations;
the gain error calibration comprises the following steps: the method comprises the following steps of feeding back and calibrating a reference voltage value of the Flash ADC through a setting result of a high-order capacitor controlled by an output result of the Flash ADC in a capacitor array, wherein the method specifically comprises the following steps: after the ADC samples and calibrates an input signal, the Flash ADC starts to work firstly, and an M-bit thermometer code is generated and fed back to a CDAC set; and then the SAR ADC starts to work, and by comparing the reference voltage output by the resistor string with the residual voltage of the CDAC, a calibration control word is generated by means of the SAR logic module, so that the reference voltage in the Flash ADC is adjusted to realize error calibration.
2. The gain error calibration device of claim 1, wherein the capacitive dac, the dynamic comparator, and the successive approximation logic block are core blocks shared by the main circuit.
3. The apparatus as claimed in claim 1, wherein the capacitive dac comprises: a most significant portion and a least significant portion, wherein: MSB is controlled by the quantized result of thermometer code and each bit has a capacitance of C F Total capacitance of M x C F (ii) a LSB is controlled by D/A conversion code and total capacitance is C S The total capacitance of the capacitive digital-to-analog converter is C tot ＝M*C F +C S 。
4. The apparatus of claim 1, wherein the flash analog-to-digital converter generates a reference voltage in a resistor string, and wherein the resistor R is a resistor R in the resistor string 1 /R 2 Ratio of C F /C S 。
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| CN113364461B (en) * | 2021-06-24 | 2024-05-03 | 苏州磐启微电子有限公司 | Analog-to-digital conversion calibration method and system for chip to be tested |
| CN114326900A (en) * | 2021-12-29 | 2022-04-12 | 华中科技大学 | High-precision adjustable reference voltage generation circuit |
| CN114337671B (en) * | 2022-01-06 | 2024-09-03 | 清华大学 | Analog-to-digital conversion circuit and electronic equipment |
| CN116248118B (en) * | 2023-02-03 | 2024-10-18 | 贵州振华风光半导体股份有限公司 | Error calibration circuit and analog-to-digital conversion system |
| EP4391389A1 (en) * | 2023-06-01 | 2024-06-26 | Hangzhou Vango Technologies, Inc. | Analog-to-digital converter integrated with reference voltage generation, and calibration method |
| CN117560001A (en) * | 2023-10-30 | 2024-02-13 | 隔空微电子(深圳)有限公司 | Digital calibration method and device in high-precision successive approximation type SARADC and analog-to-digital converter |
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