CN112888155B - Circuit board, circuit board via hole optimization method, electronic device and storage medium - Google Patents

Abstract

The application provides a circuit board and a via hole optimization method thereof, wherein the circuit board comprises: a first circuit layer and a second circuit layer; a first dielectric layer disposed between the first circuit layer and the second circuit layer; the through hole penetrates through the first dielectric layer and is electrically connected with the first circuit layer and the second circuit layer, and a first anti-bonding pad is arranged at one end, close to the first circuit layer, of the through hole in a surrounding mode; the second dielectric layer is arranged on one side of the first circuit layer, which is far away from the second circuit layer; the first grounding layer is arranged on one side of the second dielectric layer far away from the first circuit layer, and a first opening is formed in the area of the first grounding layer corresponding to the first anti-bonding pad. This application sets up the opening through the region that corresponds anti-pad on the ground plane, can avoid forming parasitic capacitance between ground plane and the via hole to improve the discontinuous problem of multilayer PCB via hole impedance to a certain extent, simultaneously, guarantee PCB intensity, reduce manufacturing cost, and do not occupy too much PCB overall arrangement space.

Description

Circuit board, circuit board via hole optimization method, electronic device and storage medium

Technical Field

The application relates to the field of printed circuit boards, in particular to a circuit board and a circuit board via hole optimization method.

Background

At present, electronic devices such as mobile phones, notebook computers, communication modules, and electronic components such as memory cards are usually multi-layer PCBs (Printed Circuit boards). In a multilayer PCB, vias are typically provided to allow signal communication between different layers. In the high frequency domain, via stub can cause via impedance discontinuity, or, cause parasitic capacitance or resistance, which will seriously affect the transmission of high-speed signals, causing signal integrity problems, and also causing reflection problems to the radio frequency link.

Along with the improvement of the communication bandwidth and the data transmission rate in the 5G era, the radio frequency is improved to a millimeter wave frequency band, and the problem of impedance discontinuity of the via hole is more and more prominent.

In the prior art, there are two solutions for optimizing the impedance of the via hole, and the via hole is subjected to back drilling treatment or a U-shaped via hole structure is formed. However, the back drilling process requires reserving all the space from the corresponding layer to the bottom layer in the PCB, and the holes formed by the back drilling can reduce the strength of the PCB, increase the PCB manufacturing process and increase the manufacturing cost; the U-shaped via hole structure has a limit requirement on the length of the via hole stub, and the newly added via hole can increase the layout space of the PCB.

Disclosure of Invention

An object of the embodiments of the present application is to provide a method for optimizing via holes of a circuit board and a circuit board, so as to improve the problem of impedance discontinuity of via holes of a multilayer PCB in the prior art, and simultaneously, ensure the strength of the PCB, without increasing the manufacturing processes of the PCB, reduce the manufacturing cost, and occupy too much layout space of the PCB.

The application provides a circuit board, includes: a first circuit layer and a second circuit layer; a first dielectric layer disposed between the first circuit layer and the second circuit layer; a via hole penetrating through the first dielectric layer and electrically connecting the first circuit layer and the second circuit layer, wherein a first anti-pad is arranged around one end of the via hole close to the first circuit layer; the second dielectric layer is arranged on one side, far away from the second circuit layer, of the first circuit layer; the first grounding layer is arranged on one side of the second dielectric layer far away from the first circuit layer, and a first opening is formed in the area, corresponding to the first anti-bonding pad, of the first grounding layer.

The application provides a circuit board sets up the opening through the region that corresponds first anti-pad at first ground plane, can avoid forming parasitic capacitance between first ground plane and the via hole to improve the discrete problem of multilayer PCB via hole impedance to a certain extent, simultaneously, guarantee PCB intensity, reduce manufacturing cost, and do not occupy too much PCB overall arrangement space. In addition, aiming at the PCB with the same thickness lamination, the length of the high-speed signal routing is ensured to be unchanged, and the structure of the high-speed signal routing is also ensured to be unchanged.

In one embodiment, the size of the first opening is the same as the size of the first anti-pad.

In one embodiment, the circuit board further comprises a third dielectric layer disposed on a side of the second circuit layer away from the first circuit layer; the second grounding layer is arranged on one side of the third dielectric layer far away from the second circuit layer; and a second anti-bonding pad is arranged at one end, close to the second circuit layer, of the via hole, and a second opening is formed in the area, corresponding to the second anti-bonding pad, of the second ground layer.

The application provides a circuit board, set up the opening through the region that corresponds the anti-pad of second at second ground plane, can avoid forming parasitic capacitance between second ground plane and the via hole, can further improve the discontinuous problem of multilayer PCB via hole impedance, simultaneously, guarantee PCB intensity, reduce manufacturing cost to and do not occupy too much PCB overall arrangement space.

In one embodiment, the size of the second opening is the same as the size of the second anti-pad.

In one embodiment, the via has a stub.

The application also provides a circuit board via hole optimization method, which comprises the following steps: simulating a circuit board based on predetermined circuit board parameters, wherein a via hole is formed in the circuit board, a first anti-bonding pad is arranged at one end surrounding the via hole, the circuit board comprises a first grounding layer, and the first grounding layer covers the first anti-bonding pad and is arranged at an interval with the first anti-bonding pad; removing the area of the first ground layer corresponding to the first anti-pad to form a first opening, wherein the first opening and the via hole form a modified via hole structure; performing insertion loss and return loss simulation on the modified via structure and the via; comparing the simulation results of the modified via structure and the via; and determining whether the comparison result meets a preset condition.

In one embodiment, the method further comprises: determining a first parasitic type between the via and a first antipad; adjusting a size of the first anti-pad based on the first parasitic type.

In one embodiment, a second antipad is connected around the other end of the via, the circuit board further includes a second ground layer covering the second antipad and spaced apart from the second antipad, and the method further includes: removing the area of the second ground layer corresponding to the second anti-pad to form a second opening, the first opening, the via and the second opening forming the modified via structure.

In one embodiment, the method further comprises: determining a first parasitic type between the via and the first anti-pad and a second parasitic type between the via and the second anti-pad; adjusting a size of the first anti-pad based on the first parasitic type and adjusting a size of the second anti-pad based on the second parasitic type.

The application also provides an electronic device, which comprises a memory and a processor, wherein the memory is stored with computer readable instructions, and the computer readable instructions, when executed by the processor, cause the processor to execute the circuit board via hole optimization method.

The application also provides a nonvolatile readable storage medium storing computer readable instructions, and when the computer readable instructions are executed by a processor, the processor executes the circuit board via hole optimization method.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and that those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.

Fig. 1 is a schematic structural diagram of a circuit board according to an embodiment of the present application.

Fig. 2 is a flowchart of a circuit board via optimization method according to an embodiment of the present disclosure.

Fig. 3 is a block diagram of a circuit board via optimization apparatus according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Icon: a circuit board 10; a first wiring layer 111; a second wiring layer 112; a first dielectric layer 121; a via hole 13; a second dielectric layer 122; a first ground layer 141; a first anti-pad 1111; a first pad 1112; a first opening 1411; a third dielectric layer 123, a second ground layer 142; a second anti-pad 1121; a second opening 1421; a circuit board via optimization device 20; a simulation module 21; a removal module 22; a simulation module 23; a comparison module 24; a determination module 25.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Referring to fig. 1, an embodiment of the present application provides a circuit board 10. In this embodiment, the circuit board 10 includes a first circuit layer 111, a second circuit layer 112, a first dielectric layer 121, a via hole 13, a second dielectric layer 122 and a first ground layer 141.

The first circuit layer 111 and the second circuit layer 112 have signal lines, respectively. The first circuit layer 111 and the second circuit layer 112 may be formed by exposing, developing, etching, etc. conductive layers of copper, tungsten, etc.

The first dielectric layer 121 is disposed between the first circuit layer 111 and the second circuit layer 112. The first dielectric layer 121 may be made of a dielectric material such as epoxy resin or polyester. It should be noted that the number of the first dielectric layers may be multiple, and multiple first dielectric layers 121 are stacked. Of course, other circuit layers may be formed between the plurality of first dielectric layers 121.

The via 13 penetrates the first dielectric layer 121 and electrically connects the first circuit layer 111 and the second circuit layer 112. The via 13 may be formed by first forming a via hole in the first dielectric layer 121 and then filling (e.g., electroplating, electroless plating, etc.) the via hole with a conductive material. In this embodiment, the via hole 13 is a high-frequency signal via hole. In this embodiment, the via hole 13 has a stub.

A first anti-pad 1111 is disposed around one end of the via hole 13 near the first circuit layer 111. Specifically, one end of the via 13 near the first circuit layer 111 is provided with a first pad 1112. The first anti-pads 1111 are spaced around the first pads 1112. The first anti-pad 1111 and the first pad 1112 are electrically isolated from each other.

The second dielectric layer 122 is disposed on a side of the first circuit layer 111 away from the second circuit layer 112. The second dielectric layer 122 may be made of a dielectric material such as epoxy resin, polyester, etc. Note that the number of the second dielectric layers 122 is one.

The first ground layer 141 is disposed on a side of the second dielectric layer away from the first circuit layer 111. The first ground layer 141 has a first opening 1411 in an area corresponding to the first anti-pad 1111. The first ground layer 141 may be made of a conductive material such as copper or aluminum. In one embodiment, the size of the first opening 1411 is the same as the size of the first anti-pad 1111.

In this embodiment, a second anti-pad 1121 is disposed around one end of the via hole 13 close to the second circuit layer 112. Specifically, one end of the via 13 near the second line layer 112 is provided with a second pad 1122. The second anti-pads 1121 are spaced around the second pad 1122. The second anti-pad 1121 and the second pad 1122 are electrically isolated from each other.

The circuit board 10 further includes a third dielectric layer 123 and a second ground layer 142.

The third dielectric layer 123 is disposed on a side of the second circuit layer 112 away from the first circuit layer 111. The third dielectric layer 123 may be made of a dielectric material such as epoxy resin or polyester. Note that the number of the third dielectric layers 123 is one.

The second ground layer 142 is disposed on a side of the third dielectric layer 123 away from the second circuit layer 112. A second opening 1421 is formed in a region of the second ground layer 142 corresponding to the second anti-pad 1121. The second ground layer 142 may be made of a conductive material such as copper, aluminum, or the like. In one embodiment, the size of the second opening 1421 is the same as the size of the first anti-pad 1121.

According to the circuit board provided by the embodiment of the application, the opening is formed in the area, corresponding to the first anti-bonding pad, of the first grounding layer, so that parasitic capacitance formed between the first grounding layer and the via hole can be avoided, the problem of discontinuous impedance of the via holes of the multilayer PCB is improved to a certain extent, meanwhile, the strength of the PCB is ensured, the manufacturing cost is reduced, and excessive PCB layout space is not occupied; the opening is formed in the area, corresponding to the second anti-bonding pad, of the second grounding layer, parasitic capacitance formed between the second grounding layer and the via hole can be avoided, the problem of impedance discontinuity of the multi-layer PCB via hole 13 can be further improved, meanwhile, the strength of the PCB is guaranteed, the manufacturing cost is reduced, and excessive PCB layout space is not occupied.

Referring to fig. 2, based on the same inventive concept, an embodiment of the present application further provides a method for optimizing a via hole of a circuit board. The method may include the following steps.

Step S101, a circuit board is simulated based on predetermined circuit board parameters, a via hole is formed in the circuit board, a first anti-bonding pad is connected to one end of the circuit board surrounding the via hole, the circuit board comprises a first grounding layer, and the first grounding layer covers the first anti-bonding pad and is arranged at an interval with the first anti-bonding pad.

Step S102, removing the area of the first ground layer corresponding to the first anti-pad to form a first opening, and forming a modified via structure by the first opening and the via. It will be appreciated that the removal operation may be accomplished by adjusting circuit board parameters.

And step S103, performing insertion loss and return loss simulation on the modified via hole structure and the via hole. It is understood that insertion and return loss simulations are well known in the art and will not be described herein.

And step S104, comparing the modified via hole structure with the simulation result of the via hole.

And step S105, determining whether the comparison result meets a preset condition. Specifically, step S104 may include determining whether S11 has reached below a preset value (e.g., -20 dB). It should be noted that S11 is a quantity of the S parameter (i.e., scattering parameter) and is an input reflection coefficient, i.e., an input return loss.

It is understood that the method further comprises: determining a first parasitic type between the via and the first anti-pad; the size of the first anti-pad is adjusted based on the first parasitic type. In an embodiment, the first parasitic type between the via hole and the first anti-pad can be determined by performing TDR simulation on the whole trace containing the via hole of the circuit board. The first parasitic type may be capacitive parasitic and inductive parasitic. Increasing the size of the first anti-pad when the first parasitic type is determined to be capacitive parasitic; when the first parasitic type is determined to be inductive parasitic, the size of the first anti-pad is reduced. Alternatively, determining the first parasitic type and adjusting the size of the first anti-pad based on the first parasitic type may be performed before step S102.

It is understood that the TDR simulation is well known in the art and will not be described herein.

In one embodiment, a second anti-pad is connected around the other end of the via hole, the circuit board further includes a second ground layer covering the second anti-pad and spaced apart from the second anti-pad, and the method may further include: and removing the area of the second ground layer corresponding to the second anti-bonding pad to form a second opening, wherein the first opening, the via hole and the second opening form a modified via hole structure.

In one embodiment, the method further comprises: determining a first parasitic type between the via hole and the first anti-bonding pad and a second parasitic type between the via hole and the second anti-bonding pad; the size of the first anti-pad is adjusted based on the first parasitic type, and the size of the second anti-pad is adjusted based on the second parasitic type. In an embodiment, the second parasitic type between the via hole and the second anti-pad may be determined by performing TDR simulation on the entire trace of the circuit board including the via hole. The second parasitic type may be capacitive parasitic and inductive parasitic. Increasing the size of the second anti-pad when the second parasitic type is determined to be capacitive parasitic; when the second parasitic type is determined to be inductive parasitic, the size of the second anti-pad is reduced. It is understood that the TDR simulation is well known in the art and will not be described herein.

Referring to fig. 3, based on the same inventive concept, an embodiment of the present application further provides a circuit board via optimization apparatus 20, which includes a simulation module 21, a removal module 22, a simulation module 23, a comparison module 24, and a determination module 25.

The simulation module 21 is configured to simulate a circuit board based on predetermined circuit board parameters, the circuit board is provided with a via hole, one end of the via hole is connected to a first anti-pad, the circuit board includes a first ground plane, and the first ground plane covers the first anti-pad and is spaced from the first anti-pad.

And a removing module 22 for removing the area of the first ground layer corresponding to the first anti-pad to form a first opening, wherein the first opening and the via hole form a modified via hole structure.

And the simulation module 23 is used for performing insertion loss and return loss simulation on the modified via structure and the via.

A comparison module 24 for comparing the modified via structure and the simulation result of the via.

And the determining module 25 is used for determining whether the comparison result meets a preset condition.

In one embodiment, the determining module 25 is further configured to determine a first parasitic type between the via and the first anti-pad; the size of the first anti-pad is adjusted based on the first parasitic type.

In one embodiment, a second anti-pad is formed around the other end of the via. The circuit board further includes a second ground plane. The second grounding layer covers the second anti-bonding pad and is arranged at a distance from the second anti-bonding pad. The removing module 22 is further configured to remove an area of the second ground plane corresponding to the second anti-pad to form a second opening, and the first opening, the via hole and the second opening form a modified via structure.

In an embodiment, the determining module 25 is further configured to determine a first parasitic type between the via and the first anti-pad and a second parasitic type between the via and the second anti-pad; the size of the first anti-pad is adjusted based on the first parasitic type, and the size of the second anti-pad is adjusted based on the second parasitic type.

It can be understood that the circuit board via hole optimizing apparatus 20 provided in the present application corresponds to the circuit board via hole optimizing method provided in the present application, and for brevity of the description, the same or similar parts may refer to the contents of the circuit board via hole optimizing method part, and are not described herein again.

The various modules in the circuit board via optimization device described above may be implemented in whole or in part by software, hardware, and combinations thereof. The modules can be embedded in a hardware form or independent of a processor in the server, and can also be stored in a memory in the server in a software form, so that the processor can call and execute operations corresponding to the modules. The processor can be a Central Processing Unit (CPU), a microprocessor, a singlechip and the like.

The circuit board via optimization method and/or the circuit board via optimization device may be implemented in the form of computer readable instructions, which may be executed on the electronic device shown in fig. 4.

The embodiment of the present application further provides an electronic device, which includes a memory, a processor, and computer readable instructions stored in the memory and executable on the processor, and when the processor executes the program, the method for optimizing the via hole of the circuit board is implemented.

Fig. 4 is a schematic diagram of an internal structure of an electronic device according to an embodiment of the present application, where the electronic device may be a server. Referring to fig. 4, the electronic device includes a processor, a nonvolatile storage medium, an internal memory, an input device, a display screen, and a network interface, which are connected by a system bus. The nonvolatile storage medium of the electronic device may store an operating system and computer readable instructions, and when the computer readable instructions are executed, the processor may execute a circuit board via optimization method according to embodiments of the present application, and a specific implementation process of the method may refer to specific contents of fig. 2, which is not described herein again. The processor of the electronic device is used for providing calculation and control capability and supporting the operation of the whole electronic device. The internal memory may have stored therein computer readable instructions that, when executed by the processor, cause the processor to perform a method of circuit board via optimization. The input device of the electronic equipment is used for inputting various parameters, the display screen of the electronic equipment is used for displaying, and the network interface of the electronic equipment is used for network communication. Those skilled in the art will appreciate that the configuration shown in fig. 4 is a block diagram of only a portion of the configuration associated with the present application, and does not constitute a limitation on the electronic device to which the present application is applied, and a particular electronic device may include more or less components than those shown in the drawings, or combine certain components, or have a different arrangement of components.

Based on the same inventive concept, embodiments of the present application provide a computer-readable storage medium, on which computer-readable instructions are stored, and when the program is executed by a processor, the steps in the circuit board via optimization method described above are implemented.

Any reference to memory, storage, database, or other medium as used herein may include non-volatile. Suitable non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.

In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (5)

1. A circuit board, comprising:

a first circuit layer and a second circuit layer;

a first dielectric layer disposed between the first circuit layer and the second circuit layer;

a via hole penetrating through the first dielectric layer and electrically connecting the first circuit layer and the second circuit layer, wherein a first anti-pad is arranged around one end of the via hole close to the first circuit layer;

the second dielectric layer is arranged on one side, far away from the second circuit layer, of the first circuit layer;

the first grounding layer is arranged on one side of the second dielectric layer far away from the first circuit layer, and a first opening is formed in the area, corresponding to the first anti-bonding pad, of the first grounding layer.

2. The circuit board of claim 1, wherein the first opening has a size that is the same as a size of the first anti-pad.

3. The circuit board of claim 1 or 2, further comprising a third dielectric layer disposed on a side of the second wiring layer remote from the first wiring layer; the second grounding layer is arranged on one side of the third dielectric layer far away from the second circuit layer; and a second anti-bonding pad is arranged at one end, close to the second circuit layer, of the via hole, and a second opening is formed in the area, corresponding to the second anti-bonding pad, of the second ground layer.

4. The circuit board of claim 3, wherein the second opening has a size that is the same as a size of the second anti-pad.

5. The circuit board of claim 1, wherein the via has a stub.

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