CN112786618A

CN112786618A - Semiconductor device with a plurality of semiconductor chips

Info

Publication number: CN112786618A
Application number: CN202010817820.5A
Authority: CN
Inventors: 戴名柔; 蔡嘉豪
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2019-11-06
Filing date: 2020-08-14
Publication date: 2021-05-11
Anticipated expiration: 2040-08-14
Also published as: CN112786618B

Abstract

An embodiment of the present disclosure provides a semiconductor device including a substrate, a polysilicon semiconductor layer, and a conductive line. The polycrystalline silicon semiconductor layer is arranged on the substrate. The conducting wire is arranged on the substrate. The conductive line contacts the polycrystalline silicon semiconductor layer through the contact portion. The contact parts of the polycrystalline silicon semiconductor layer and the conducting wire are respectively provided with mutually aligned side edges. The semiconductor device of the present disclosure has good electrical connection, improved contact problems, improved reliability, reduced resistivity, increased drive capability, or improved display quality.

Description

Semiconductor device with a plurality of semiconductor chips

Technical Field

Embodiments of the present disclosure relate to an electronic device, and more particularly, to an electronic device including a semiconductor device providing good electrical connection.

Background

Flat display panels have been widely used in electronic devices such as mobile phones, televisions, monitors, tablet computers, car monitors, wearable devices, and desktop computers. With the rapid development of electronic products, the requirements for display quality on the electronic products are higher and higher, so that the electronic devices for displaying are continuously moving towards the improvement of larger and higher resolution display effects.

Disclosure of Invention

The present disclosure provides a semiconductor device having good electrical connection, improved contact problems, improved reliability, reduced resistivity, increased driving capability, or improved display quality.

According to an embodiment of the present disclosure, a semiconductor device includes a substrate, a polysilicon semiconductor layer, and a conductive line. The polycrystalline silicon semiconductor layer is arranged on the substrate. The conducting wire is arranged on the substrate. The conductive line contacts the polycrystalline silicon semiconductor layer through the contact portion. The contact parts of the polycrystalline silicon semiconductor layer and the conducting wire are respectively provided with mutually aligned side edges.

In summary, in the semiconductor device according to the embodiment of the disclosure, the side of the contact portion of the conductive line is aligned with the side of the polysilicon semiconductor layer in the first opening, so that the contact portion and the polysilicon semiconductor layer have good electrical connection. The semiconductor device has excellent technical effects of improving contact problems, increasing reliability, or improving display quality. In addition, the semiconductor device can reduce the load of the wiring, increase the driving capability, or improve the display quality.

Drawings

The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic top view of a semiconductor device according to an embodiment of the disclosure;

FIG. 2 is a cross-sectional view of the semiconductor device of FIG. 1 along line A-A';

FIG. 3 is an enlarged, fragmentary, top view of region R1 of FIG. 1;

FIG. 4 is a cross-sectional view of section line M-M' of FIG. 3;

fig. 5 is a schematic top view of a semiconductor device in a non-display area according to an embodiment of the disclosure;

FIG. 6 is an enlarged, fragmentary, top view of the region R2 of FIG. 5;

FIG. 7 is a cross-sectional view of the semiconductor device of FIG. 6 along line B-B';

FIG. 8 is a schematic top view of a semiconductor device according to another embodiment of the present disclosure;

fig. 9 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present disclosure.

Detailed Description

The present disclosure may be understood by reference to the following detailed description taken in conjunction with the accompanying drawings, in which it is noted that, for the sake of clarity and brevity of the drawings, the various drawings in the present disclosure depict only some of the electronic devices and are not necessarily drawn to scale. In addition, the number and size of the elements in the figures are merely illustrative and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the following description and appended claims to refer to particular elements. Those skilled in the art will appreciate that electronic device manufacturers may refer to the same components by different names. This document does not intend to distinguish between components that differ in function but not name. In the following description and claims, the terms "comprising," including, "" having, "and the like are open-ended terms and thus should be interpreted to mean" including, but not limited to, …. Thus, when the terms "comprises," "comprising," and/or "having" are used in the description of the present disclosure, they specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional phrases used herein include, for example: "upper", "lower", "front", "rear", "left", "right", etc., refer only to the orientation of the figures. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. In the drawings, which illustrate general features of methods, structures, and/or materials used in certain embodiments. These drawings, however, should not be construed as defining or limiting the scope or nature encompassed by these embodiments. For example, the relative sizes, thicknesses, and locations of various film layers, regions, and/or structures may be reduced or exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "connected to" another element or layer, it can be directly connected to the other element or layer or intervening elements or layers may be present. When an element is referred to as being "directly connected to" another element or layer, there are no intervening elements or layers present between the two. In addition, when an element is referred to as being "coupled" to another element (or a variant thereof), it can be directly connected to the other element or be indirectly connected (e.g., electrically connected) to the other element through one or more elements.

In the present disclosure, the length and the width can be measured by an optical microscope, and the thickness can be measured by a cross-sectional image in an electron microscope, but not limited thereto. In addition, there may be some error in any two values or directions for comparison.

The terms "about," "equal to," or "the same," "substantially," or "approximately" are generally construed as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

The structure (or layer, component, substrate) located on another structure (or layer, component, substrate) described in the present disclosure may refer to two structures adjacent to each other and directly connected, or may refer to two structures adjacent to each other and not directly connected, where the indirect connection refers to two structures having at least one secondary structure (or secondary layer, secondary component, secondary substrate, secondary space) between them, the lower surface of one structure is adjacent to or directly connected to the upper surface of the secondary structure, the upper surface of the other structure is adjacent to or directly connected to the lower surface of the secondary structure, and the secondary structure may be a single-layer or multi-layer solid structure or a non-solid structure, without limitation. In the present disclosure, when a structure is disposed "on" another structure, it may be directly on the other structure or indirectly on the other structure, that is, at least one structure is sandwiched between the other structure and the certain structure.

The terms "first," "second," etc. may be used herein to describe various elements, components, regions, layers and/or sections, but these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, the discussion of a "first element," "component," "region," "layer," or "portion" below is intended to be inclusive in a manner separate from a "second element," "component," "region," "layer," or "portion," and not intended to limit the order or particular elements, components, regions, layers, and/or portions.

The electronic device can achieve a display effect through the semiconductor device according to the embodiment of the disclosure, wherein the electronic device may include a display device, an antenna device, a sensing device, a splicing device, or a transparent display device, but is not limited thereto. The electronic device may be a rollable, stretchable, bendable or flexible electronic device. The electronic device may include, for example, a liquid crystal (liquid crystal), a Light Emitting Diode (LED), a Quantum Dot (QD), a fluorescent (fluorescent), a phosphorescent (phosphor) or other suitable material, and the materials may be combined in any arrangement or other suitable display medium, or a combination of the foregoing; the light emitting diode may include, for example, an Organic Light Emitting Diode (OLED), a millimeter/sub-millimeter light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (QD, which may be, for example, a QLED or a QDLED), but is not limited thereto. The antenna device may be, for example, a liquid crystal antenna, but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device can be any permutation and combination of the foregoing, but not limited thereto. In addition, the exterior of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, a shelf system …, etc. to support the display device, the antenna device, or the tile device. The present disclosure will be described in terms of a semiconductor device, but the present disclosure is not limited thereto.

In the present disclosure, various embodiments described below may be mixed and matched without departing from the spirit and scope of the present disclosure, for example, some features of one embodiment may be combined with some features of another embodiment to form a further embodiment.

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Fig. 1 is a top view of a semiconductor device according to an embodiment of the disclosure. Several elements are omitted from fig. 1 for clarity and ease of illustration. Fig. 2 is a cross-sectional view of the semiconductor device of fig. 1 along a sectional line a-a'. Fig. 3 is a partially enlarged top view of the region R1 in fig. 1. Referring to fig. 1 and fig. 2, the semiconductor device 10 of the present embodiment is, for example, a display device suitable for displaying images, but the disclosure is not limited thereto. The semiconductor device 10 includes a substrate 100, a polysilicon semiconductor layer 130, and a conductive line 150. The polysilicon semiconductor layer 130 is disposed on the substrate 100. The conductive line 150 is disposed on the substrate 100. The conductive line 150 has a contact portion 152, and the conductive line 150 contacts the polysilicon semiconductor layer 130 through the contact portion 152 at the first opening H1. In the top view of the present embodiment, since the side 131 of the polysilicon semiconductor layer 130 and the side 154 of the contact portion 152 of the conductive line 150 can be aligned (align), the conductive line 150 and the polysilicon semiconductor layer 130 can have good electrical connection. In addition, the semiconductor device 10 of the present embodiment has the excellent technical effects of improving the contact problem, increasing the reliability, decreasing the resistivity, increasing the driving capability, or improving the display quality.

In detail, as shown in fig. 1 and 2, the semiconductor device 10 includes a substrate 100. The substrate 100 includes a rigid substrate, a flexible substrate, or a combination thereof. For example, the material of the substrate 100 may include glass, quartz, sapphire (sapphire), ceramic, Polycarbonate (PC), Polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination thereof, but is not limited thereto.

The light-shielding layer 110 is disposed on the substrate 100. The plurality of light-shielding layers 110 may be arranged in a row along the first direction X, and the plurality of light-shielding layers 110 may be arranged in a row along the second direction Y, when viewed in a normal direction (e.g., a top view direction, which may also be referred to as a third direction Z) of the substrate 100. In the present embodiment, the first direction X, the second direction Y, and the third direction Z are different directions, for example, the first direction X is, for example, an extending direction of the scan line SL (for example, from left to right in fig. 1), the second direction Y is, for example, an extending direction of the conductive line 150, the third direction Z is, for example, a normal direction of the substrate, and the third direction Z is perpendicular to the first direction X and the second direction Y, respectively, but the present embodiment is not limited thereto. The material of the light-shielding layer 110 may include molybdenum or other suitable light-shielding materials, which is not limited in this embodiment.

In the present embodiment, the light-shielding layer 110 is disposed corresponding to an active device (active device) of a Thin Film Transistor (TFT), for example, to reduce light leakage current or improve flicker. The configuration of the thin film transistor TFT will be briefly described below.

As shown in fig. 1 and 2, the semiconductor device 10 further includes a buffer layer 120, a gate insulating layer 140, an interlayer dielectric layer 160, a first insulating layer 180, a second insulating layer 190, a plurality of TFTs, and a plurality of wires 150 disposed on the substrate 100. Specifically, the buffer layer 120 is disposed on the substrate 100 and covers the plurality of light-shielding layers 110. The gate insulating layer 140 is disposed on the buffer layer 120. The interlayer dielectric layer 160 is disposed on the gate insulating layer 140. The first insulating layer 180 is disposed on the interlayer dielectric layer 160. The second insulating layer 190 is disposed on the first insulating layer 180. In the present embodiment, the buffer layer 120, the gate insulating layer 140, the interlayer dielectric layer 160, the first insulating layer 180, and the second insulating layer 190 may be a single layer or a multi-layer structure, and may include, for example, an organic material, an inorganic material, or a combination thereof, where the organic material may include polyethylene terephthalate (PET), polyethylene, PE, Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), Polyimide (PI), photosensitive polyimide (PSPI), or a combination thereof, and the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, but not limited thereto.

In the present embodiment, the thin film transistor is disposed on the substrate, and the thin film transistor may be composed of the polycrystalline silicon semiconductor layer 130, the gate electrode GE, the source pattern and the drain pattern 151. The polysilicon semiconductor layer 130 is disposed on the buffer layer 120. Under the above configuration, the polysilicon semiconductor layer 130 may have a U-shape, but not limited thereto. In this embodiment, the material of the polysilicon semiconductor layer 130 is, for example, Low Temperature Polysilicon (LTPS).

Referring to the cross-sectional view of fig. 2, the gate insulating layer 140 is disposed on the polysilicon semiconductor layer 130. The scan line SL is disposed on the gate insulating layer 140. In the present embodiment, the scan line SL may extend along the first direction X and overlap the polycrystalline silicon semiconductor layer 130 in the third direction Z. A portion of the scan line SL overlapping the polycrystalline silicon semiconductor layer 130 may be defined as a gate electrode GE.

In the present embodiment, the thin film transistor further includes a dielectric layer IL disposed between the gate GE and the gate insulating layer 140, but the present embodiment is not limited thereto. The dielectric layer IL may be a single layer or a multi-layer structure, and may include, for example, an organic material, an inorganic material (e.g., silicon nitride, etc.), or a combination thereof, but is not limited thereto. The organic material may include polyethylene terephthalate (PET), Polyethylene (PE), Polyethersulfone (PEs), Polycarbonate (PC), polymethyl methacrylate (PMMA), Polyimide (PI), photosensitive polyimide (PSPI), or a combination thereof, and the inorganic material may include silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof, but is not limited thereto.

The interlayer dielectric layer 160 is disposed on the scan line SL. The conductive line 150 is disposed on the interlayer dielectric layer 160. As shown in the top view of fig. 1, the conductive line 150 extends substantially along the second direction Y, and as shown in the cross-sectional view of fig. 2, the conductive line 150 partially overlaps the polysilicon semiconductor layer 130 in the third direction Z. The polysilicon semiconductor layer 130 includes, for example, a first segment 130A, a second segment 130B, and a third segment 130C. The second segment 130B is connected to the first segment 130A and the third segment 130C. In the cross-sectional view of the present embodiment, the conductive line 150 partially overlaps the first segment 130A of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100. Referring to the cross-sectional view of fig. 2, the drain pattern 151 is disposed on the interlayer dielectric layer 160, and the drain pattern 151 partially overlaps the third segment 130C of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100. In other words, the conductive line 150 and the drain pattern 151 do not overlap the second segment 130B of the polysilicon semiconductor layer 130 in the third direction Z perpendicular to the substrate 100, but the disclosure is not limited thereto.

The conductive line 150 is, for example, a data line, but not limited thereto. In the present embodiment, the interlayer dielectric layer 160 has a first opening H1, and the first opening H1 penetrates the gate insulating layer 140 and is located on the first segment 130A of the conductive line 150 overlapping the polysilicon semiconductor layer 130. In detail, in the third direction Z, the first opening H1 overlaps a portion of the first segment 130A of the polysilicon semiconductor layer 130. The contact portion 152 of the conductive line 150 passes through the first opening H1 to contact the polycrystalline silicon semiconductor layer 130. Thereby, the contact portion 152 may be applied as a source pattern of the thin film transistor TFT. The interlayer dielectric layer 160 further has a second opening H2 on the drain pattern 151 overlapping the third segment 130C, and in detail, in the third direction Z, the second opening H2 overlaps a portion of the third segment 130C of the polysilicon semiconductor layer 130.

Referring to the top view of fig. 3, fig. 3 is a partially enlarged view of the region R1 in fig. 1. In the partially enlarged view of fig. 3, the drain pattern 151 may pass through the second opening H2 to contact the polycrystalline silicon semiconductor layer 130. In the top view of the present embodiment, the drain pattern 151 has a side 153, the side 153 is parallel to the first direction X, the polysilicon semiconductor layer 130 has a side 131 ', the side 131 ' is also parallel to the first direction X, and the side 153 of the drain pattern 151 and the side 131 ' of the polysilicon semiconductor layer 130 are aligned (align). In the present embodiment, the alignment of the side 153 and the side 131' can be defined as: in the top view of the present embodiment, as shown in fig. 3, the distance D between the side 153 and the side 131 'in the second direction Y is less than or equal to 1 micrometer, or, as shown in fig. 4, fig. 4 is a cross-sectional view of a section line M-M' of fig. 3, and the distance D between the side 153 and the side 131 in the second direction Y is less than or equal to 1 micrometer.

In the present embodiment, the conductive line 150, the contact portion 152 and the drain pattern 151 are made of molybdenum (Mo), titanium (Ti) or a combination thereof, but not limited thereto. In some embodiments, the material of the conductive line 150, the contact 152 and the drain pattern 151 may further include tantalum (Ta), niobium (Nb), hafnium (Hf), nickel (Ni), chromium (Cr), cobalt (Co), zirconium (Zr), tungsten (W), other suitable metals, or alloys or combinations thereof, but is not limited thereto.

In some embodiments, referring to the schematic cross-sectional view of fig. 4, the drain pattern 151 is exemplified by the drain pattern 151, and the drain pattern 151 may be a stacked structure formed by stacking a plurality of metal layers in the third direction Z. In detail, the drain pattern 151 may include a metal layer 1511, a metal layer 1512, and a metal layer 1513. The metal layer 1512 is disposed between the

metal layers

1511 and 1513. The metal layer 1511 contacts the polysilicon semiconductor layer 130 in the second opening H2. The material of the

metal layers

1511 and 1513 is, for example, titanium. The metal layer 1512 is made of molybdenum, for example, but the embodiments of the disclosure are not limited thereto.

With reference to fig. 1, in order to further reduce the resistivity (resistivity) of the conductive line 150, the semiconductor device 10 further includes an auxiliary conductive line 170, and the auxiliary conductive line 170 substantially extends along the second direction Y corresponding to the conductive line 150. As shown in the cross-sectional view of fig. 2, the auxiliary conductive line 170 is disposed on the first insulating layer 180 and overlaps the conductive line 150 in the third direction Z, wherein the auxiliary conductive line 170 may be, for example, a data line.

In the present embodiment, as shown in the cross-sectional view of fig. 2, the first insulating layer 180 is disposed between the conductive line 150 and the auxiliary conductive line 170, and the first insulating layer 180 has a first opening O1. The auxiliary conductive line 170 is electrically connected to the conductive line 150 through the first opening O1. Thus, the auxiliary conductive line 170 can be electrically connected to the conductive line 150. In the present embodiment, the first opening O1 has a first minimum width W1 in the second direction Y. The first minimum width W1 can be defined as the width of the first opening O1 closest to the conductive line 150 in the second direction Y, and more specifically, the minimum width of the opening or hole referred to in the present disclosure is measured by: the minimum distance between the two sides of the opening or aperture in the second direction Y. Under the above configuration, the semiconductor device 10 of the present disclosure can be electrically connected to the auxiliary wires 170 through the wires 150 to achieve the structure of the dual data lines, thereby reducing the resistivity of the lines.

In some embodiments, in the third direction Z (i.e. the normal direction) perpendicular to the substrate 100, the width W6 of the auxiliary wire 170 along the first direction X and the width W5 of the wire 150 along the first direction X are measured as follows: the minimum distance of the two sides of the wire or the auxiliary wire in the first direction X. In the embodiment of the present disclosure, the width W6 is greater than or equal to 0.5 times W5 and less than or equal to 1.5 times W5. When the width W6 is less than 0.5 times the width W5, the effect of reducing the resistivity of the wire 150 is not effectively provided. When the width W6 is greater than 1.5 times the width W5, the aperture ratio of the pixel is affected. Under the above arrangement, in the third direction Z, the contour of the conductive wire 150 may be located within the contour of the auxiliary conductive wire 170, or the contour of the auxiliary conductive wire 170 may be located within the contour of the conductive wire 150, depending on the user's requirement.

It is noted that the auxiliary wire 170 has good resistivity because the auxiliary wire 170 is made of gold (Au), silver (Ag), copper (Cu), aluminum (Al), or other suitable metal, or an alloy or combination thereof. Compared to the conductive line 150, the resistivity of the auxiliary conductive line 170 of the present embodiment is smaller than the resistivity of the conductive line 150, and in detail, at a temperature of 20 ℃, the resistivity of the auxiliary conductive line 170 is 53.4n Ω · m, and the resistivity of the conductive line 150 is 28.2n Ω · m, but not limited thereto. In addition, the semiconductor device 10 can be electrically connected to the auxiliary conductive line 170 through the conductive line 150 to achieve the dual data line structure, so that the resistivity of the circuit of the semiconductor device 10 can be further reduced. Specifically, when the display panel with a small pixel size still has a high resolution, the load (Loading) of the data lines is significantly higher than that of the display panel with a large pixel size, and thus, abnormal image display may be caused due to the excessive load of the data lines. Therefore, according to the teachings of the present embodiment, the dual-layer data lines are disposed in the display panel with a small pixel size, and the electrical connection design of the dual-layer data lines can reduce the impedance or increase the driving capability of the panel, so as to satisfy the display requirements with a small pixel size or high resolution. As a result, the structure of the double-layer data line of the semiconductor device 10 can reduce the resistivity of the line, so that the load can be reduced, thereby increasing the driving capability of the semiconductor device 10 or improving the display quality.

Referring to the cross-sectional view of fig. 2, the second insulating layer 190 is disposed on the auxiliary conductive line 170. The second insulating layer 190 has a second opening O2. In addition, the semiconductor device 10 further includes a pixel electrode PE disposed on the insulating layer 190, a protective layer 192 disposed on the pixel electrode PE, and a common electrode CE disposed on the protective layer 192. The pixel electrode PE is electrically connected to the drain pattern 151 through the second opening O2. In addition, the protective layer 192 and the common electrode CE may also be partially disposed in the second opening O2. The material of the pixel electrode PE and the common electrode CE includes a transparent conductive material, such as Indium Tin Oxide (ITO), but not limited thereto.

In the present embodiment, the second opening O2 has a second minimum width W2 in the second direction Y. The second minimum width W2 may be defined as a width of the second opening O2 closest to the drain pattern 151 in the second direction Y. In the present embodiment, the first minimum width W1 is less than the second minimum width W2. Under the above arrangement, the second opening O2 may provide enough space for the pixel electrode PE to be electrically connected to the drain pattern 151, so as to ensure good electrical connection. As such, the semiconductor device 10 has the excellent technical effects of good electrical connection, improving contact problems, increasing reliability, or improving display quality, but the disclosure is not limited thereto.

In some embodiments, the first apertures H1 have a third minimum width W3 along the second direction Y. The third minimum width W3 may be defined as the width of the first opening H1 closest to the polysilicon semiconductor layer 130 in the second direction Y. In the present embodiment, the second minimum width W2 is greater than the third minimum width W3. As such, the contact portion 152 can be electrically connected to the polysilicon semiconductor layer 130 through the first opening H1, or the aperture ratio of the pixel is not affected, but the disclosure is not limited thereto.

In some embodiments, in a normal direction of the substrate 100 (e.g., the third direction Z), the minimum width W4 of the light shielding layer 110 along the second direction Y is greater than the second minimum width W2. In detail, in the cross-sectional view of the embodiment, the minimum width W4 of the two side edges of the light-shielding layer 110 along the second direction Y is greater than the second minimum width W2. Accordingly, the light-shielding layer 110 may prevent light from directly irradiating the channel CH2 from below the substrate 100 to generate a light leakage current, or prevent the light from affecting the drain pattern 151, the pixel electrode PE, or the common electrode CE, but the disclosure is not limited thereto.

Fig. 5 is a schematic top view of a semiconductor device in a non-display area according to an embodiment of the disclosure. Several elements are omitted from fig. 5 for clarity of the drawing and ease of illustration. Fig. 6 is a partially enlarged top view schematically illustrating the region R2 of fig. 5. Fig. 7 is a cross-sectional view of the semiconductor device of fig. 6 along a sectional line B-B'. Referring to fig. 5, the semiconductor device 10 of the present embodiment includes a display region 11 and a non-display region 13 defined on a substrate 100 and surrounding the display region 11. The display region 11 is provided with the above-described thin film transistor TFT, a conductive line 150, and an auxiliary conductive line 170. The conductive lines 150 and the auxiliary conductive lines 170 may extend from the display region 11 to the non-display region 13 to electrically connect with the electronic devices 300 in the non-display region 13. The electronic device 300 is exemplified by an Integrated Circuit (IC) providing a driving signal, an integrated driving and touch IC (tddi), a chip, a Flexible Printed Circuit (FPC) or a Chip On Film (COF), but not limited thereto.

It is noted that the semiconductor device 10 of the present embodiment further includes a conductive line 250 and an auxiliary conductive line 270 disposed in the non-display region 13. As shown in fig. 7, the

conductive lines

150 and 250 are disposed on the interlayer dielectric layer 160. The

auxiliary wires

170 and 270 are disposed on the first insulating layer 180, and the first insulating layer 180 is located between the wires 150 (or the wires 250) and the auxiliary wires 170 (or the auxiliary wires 270). The first insulating layer 180 further includes a plurality of third openings V, and the auxiliary conductive line 170 is electrically connected to the conductive line 250 through one of the third openings V, or the conductive line 150 is electrically connected to the auxiliary conductive line 270 through one of the third openings V. Thus, the wires 150 and the auxiliary wires 170 extending from the display area 11 may be connected to the electronic element 300 through the wires 250 and the auxiliary wires 270, so as to increase the circuit layout margin of the semiconductor device 10, or the semiconductor device may achieve the requirement of narrow frame or frameless, but the disclosure is not limited thereto. In addition, the structure of the auxiliary conductive line 170 (or the auxiliary conductive line 270) and the conductive line 150 (or the conductive line 250) as a dual-layer data line can reduce the resistivity of the lines. The semiconductor device 10 has an excellent technical effect of increasing driving capability or improving display quality.

As shown in the region R2 of fig. 5 and 6, the plurality of third openings V are staggered along the first direction X in the normal direction of the substrate 100. For example, the plurality of third openings V includes a plurality of third openings V1 aligned in a line along the first direction X, and a plurality of third openings V2 aligned in another line along the first direction X. In the second direction Y, one row of the plurality of third apertures V1 is adjacent to the electronic element 300, and another row of the plurality of third apertures V2 is adjacent to the display area 11. That is, the third openings V1 and the third openings V are staggered in the second direction Y and are arranged along the second direction. It should be noted that fig. 5 and 6 illustrate two rows of the third openings V, but the disclosure is not limited thereto. In other embodiments, the number of rows of the third openings V may not be limited thereto, but may be arranged in three, four or more rows, depending on the needs of the user.

Under the above arrangement, when applied to a small-sized high-resolution display device, the semiconductor device 10 can avoid short circuit caused by contact of the third openings arranged with high line precision by the staggered arrangement of the third openings V, and thus the reliability of the semiconductor device 10 can be improved.

In short, in the top view of the present embodiment, in the semiconductor device 10, the side 154 of the contact portion 152 is aligned with the side 131 of the polysilicon semiconductor layer 130 in the first opening H1, so that the contact portion 152 and the polysilicon semiconductor layer 130 have good electrical connection, and the contact problem of the semiconductor device 10 can be improved, thereby improving the reliability or improving the excellent technical effect of the display quality. In addition, the semiconductor device 10 can be electrically connected to the auxiliary wires 170 through the wires 150 to achieve a double-layer data line structure, thereby reducing the resistivity of the line. Since the auxiliary wire 170 has a resistivity smaller than that of the wire 150, the resistivity of the dual-layer data line of the semiconductor device 10 can be further reduced. Thus, the semiconductor device 10 can reduce the load of the dual-layer data line, increase the driving capability, or improve the display quality. In addition, since the first minimum width W1 of the first opening is smaller than the second minimum width W2 of the second opening O2, and the second minimum width W2 is greater than the third minimum width W3 of the connection portion 152. Therefore, the semiconductor device 10 can ensure good electrical connection or does not affect the aperture ratio of the pixel. In addition, the width W4 of the light shielding layer 110 is greater than the second minimum width W2. Therefore, the light-shielding layer 110 can prevent the generation of light leakage current or influence on the display effect. The semiconductor device 100 further includes a conductive line 250 and an auxiliary conductive line 270 layered in the non-display region 13, and a plurality of third openings V arranged in a staggered manner. Thus, the wires 250 and the auxiliary wires 270 arranged in layers can increase the wiring margin in the non-display region 13. The staggered third openings V can avoid short circuit or improve reliability. The measured widths are all widths in the second direction Y.

Other examples will be listed below for illustration. It should be noted that the following embodiments follow the reference numerals and parts of the contents of the foregoing embodiments, wherein the same reference numerals are used to indicate the same or similar elements, and the description of the same technical contents is omitted. For the description of the omitted parts, reference may be made to the foregoing embodiments, and the following embodiments will not be repeated.

Fig. 8 is a top view of a semiconductor device according to another embodiment of the present disclosure. Several elements are omitted from fig. 8 for clarity and ease of illustration. The semiconductor device 10A of the present embodiment is substantially similar to the semiconductor device 10 of fig. 1, and therefore the same and similar components in the two embodiments are not repeated herein. The present embodiment is different from the semiconductor device 10 mainly in that, in the normal direction of the substrate 100, the width of the auxiliary conductive line 170A in the first direction X is greater than or equal to 0.5 times the width of the conductive line 150 in the first direction X, and is smaller than the width of the conductive line 150 in the first direction X. Thus, the semiconductor device 10A has an effect of reducing the resistivity of the conductive line 150 or does not affect the aperture ratio of the pixel. In addition, the semiconductor device 10A can also achieve excellent technical effects similar to those of the above-described embodiments.

Fig. 9 is a schematic cross-sectional view of a semiconductor device according to still another embodiment of the present disclosure. The semiconductor device 10B of the present embodiment is substantially similar to the semiconductor device 10 of fig. 2, and therefore the same and similar components in the two embodiments are not repeated herein. The present embodiment is different from the semiconductor device 10 mainly in that the thickness T2 of the auxiliary wire 170B in the third direction Z is different from the thickness T1 of the wire 150. For example, the thickness T2 may be greater than the thickness T1 and equal to or less than 3 times the thickness T1, but is not limited thereto. Since the resistivity of the auxiliary conductive line 170B is greater than the resistivity of the conductive line 150, in some embodiments, when the thickness T2 of the auxiliary conductive line 170B in the third direction Z is greater than the thickness T1 of the conductive line 150, the resistivity of the dual-layer data line can be further reduced. When the thickness T2 of the auxiliary conductive line 170B in the third direction Z is greater than 3 times the thickness T1, cracks or discontinuities of the subsequent layer, such as cracks or discontinuities of the second insulating layer 190, may be caused, which may affect the stability of the electrical connection. With the above arrangement, the auxiliary conductive line 170B can further reduce the resistivity and the load of the dual-layer data line, so that the semiconductor device 10B can increase the driving capability or improve the display quality. The thickness referred to in this disclosure is the minimum distance between the bottom and the top of the device along the third direction Z. In addition, the semiconductor device 10B can also achieve excellent technical effects similar to those of the above-described embodiments.

In summary, in the semiconductor device according to the embodiment of the disclosure, the side of the contact portion is aligned with the side of the polysilicon semiconductor layer in the first opening, so that the contact portion and the polysilicon semiconductor layer have good electrical connection. The semiconductor device has excellent technical effects of improving contact problems, increasing reliability, or improving display quality. In addition, the semiconductor device can be electrically connected with the auxiliary lead through the lead to achieve the structure of the double-layer data line, so that the resistivity of the line is reduced. Since the resistivity of the auxiliary wire is smaller than that of the wire, the resistivity of the double-layer data line of the semiconductor device can be further reduced. Thus, the semiconductor device can reduce the load of the double-layer data line, increase the driving capability or improve the display quality. In addition, the semiconductor device can ensure good electrical connection by the size of the opening or does not affect the aperture ratio of the pixel. In addition, the light shielding layer can avoid the generation of light leakage current or influence on the display effect. In addition, the semiconductor device also comprises a conducting wire, an auxiliary conducting wire and a plurality of third openings which are arranged in a layered mode in the non-display area. Therefore, the wires and the auxiliary wires which are arranged in a layered mode can improve the wiring margin in the non-display area. The staggered arrangement of the third openings can avoid short circuit or improve reliability. In addition, the semiconductor device of the present disclosure may further reduce the resistivity through the widths of the auxiliary wires and the wires or the thickness of the wires, or not affect the aperture ratio of the pixels.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, comprising:

a substrate;

the polycrystalline silicon semiconductor layer is arranged on the substrate; and

a conductive line disposed on the substrate and contacting the polysilicon semiconductor layer through a contact portion,

wherein the contact portions of the polysilicon semiconductor layer and the conductive line respectively have sides aligned with each other.

2. The semiconductor device according to claim 1, wherein the wire is made of molybdenum, titanium, or a combination thereof.

3. The semiconductor device according to claim 1, further comprising an auxiliary wiring electrically connected to the wiring.

4. The semiconductor device according to claim 3, wherein a resistivity of the auxiliary wire is smaller than a resistivity of the wire.

5. The semiconductor device according to claim 3, wherein the auxiliary wire is made of gold, silver, copper, aluminum, or a combination thereof.

6. The semiconductor device according to claim 3, further comprising a first insulating layer disposed between the conductive line and the auxiliary conductive line, the first insulating layer having a first opening through which the auxiliary conductive line is electrically connected to the conductive line, wherein the first opening has a first minimum width W1 in the second direction.

7. The semiconductor device according to claim 6, further comprising a second insulating layer provided over the auxiliary conductive line, the second insulating layer having a second opening, wherein the second opening has a second minimum width W2 in the second direction, and wherein the first minimum width W1 is smaller than the second minimum width W2.

8. The semiconductor device according to claim 3, wherein a width of the auxiliary wiring in a first direction is 0.5 to 1.5 times a width of the wiring in the first direction in a normal direction of the substrate.

9. The semiconductor device according to claim 3, further comprising a plurality of third openings, wherein the auxiliary conductive line is electrically connected to the conductive line through one of the plurality of third openings, and wherein the plurality of third openings are staggered in the first direction in a normal direction of the substrate.

10. The semiconductor device according to claim 3, wherein a thickness of the auxiliary wiring is different from a thickness of the wiring.