CN112769553B - Implementation method and device for accelerating SM9 bilinear pairing operation in embedded system - Google Patents
Implementation method and device for accelerating SM9 bilinear pairing operation in embedded system Download PDFInfo
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Abstract
The present application relates to the field of information security technologies, and in particular, to a method and an apparatus for implementing an SM9 bilinear pairing operation acceleration in an embedded system. In the application, the effective operation of the bilinear pairings of the SM9 password system is realized, the time of the bilinear pairings in the operation process is reduced, and the speed of the bilinear pairings is improved.
Description
Technical Field
The present application relates to the field of information security technologies, and in particular, to a method and an apparatus for implementing an SM9 bilinear pairing operation acceleration in an embedded system.
Background
The SM9 bilinear asymmetric algorithm (SM 9 algorithm for short) is an identification cryptographic algorithm based on bilinear pairings, generates a public key pair and a private key pair of a user according to the identity of the user, and associates identity information with the cryptographic algorithm, thereby omitting the processes of digital certificate, certificate bank and key bank management. The SM9 algorithm does not need to apply for a digital certificate, and is suitable for security guarantee of various emerging applications of Internet application. Such as password service based on cloud technology, e-mail security, intelligent terminal protection, internet of things security, cloud storage security, and the like. The security applications can adopt a mobile phone number or a mail address as a public key, realize security applications such as data encryption, identity authentication, call encryption, channel encryption and the like, have the characteristics of convenient use and easy deployment, and open the door for popularizing a cryptographic algorithm.
At present, IBC (Identity-Based Cryptograph, identification cryptosystem) is rapidly developed, and the system can theoretically remove a CA certificate, so that great convenience exists in use, and as an SM9 cryptosystem of a unique set of identification cryptosystem in international, the core thereof lies in operation of bilinear pairing, and how to realize accelerating operation of bilinear pairing becomes a current technical problem to be solved urgently.
Disclosure of Invention
The application provides a method and a device for accelerating SM9 bilinear pairings operation in an embedded system, so as to realize accelerating effective operation on the bilinear pairings of an SM9 password system.
In a first aspect, a method for implementing an SM9 bilinear pairwise operation acceleration in an embedded system is provided, which includes the following steps:
step S1, the coprocessor calculates to obtain a first coordinate data and a second coordinate data according to the acquired random number, and stores the first coordinate data into a first register and the second coordinate data into a second register;
step S2, the coprocessor maps the data in the second register to third coordinate data, and stores the mapped third coordinate data in a third register;
step S3, the coprocessor acquires a second preset value and arranges the second preset value in sequence from high to low according to the bit number of the second preset value;
step S4, if the bit with the highest bit number is the non-specific bit, go to step S5 to execute the processing; if the bit with the highest current bit number is the specific bit, the step S9 is executed; if all the bit numbers of the second preset value are traversed, transferring the data corresponding to the last bit number to the step S12 for processing;
step S5, the coprocessor carries out line function point multiplication operation according to the data in the first register and the data in the third register, and stores the obtained operation result into a second data group of a fourth register;
step S6, the coprocessor performs a dot multiplication operation on the data in the third register to obtain an operation result, and updates the operation result with the data in the third register;
step S7, the coprocessor carries out twelve times of domain square operation on the first data group in the fifth register, and updates the operation result with the data in the fifth register;
step S8, the coprocessor performs twelve domain multiplication on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register; if the bit is not the last bit, sequentially selecting the bit with the highest next bit number, and then switching to the step S4 for traversal processing according to the data obtained in the steps S5 to S8; if the bit is the last bit, the data obtained based on the above operation is transferred to step S12 for processing;
step S9, the coprocessor performs a line function point add operation according to the data in the third register, the data in the first register, and the data in the second register, and updates the operation result with the data in the second data group in the fourth register;
step S10, the coprocessor performs a dot-and-add operation according to the data in the third register and the data in the second register, and updates the data in the third register with the operation result;
step S11, the coprocessor performs twelve-domain multiplication operations on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register; after sequentially selecting the bit with the highest next bit number, switching to the step S4 for traversal processing according to the data obtained in the steps S9 to S11;
step S12, the coprocessor carries out secondary domain expansion space operation according to the acquired first preset value, the acquired third preset value and the data in the second register, and stores the obtained operation result into a sixth register and a seventh register;
step S13, the coprocessor performs a dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, updates the data in the fourth register and the data in the third register with the operation result, performs twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and updates the data in the fifth register with the operation result;
and step S14, the coprocessor calculates the data in the fifth register to obtain and store a linear pair calculation result.
In one possible implementation, the step S1 includes:
the coprocessor calculates the inverse of the random number relative to a first preset value and stores an obtained operation result into an eighth register;
the coprocessor performs dot multiplication operation according to the random number and the data in the first register, and stores an operation result into the first register;
and the coprocessor performs dot product operation according to the data in the eighth register and the data in the second register and stores an operation result to the second register.
In one possible implementation, the step S2 includes:
and the coprocessor maps the two-dimensional second coordinate data in the second register to the three-dimensional third coordinate data in the third register.
In one possible implementation, the step S3 includes:
the coprocessor acquires a second preset value 6 x t +2, determines the bit number of the second preset value 6 x t +2, and arranges the bit numbers in sequence from high to low, wherein the lowest bit number is the 0 th bit.
In one possible implementation, the specific bit in the step S4 is a 1 st bit.
In one possible implementation, the step S13 includes:
the coprocessor executes a line function point addition operation according to the data in the first register, the data in the sixth register, the data in the third register and the data in the fourth register, and updates the operation result to the data in the fourth register;
the coprocessor executes secondary domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updates the operation result to the data in the third register;
the coprocessor performs twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register;
the coprocessor executes a line function point addition operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updates the operation result to the data in the fourth register;
the coprocessor executes secondary domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updates the operation result to the data in the third register;
and the coprocessor performs twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updates the operation result to the data in the fifth register.
In a second aspect, an apparatus for implementing an SM9 bilinear pairwise acceleration operation in an embedded system is provided, including:
the first processing module is used for calculating to obtain first coordinate data and second coordinate data according to the acquired random number, and storing the first coordinate data into a first register and the second coordinate data into a second register;
the second processing module is used for mapping the data in the second register to third coordinate data and storing the mapped third coordinate data into a third register;
the third processing module is used for acquiring a second preset value and sequentially arranging the second preset value according to the bit number of the second preset value from high to low; if the bit with the highest current bit number is a non-specific bit, the fourth processing module executes processing; if the bit with the highest current bit number is the specific bit, the eighth processing module executes processing;
the fourth processing module is used for performing line function point multiplication operation according to the data in the first register and the data in the third register and storing an obtained operation result into a second data group of a fourth register;
the fifth processing module is used for performing point multiplication operation on the data in the third register to obtain an operation result, and updating the data in the third register with the operation result;
the sixth processing module is used for performing twelve-time domain square operation on the first data group in the fifth register and updating the data in the fifth register with the operation result;
a seventh processing module, configured to perform twelve domain multiplication on the data in the fourth register and the data in the fifth register, and update the data in the fifth register with an operation result; if the bit is not the last bit, sequentially selecting the bit with the highest next bit number, and traversing by the third processing module according to the obtained data; if the bit is the last bit, processing the data obtained based on the operation by an eleventh processing module;
the eighth processing module is configured to perform a line function point addition operation according to the data in the third register, the data in the first register, and the data in the second register, and update the operation result with the data in the second data group in the fourth register;
the ninth processing module is used for performing dot-and-add operation on the data in the third register and the data in the second register and updating the data in the third register with the operation result;
a tenth processing module, configured to perform twelve-domain multiplication operations on the data in the fourth register and the data in the fifth register, and update the operation result with the data in the fifth register; after sequentially selecting the bit with the highest bit number, the third processing module performs traversal processing according to the obtained data;
the eleventh processing module is configured to perform secondary domain expansion space operation according to the acquired first preset value, the acquired third preset value and the data in the second register, and store an obtained operation result in a sixth register and a seventh register;
a twelfth processing module, configured to perform a dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, update the data in the fourth register and the data in the third register with an operation result, perform twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and update the data in the fifth register with the operation result;
and the thirteenth processing module is used for operating the data in the fifth register to obtain and store a linear pair operation result.
In one possible implementation, the first processing module is configured to calculate an inverse of the random number with respect to a first preset value, and store an obtained operation result in an eighth register; performing dot product operation according to the random number and data in the first register, and storing an operation result into the first register; and performing dot product operation according to the data in the eighth register and the data in the second register, and storing an operation result to the second register.
In one possible implementation manner, the second processing module is configured to map the two-dimensional second coordinate data in the second register to the three-dimensional third coordinate data in the third register, and update the data in the third register with the operation result.
In one possible implementation manner, the third processing module is configured to obtain a second preset value 6 × t +2, determine the bit numbers of the second preset value 6 × t +2, and arrange the bit numbers in sequence from high to low, where the lowest bit number is the 0 th bit.
In one possible implementation, the specific bit is a 1 st bit.
In one possible implementation, the twelfth processing module is configured to perform a line function dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the third register, and the data in the fourth register, and update the data in the fourth register with the operation result; performing a second domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updating the data in the third register with the operation result; performing twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register according to the operation result; performing a line function point-and-point operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updating the data in the fourth register with the operation result; performing a second-time domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updating the data in the third register with an operation result; and performing twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register according to the operation result.
By means of the technical scheme, the technical scheme provided by the application at least has the following advantages:
in the application, the effective operation of the bilinear pairing of the SM9 password system is realized, the time of the operation process of the bilinear pairing is reduced, and the operation speed of the bilinear pairing is also improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the embodiments of the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
fig. 1 is a schematic flowchart of an implementation method for accelerating SM9 bilinear pairwise operation in an embedded system provided in the present application;
fig. 2 is a schematic structural diagram of an implementation apparatus for accelerating SM9 bilinear pairwise operation in the embedded system provided in the present application.
Detailed Description
The present application provides a method and an apparatus for implementing an operation of accelerating SM9 bilinear pairings in an embedded system, and the following describes in detail a specific embodiment of the present application with reference to the accompanying drawings.
Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary only for the purpose of explaining the present application and are not to be construed as limiting the present application.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. As used herein, the term "and/or" includes all or any element and all combinations of one or more of the associated listed items.
It will be understood by those within the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
For the present application, several parameters are involved in the bilinear pairings operation process, including: a first preset value (P), a second preset value (constant 6 x t +2), a third preset value (constant C) and a fourth preset value (inverse C' of constant C), a first data set (f), a second data set (G), first coordinate data (point coordinates G on a primary extension area) 1 (x 1 ，y 1 ) Second coordinate data (point coordinate G on second expansion region) 2 (x 2 ，y 2 ) Jacobian coordinates G), third coordinate data 3 ’(x 2 ’,y 2 ’,z 3 ) First spatial coordinate data (spatial coordinate Q on quadratic expansion domain) 1 (Q 1 x,Q 1 y)) and second spatial coordinate data (spatial coordinate Q over a quadratic extension 2 (Q 2 x,Q 2 y))；
Wherein, the parameter P:
B640000002A3A6F1D603AB4FF58EC74521F2934B1A7AEEDBE56F9B27E351457D
t：
600000000058F98A
constant 6 × t + 2:
00000002400000000215D93E
constant C:
3F23EA58E5720BDB843C6CFA9C08674947C5C86E0DDD04EDA91D8354377B698B
C'：
88FF5C730C0B73A064E54BB6A38B7F78CA1B1AA1217BA25198DAFEA840A7DEF7
data set f and data set g are each twelve-domain data (a) 0 ,,,,,,,,,,,a 11 ) Is twelve-dimensional 256-bit data, the original value is 1, i.e. a 0 ......a 10 All are 0, a 11 A value of 1;
point coordinate G on primary extension 1 (x 1 ，y 1 )；x 1 、y 1 All 256 bits of data;
point coordinate G on quadratic expansion 2 (x 2 ，y 2 )；x 2 、y 2 All 256 bits of data;
space coordinate Q on quadratic expansion domain 1 (Q 1 x,Q 1 y) and Q 2 (Q 2 x,Q 2 y)；
And (3) outputting: e (G) 1 ,G 2 ) (linear pair output, 12 256 bits).
Based on the above parameters, as shown in fig. 1, a flow diagram of an implementation method and an implementation device for accelerating SM9 bilinear pairwise operation in an embedded system provided by the present application is provided, where the method includes the following steps:
step S1, the coprocessor calculates a first coordinate data and a second coordinate data according to the acquired random number, and stores the first coordinate data in the first register and the second coordinate data in the second register.
In a possible implementation, the coprocessor calculates the inverse of the random number with respect to the first preset value, and stores the obtained operation result in the eighth register; the coprocessor carries out dot product operation according to the random number and data in the first register, and stores an operation result into the first register; and the coprocessor performs dot product operation according to the data in the eighth register and the data in the second register and stores the operation result in the second register.
In step S2, the coprocessor maps the data in the second register to third coordinate data, and stores the mapped third coordinate data in a third register.
In one possible implementation, the coprocessor maps the two-dimensional second coordinate data in the second register to the three-dimensional third coordinate data in the third register, and updates the data in the third register with the operation result.
In step S3, the coprocessor obtains the second preset value, and the bits are sequentially arranged from high to low according to the second preset value.
In one possible implementation, the coprocessor obtains the second preset value 6 × t +2, determines the number of bits of the second preset value 6 × t +2, and arranges the bits in sequence from high to low, wherein the lowest number of bits is the 0 th bit.
And step 4, the coprocessor performs corresponding processing according to the bit number.
In a possible implementation manner, the coprocessor sequentially selects the bits with the highest current bit number according to the bit numbers from high to low, determines whether the selected bits are non-specific bits, and if the bits with the highest current bit number are non-specific bits, goes to step S5 to execute processing; if the bit with the highest current bit number is the specific bit, the process goes to step S9 to execute the process; executing corresponding cyclic processing according to the bit number from high to low; wherein, the specific bit is the 1 st bit.
In step S5, the coprocessor performs a line function point multiplication operation according to the data in the first register and the data in the third register, and stores the obtained operation result in the second data group of the fourth register.
And step S6, the coprocessor performs point multiplication operation on the data in the third register to obtain an operation result, and the operation result is updated to the data in the third register.
In step S7, the coprocessor performs twelve domain square operations on the first data set in the fifth register, and updates the operation result with the data in the fifth register.
In step S8, the coprocessor performs twelve domain multiplication operations on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register.
In a possible implementation manner, after updating the data in the fifth register according to the operation result, if the current bit is not the last bit, sequentially selecting the bit with the highest next bit number, and performing traversal processing according to the data obtained in steps S5 to S8 to step S4; if the current bit is the last bit, the data obtained based on the above operation is transferred to step S12 for processing.
In step S9, the coprocessor performs a line function dot-and-dot operation according to the data in the third register, the data in the first register, and the data in the second register, and updates the operation result with the data in the second data group in the fourth register.
And step S10, the coprocessor performs a dot-and-add operation according to the data in the third register and the data in the second register, and updates the data in the third register with the operation result.
In step S11, the coprocessor performs twelve domain multiplication operations on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register.
Further, after the operation result is updated to the data in the fifth register, the next bit with the highest bit number is sequentially selected, and the traversal processing is performed in step S4 according to the data obtained in step S9 to step S11.
And step S12, the coprocessor performs secondary domain expansion space operation according to the acquired first preset value, third preset value and data in the second register, and stores the obtained operation result into a sixth register and a seventh register.
In a possible implementation manner, if all the bit numbers corresponding to the second preset value are traversed, corresponding calculation is performed based on the data corresponding to the last bit number;
taking a first coordinate value of the coordinate data in the second register as a base number and a first preset value as an index as a first intermediate value, taking a fourth preset value as a base number and minus 2 as an index as a second intermediate value, and calculating the product of the first intermediate value and the second intermediate value to obtain a first operation result in the first space coordinate data; taking a second coordinate value of the coordinate data in the second register as a base number and a first preset value as an index as a first intermediate value, taking a fourth preset value as a base number and a minus 3 as an index as a second intermediate value, and calculating the product of the first intermediate value and the second intermediate value to obtain a second operation result in the first space coordinate data; the first operation result and the second operation result form first space coordinate data;
taking the fourth preset value as a base number and negative 4 as an index as a second intermediate value, and calculating the product of the second intermediate value and the first coordinate value of the coordinate data in the second register to obtain a first operation result in the second spatial coordinate data; taking a fourth preset value as a base number and a negative 6 as an exponent as a second intermediate value, and calculating a product of the second intermediate value and a second coordinate value of the coordinate data in the second register to obtain a second operation result in the second space coordinate data; the first operation result and the second operation result form second space coordinate data; and calculating the inverse of the second operation result in the second space coordinate data.
In step S13, the coprocessor performs a dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, updates the data in the fourth register and the data in the third register with the operation result, performs twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and updates the data in the fifth register with the operation result.
In one possible implementation manner, the coprocessor executes a line function point addition operation according to the data in the first register, the data in the sixth register, the data in the third register and the data in the fourth register, and updates the data in the fourth register with the operation result;
the coprocessor executes secondary domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updates the operation result to the data in the third register;
the coprocessor performs twelve-time domain multiplication operation on the data in the fourth register and the data in the fifth register, and updates the operation result to the data in the fifth register;
the coprocessor executes line function point addition operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updates the data in the fourth register with the operation result;
the coprocessor executes secondary domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updates the operation result to the data in the third register;
and the coprocessor performs twelve-time domain multiplication operation on the data in the fourth register and the data in the fifth register, and updates the data in the fifth register with the operation result.
And step S14, the coprocessor calculates the data in the fifth register to obtain and store the calculation result of the linear pair.
In one possible implementation manner, after updating the data in the fifth register, the coprocessor performs operation according to the updated data in the fifth register to obtain a corresponding linear pair operation result, and stores the linear pair operation result.
In the application, the effective operation of the bilinear pairings of the SM9 password system is realized, the time of the bilinear pairings in the operation process is reduced, and the speed of the bilinear pairings is improved.
Based on the above technical solution of the implementation method for accelerating SM9 bilinear pairwise operation in the embedded system provided by the present application, the present application correspondingly provides a schematic structural diagram of an implementation apparatus for accelerating SM9 bilinear pairwise operation in the embedded system, as shown in fig. 2, the implementation apparatus 20 for accelerating SM9 bilinear pairwise operation in the embedded system of the present application may include:
the first processing module 21 is configured to calculate to obtain first coordinate data and second coordinate data according to the acquired random number, and store the first coordinate data in the first register and store the second coordinate data in the second register;
the second processing module 22 is configured to map the data in the second register to third coordinate data, and store the mapped third coordinate data in a third register;
the third processing module 23 is configured to obtain a second preset value, and arrange the second preset value in sequence from high to low according to the number of bits of the second preset value; if the bit with the highest current bit number is a non-specific bit, the fourth processing module 24 performs processing; if the bit with the highest current bit number is the specific bit, the eighth processing module 28 executes the processing;
a fourth processing module 24, configured to perform a line function point multiplication operation according to the data in the first register and the data in the third register, and store an obtained operation result in a second data group of a fourth register;
a fifth processing module 25, configured to perform a dot multiplication operation on the data in the third register to obtain an operation result, and update the operation result with the data in the third register;
a sixth processing module 26, configured to perform twelve-time domain square operation on the first data group in the fifth register, and update the operation result with the data in the fifth register;
a seventh processing module 27, configured to perform twelve domain multiplication on the data in the fourth register and the data in the fifth register, and update the data in the fifth register with the operation result; if the bit is not the last bit, sequentially selecting the bit with the highest next bit number, and performing traversal processing by the third processing module 23 according to the obtained data; if the bit is the last bit, the eleventh processing module 211 processes the data obtained based on the operation;
an eighth processing module 28, configured to perform a line function point add operation according to the data in the third register, the data in the first register, and the data in the second register, and update the data in the second data group in the fourth register with the operation result;
a ninth processing module 29, configured to perform a dot-and-add operation according to the data in the third register and the data in the second register, and update the data in the third register with the operation result;
a tenth processing module 210, configured to perform twelve domain multiplication operations on the data in the fourth register and the data in the fifth register, and update the operation result with the data in the fifth register; after sequentially selecting the next bit with the highest bit number, the third processing module 23 performs traversal processing according to the obtained data;
the eleventh processing module 211 is configured to perform secondary domain expansion space operation according to the acquired first preset value, the acquired third preset value, and data in the second register, and store an obtained operation result in a sixth register and a seventh register;
a twelfth processing module 212, configured to perform a dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, update the data in the fourth register and the data in the third register with the operation result, perform twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and update the data in the fifth register with the operation result;
and the thirteenth processing module 213, configured to perform an operation on the data in the fifth register to obtain and store a linear pair operation result.
In a possible implementation manner, the first processing module 21 is configured to calculate an inverse of the random number with respect to the first preset value, and store the obtained operation result in the eighth register; performing dot product operation according to the random number and data in the first register, and storing an operation result into the first register; and performing dot product operation according to the data in the eighth register and the data in the second register, and storing the operation result into the second register.
In one possible implementation, the second processing module 22 is configured to map the two-dimensional second coordinate data in the second register to the three-dimensional third coordinate data in the third register.
In one possible implementation, the third processing module 23 is configured to obtain a second preset value 6 × t +2, determine the number of bits of the second preset value 6 × t +2, and arrange the bits in order from high to low, where the lowest number of bits is the 0 th bit.
In one possible implementation, the particular bit is the 1 st bit.
In one possible implementation, the twelfth processing module 212 is configured to perform a line function dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the third register, and the data in the fourth register, and update the data in the fourth register with the operation result; performing secondary domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updating the data in the third register according to the operation result; performing twelve-domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register with the operation result; performing a line function point-and-point operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updating the data in the fourth register with the operation result; performing secondary domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updating the data in the third register according to the operation result; and performing twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register according to the operation result.
In the application, the effective operation of the bilinear pairings of the SM9 password system is realized, the time of the bilinear pairings in the operation process is reduced, and the speed of the bilinear pairings is improved.
It will be understood by those within the art that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. Those skilled in the art will appreciate that the computer program instructions may be implemented by a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the aspects specified in the block diagrams and/or flowchart block or blocks of the present disclosure.
The modules of the device can be integrated into a whole or can be separately deployed. The modules may be combined into one module, or further split into a plurality of sub-modules.
Those skilled in the art will appreciate that the drawings are merely schematic representations of one preferred embodiment and that the blocks or flow diagrams in the drawings are not necessarily required to practice the present application.
Those skilled in the art can understand that the modules in the devices in the embodiments can be distributed in the devices in the embodiments according to the description of the embodiments, and the modules can be located in one or more devices different from the embodiments with corresponding changes. The modules of the above embodiments may be combined into one module, or further split into multiple sub-modules.
The above application serial numbers are for descriptive purposes only and do not represent the merits of the embodiments.
The disclosure of the present application is only a few specific embodiments, but the present application is not limited to these, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present application.
Claims (12)
1. A realization method for accelerating SM9 bilinear pairing operation in an embedded system is characterized by comprising the following steps:
step S1, the coprocessor calculates to obtain a first coordinate data and a second coordinate data according to the acquired random number, and stores the first coordinate data into a first register and the second coordinate data into a second register;
step S2, the coprocessor maps the data in the second register to third coordinate data, and stores the mapped third coordinate data in a third register;
step S3, the coprocessor acquires a second preset value and arranges the second preset value in sequence from high to low according to the bit number of the second preset value;
step S4, if the bit with the highest bit number is the non-specific bit, go to step S5 to execute the processing; if the bit with the highest current bit number is the specific bit, the process goes to step S9 to execute the process;
step S5, the coprocessor carries out line function point multiplication operation according to the data in the first register and the data in the third register, and stores the obtained operation result into a second data group of a fourth register;
step S6, the coprocessor performs a dot multiplication operation on the data in the third register to obtain an operation result, and updates the operation result with the data in the third register;
step S7, the coprocessor carries out twelve times of domain square operation on the first data group in the fifth register, and updates the operation result with the data in the fifth register;
step S8, the coprocessor performs twelve-domain multiplication on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register; if the bit is not the last bit, sequentially selecting the bit with the highest next bit number, and then switching to the step S4 for traversal processing according to the data obtained in the steps S5 to S8; if the bit is the last bit, the data obtained based on the above operation is transferred to step S12 for processing;
step S9, the coprocessor performs a line function point add operation according to the data in the third register, the data in the first register, and the data in the second register, and updates the operation result with the data in the second data group in the fourth register;
step S10, the coprocessor performs a dot-and-add operation according to the data in the third register and the data in the second register, and updates the data in the third register with the operation result;
step S11, the coprocessor performs twelve domain multiplication operations on the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register; after sequentially selecting the bit with the highest next bit number, turning to step S4 for traversal processing according to the data obtained in steps S9 to S11;
step S12, the coprocessor carries out secondary domain expansion space operation according to the acquired first preset value, the acquired third preset value and the data in the second register, and stores the obtained operation result into a sixth register and a seventh register;
step S13, the coprocessor performs a dot-and-dot operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, updates the data in the fourth register and the data in the third register with the operation result, and performs twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and updates the data in the fifth register with the operation result;
and step S14, the coprocessor calculates the data in the fifth register to obtain and store a linear pair calculation result.
2. The method according to claim 1, wherein the step S1 includes:
the coprocessor calculates the inverse of the random number relative to a first preset value and stores an obtained operation result into an eighth register;
the coprocessor carries out dot product operation according to the random number and the data in the first register and stores an operation result into the first register;
and the coprocessor performs dot product operation according to the data in the eighth register and the data in the second register and stores an operation result to the second register.
3. The method according to claim 2, wherein the step S2 includes:
and the coprocessor maps the two-dimensional second coordinate data in the second register to the three-dimensional third coordinate data in the third register.
4. The method according to claim 1, wherein the step S3 includes:
the coprocessor acquires a second preset value 6 x t +2, determines the bit number of the second preset value 6 x t +2, and arranges the bit number from high to low in sequence, wherein the lowest bit number is a 0 th bit, and t is 600000000058F 98A.
5. The method of claim 1, wherein the specific bit in the step S4 is a 1 st bit.
6. The method according to claim 3, wherein the step S13 includes:
the coprocessor executes a line function point addition operation according to the data in the first register, the data in the sixth register, the data in the third register and the data in the fourth register, and updates the operation result to the data in the fourth register;
the coprocessor executes secondary domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updates the operation result to the data in the third register;
the coprocessor performs twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updates the operation result with the data in the fifth register;
the coprocessor executes a line function point addition operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updates the operation result to the data in the fourth register;
the coprocessor executes secondary domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updates the operation result to the data in the third register;
and the coprocessor performs twelve-time domain multiplication operation on the data in the fourth register and the data in the fifth register, and updates the operation result to the data in the fifth register.
7. An apparatus for accelerating SM9 bilinear pairwise operation in an embedded system, comprising:
the first processing module is used for calculating to obtain first coordinate data and second coordinate data according to the acquired random number, and storing the first coordinate data into a first register and the second coordinate data into a second register;
the second processing module is used for mapping the data in the second register to third coordinate data and storing the mapped third coordinate data into a third register;
the third processing module is used for acquiring a second preset value and sequentially arranging the second preset value according to the bit number of the second preset value from high to low; if the bit with the highest current bit number is a non-specific bit, the fourth processing module executes processing; if the bit with the highest current bit number is the specific bit, the eighth processing module executes processing;
the fourth processing module is used for performing line function point multiplication operation according to the data in the first register and the data in the third register and storing an obtained operation result into a second data group of a fourth register;
the fifth processing module is used for performing point multiplication operation on the data in the third register to obtain an operation result, and updating the data in the third register with the operation result;
the sixth processing module is used for performing twelve-time domain square operation on the first data group in the fifth register and updating the data in the fifth register with the operation result;
a seventh processing module, configured to perform twelve-domain multiplication on the data in the fourth register and the data in the fifth register, and update the data in the fifth register with an operation result; if the bit is not the last bit, sequentially selecting the bit with the highest next bit number, and performing traversal processing by the third processing module according to the obtained data; if the bit is the last bit, processing the data obtained based on the operation by an eleventh processing module;
the eighth processing module is configured to perform a line function point addition operation according to the data in the third register, the data in the first register, and the data in the second register, and update the operation result with the data in the second data group in the fourth register;
the ninth processing module is used for performing a dot-and-add operation on the data in the third register and the data in the second register and updating the data in the third register with the operation result;
a tenth processing module, configured to perform twelve domain multiplication on the data in the fourth register and the data in the fifth register, and update the data in the fifth register with an operation result; after sequentially selecting the bit with the highest bit number, the third processing module performs traversal processing according to the obtained data;
the eleventh processing module is configured to perform secondary domain expansion space operation according to the acquired first preset value, the acquired third preset value and the data in the second register, and store an obtained operation result in a sixth register and a seventh register;
a twelfth processing module, configured to perform a dot-and-add operation according to the data in the first register, the data in the sixth register, the data in the seventh register, the data in the third register, and the data in the fourth register, update the data in the fourth register and the data in the third register with an operation result, perform twelve domain multiplication operations according to the data in the fourth register and the data in the fifth register, and update the data in the fifth register with the operation result;
and the thirteenth processing module is used for operating the data in the fifth register to obtain and store a linear pair operation result.
8. The apparatus of claim 7, wherein the first processing module is configured to compute an inverse of the random number with respect to a first preset value, and store a result of the computation in an eighth register; performing dot product operation according to the random number and data in the first register, and storing an operation result into the first register; and performing dot product operation according to the data in the eighth register and the data in the second register, and storing an operation result into the second register.
9. The apparatus of claim 8, wherein the second processing module is to map second coordinate data in two dimensions in a second register to third coordinate data in three dimensions in a third register.
10. The apparatus of claim 7, wherein the third processing module is configured to obtain a second preset value 6 × t +2, determine the number of bits of the second preset value 6 × t +2, and arrange the bits in order from high to low, wherein the lowest number of bits is 0 th bit, and t is 600000000058F 98A.
11. The apparatus of claim 7, wherein the specific bit is a 1 st bit.
12. The apparatus of claim 9, wherein the twelfth processing module is configured to perform a line function dot-and-add operation on the data in the first register, the data in the sixth register, the data in the third register, and the data in the fourth register, and update the data in the fourth register with the operation result; performing a second domain expansion point addition operation according to the data in the sixth register and the data in the third register, and updating the data in the third register with the operation result; performing twelve-time domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register according to the operation result; performing a line function point addition operation according to the data in the first register, the data in the seventh register, the data in the third register and the data in the fourth register, and updating the data in the fourth register with the operation result; performing a second-time domain expansion point addition operation according to the data in the seventh register and the data in the third register, and updating the data in the third register with an operation result; and performing twelve-domain multiplication operation according to the data in the fourth register and the data in the fifth register, and updating the data in the fifth register according to the operation result.
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