CN112736105A - CMOS image sensor and manufacturing method thereof - Google Patents
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000009792 diffusion process Methods 0.000 claims abstract description 55
- 238000002955 isolation Methods 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 122
- 238000002161 passivation Methods 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 239000002356 single layer Substances 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 11
- 239000003990 capacitor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000000746 purification Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
The invention provides a CMOS image sensor and a manufacturing method thereof, comprising the following steps: forming an isolation region in a semiconductor substrate, defining an active region of a unit pixel of a CMOS image sensor; forming a gate electrode on a semiconductor substrate; forming a mask layer covering a boundary region of the isolation region; performing ion implantation of impurities using the mask layer; a diffusion region for clamping the photodiode is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region. By implanting impurities in the boundary portion between the diffusion regions, damage of the clamp photodiode PDD and the isolation region is prevented, and dark current in the CMOS image sensor is reduced.
Description
Technical Field
The invention relates to the technical field of CMOS image sensors and manufacturing methods thereof, in particular to a CMOS image sensor for reducing dark current and a manufacturing method thereof.
Background
Generally, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally classified into a Charge Coupled Device (CCD) and a complementary mos (cmos) image sensor.
A CCD typically includes a plurality of MOS capacitors, each placed adjacent to the other, storing charge on one of the MOS capacitors, and then transferring to one of the MOS capacitors next to the MOS capacitor. The CCD has the disadvantages of complicated driving method, high power consumption, complicated manufacturing process, various processing steps, and the like. In addition, the CCD has a disadvantage in that it is difficult to manufacture a compact product because it is difficult to integrate various circuits such as a control circuit, a signal processing circuit, an analog/digital conversion circuit, and the like into a single chip.
Currently, CMOS image sensors are receiving increasing attention as a next-generation image sensor that overcomes the disadvantages of the CCD. Each unit pixel of the CMOS image sensor is a switching device of a photodiode and a MOS transistor formed on a semiconductor substrate using CMOS technology. The CMOS image sensor generally includes peripheral circuits such as a control circuit, a signal processing circuit, and the like, and sequentially detects the output of each unit pixel through a MOS transistor. Therefore, the CMOS image sensor sequentially detects an electric signal of each unit pixel in a switching mode with a photodiode and a MOS transistor formed in each unit pixel to acquire an image.
The CMOS image sensor has the advantages of low power consumption, simple manufacturing process, few processing steps and the like. In addition, the CMOS image sensor has an advantage that a product is compact into one chip by integrating a control circuit, a signal processing circuit, an analog/digital conversion circuit, and the like. Therefore, CMOS image sensors are now widely used in various applications such as digital still cameras, digital cameras, and the like.
Fig. 1 shows a circuit diagram of a unit pixel of a conventional CMOS image sensor. As shown in fig. 1, a unit pixel 100 of a CMOS image sensor includes a photodiode 110 as a photoelectric conversion portion and four transistors including a transfer transistor 120, a reset transistor 130, a driving transistor 140, and a selection transistor 150. The output terminal of the unit pixel 100 is connected to the load transistor 160, where FD denotes a floating diffusion region, TX denotes a gate voltage of the transfer transistor 120, RX denotes a gate voltage of the reset transistor 130, DX denotes a gate voltage of the drive transistor 140, and Sx denotes a gate voltage of the selection transistor 150.
Fig. 2 shows a layout of a unit pixel of a conventional CMOS image sensor. As shown in fig. 2, in the unit pixel 100, the active area is an area defined by a bold solid line. The isolation region 13 is a region where an isolation layer (not shown) is formed outside the active region. The gates 123 of the transfer transistor 120, reset transistor 130, drive transistor 140 and select transistor 150 are arranged as shown in fig. 2. FD denotes a floating diffusion region, and PD denotes a portion of the photodiode 110.
Fig. 3 is a structural cross-sectional view of a photodiode of a unit pixel. As shown in fig. 3, one P-The epitaxial layer 11 is in P++Formed on a type semiconductor substrate 10. Wherein P is++Indicating a heavily doped region. To define the active region of the semiconductor substrate, isolation regions 13, one n, are formed in a portion of the epitaxial layer- Type diffusion regions 111 and PoP of the photodiode 110 is formed in a portion P of the epitaxial layero Type diffusion region 113, PoThe type diffusion region 113 is located at n-A type diffusion region 111. Wherein n is-Indicating low doping rate, PoIndicating dielectric doping of the impurity.
The conventional CMOS image sensor has a structure having a disadvantage in that performance and electric buffer capacity are degraded due to an increase in dark current, which is generated by transfer of electrons from the photodiode 110 to a floating diffusion region when no light is received by the photodiode 110.
It is reported that the dark current is generally caused by various defects, dangling bonds, etc., in the adjacent portions of the surface of the semiconductor substrate, the isolation regions 13 and PoA boundary portion of the type diffusion region 113. Isolation regions 13 and n-A boundary portion of the type diffusion region 111. Po Type diffusion regions 113 and n-A type diffusion region 111. By using two Po Type diffusion regions 113 and n-The photodiode composed of the type diffusion region 111 reduces dark current generated at a portion near the surface of the silicon substrate as compared with a conventional CMOS image sensor.
However, the conventional CMOS image sensor suffers from the isolation regions 13 and PoThe boundary portion of (a) has a large influence of dark current. Po Type diffusion region 113 at Po Type diffusion regions 113 and n-A type diffusion region 111.
In particular, as shown in fig. 3. When a photoresist pattern (not shown) is used for ion implantation to form n- Type diffusion region 111, PoThe type diffusion region 113 forms a diffusion region on the semiconductor substrate is an active region ion-implanted in the photodiode, and these impurities are also ion-implanted to a boundary portion between the active region and the photodiode 110.
Therefore, the damage is caused by implanting impurities into n-/PoThe boundary portion between the type diffusion regions and the defects of the isolation region 13 are further caused. Defects may cause electron or hole carriers and provide recombination centers, the generation of electrons and holes thereby increasing the leakage current of the photodiode and the dark current of the CM0S image sensor.
As described above, the conventional CMOS image sensor has a structure in which, when the secondary region of the photodiode is formed, impurities are also ion-implanted into the boundary portion between the isolation region and the active region, thereby increasing the dark current of the photodiode. Furthermore, the method is simple. It is difficult to maintain uniform device characteristics among pixels of the image sensor due to such a structure. Thus, the performance of conventional image sensors is generally not ideal.
Disclosure of Invention
In view of the above problems, the present invention provides a CMOS image sensor and a method for manufacturing the same, which introduces a clamp photodiode structure to reduce dark current in the CMOS image sensor.
The present invention provides a structure of a CMOS image sensor, including: forming an isolation region in a semiconductor substrate, defining an active region of a unit pixel of a CMOS image sensor; forming a gate on the semiconductor substrate; forming a mask layer covering a boundary region of the isolation region; performing ion implantation of impurities using the mask layer; a diffusion region of the clamping photodiode is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region.
Preferably, the surface of the clamping photodiode structure is highly doped with P+The clamping layer is made of Si/Si02The interface is isolated from the buried N layer of the charge collection region to reduce dark current generated therein.
Preferably, further comprising forming a passivation layer on the gate electrode; the passivation layer is composed of an insulating layer.
Preferably, the passivation layer includes any one of a single layer of oxide or a single layer of nitride; the passivation layer may further include at least one oxide layer and at least one nitride layer of a plurality of layers.
A method of fabricating a CMOS image sensor, comprising the steps of:
s1: forming an isolation region in a semiconductor substrate, defining an active region of a unit pixel of a CMOS image sensor;
s2: forming a gate on the semiconductor substrate; forming a mask layer covering a boundary region of the isolation region; performing ion implantation of impurities using the mask layer;
s3: a diffusion region of the clamping photodiode is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region.
Preferably, step 2 further comprises forming a passivation layer after the formation of the gate; the passivation layer is composed of an insulating layer.
Preferably, the passivation layer includes any one of a single oxide layer or a single nitride layer.
Preferably, the passivation layer comprises a plurality of layers of at least one oxide layer and at least one nitride layer.
Preferably, the mask layer is a photoresist layer.
Preferably, the semiconductor substrate is P++A type silicon substrate on which a P-type epitaxial layer is formed, and a diffusion region of the clamp photodiode has an n-type diffusion region; forming a Po-type diffusion region in the n-type diffusion region of the clamped photodiode to reduce the formation ofDark current generated on the surface of the semiconductor substrate.
The invention can obtain the following beneficial effects:
1. impurities are implanted through a boundary portion between the diffusion regions.
2. Damage to the clamp photodiode PDD and the isolation region is prevented, and dark current in the CMOS image sensor is reduced.
3. High doping P on the surface of clamping photodiode structure+The clamping layer is made of Si/Si02The interface is isolated from the buried N layer of the charge collection region to reduce dark current generated therein.
Drawings
Fig. 1 is a unit pixel circuit of a conventional CMOS image sensor in the related art.
Fig. 2 is a layout of a unit pixel of a conventional CMOS image sensor in the related art.
Fig. 3 is a structural cross-sectional view of a photodiode of a unit pixel.
Fig. 4 is a diagram of a clamped photodiode structure of a CMOS image sensor and a method of fabricating the same according to the present invention.
Fig. 5 is a layout of a unit pixel of a CMOS image sensor and a method of fabricating the same according to the present invention.
Fig. 6 is a cross-sectional view of a clamping photodiode of one unit pixel of a CMOS image sensor and a method of fabricating the same of the present invention.
Fig. 7 is a transfer gate cross-sectional view of a clamping photodiode of one unit pixel of a CMOS image sensor and a method of fabricating the same of the present invention.
Fig. 8A to 8D are flow charts of a fabrication process of a CMOS image sensor and a method of fabricating the same according to the present invention.
Wherein the reference numerals are:
unit pixel 100, P++ Type semiconductor substrate 10, P-Epitaxial layer 11, isolation region 13, photodiode 110, n- Type diffusion region 111, Po Type diffusion region 113, transfer transistor 120, reset transistor 130, drive transistor 140, selection transistor 150, and a gate electrode,Load transistor 160, gate electrode 123, semiconductor substrate 20, epitaxial layer 21, isolation region 23, unit pixel 200, clamp photodiode 210, transfer transistor 220, reset transistor 230, drive transistor 240, select transistor 250, passivation layer 260, gate insulating layer 212, gate electrode 223, opening 231, photoresist pattern 232, n- Type diffusion region 211, PoAnd a type diffusion region 213.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not to be construed as limiting the invention.
A CMOS image sensor and a method for fabricating the same according to the present invention will be described in detail.
The invention provides a CMOS image sensor and a manufacturing method thereof, comprising the following steps: forming an isolation region in a semiconductor substrate, defining an active region of a unit pixel of a CMOS image sensor; forming a gate on the semiconductor substrate; forming a mask layer covering a boundary region of the isolation region; performing ion implantation of impurities using the mask layer; a diffusion region of the clamping photodiode is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region.
In the examples of the present invention, P++The type representing a high concentration PoRepresents a medium concentration of P type, N-Type indicates a low concentration of N-type.
Fig. 4 is a diagram of a clamped photodiode structure of a CMOS image sensor and a method of fabricating the same according to the present invention.
As shown in fig. 4, the present invention introduces a clamp photodiode-PDD, which is a photosensitive structure, that is the preferred device in solid-state image sensors due to CMOS high quantum efficiency and low dark current, and the associated double sampling of the readout process tends to reduce noise readout by canceling reset noise and mitigating low frequency noise. Consider when P+Depletion regions of N and PN junctions are the case when N layers are merged. PliersThe n-layer of the bit photodiode is fully depleted as shown in figure 4. n marks P+And the edge between the n layers, and xp marks the boundary between the latter and the epitaxial p-block. Xp1 is P+The depletion side of the N-junction is abscissa and Xp2 is the depletion side of the p-junction.
Fig. 5 is a layout of a unit pixel of a CMOS image sensor and a method of fabricating the same according to the present invention.
In the unit pixel 200, a solid line indicates an active region where a clamp photodiode-PDD is to be formed, and is defined by an isolation region (not shown) formed around the active region. The gates 223 of the transfer transistor 220, the reset transistor 230, the drive transistor 240, and the selection transistor 250 are respectively provided as shown in fig. 5.
In order to prevent the boundary portion of the active region from being damaged by ion implantation of impurities. An extension passivation layer 260 is disposed on a boundary portion between the active region and the isolation region. FD denotes a floating diffusion region.
Although the unit pixel 200 is shown in fig. 5 as being composed of one clamping photodiode and four transistors, it may be composed of one phototransistor and three transistors, for example, a reset transistor 230, a driving transistor 240 and a selection transistor 250. For convenience of explanation, the present invention will be described using a unit pixel having one phototransistor and four transistors.
Fig. 6 is a cross-sectional view of a clamping photodiode of one unit pixel of a CMOS image sensor and a method of fabricating the same of the present invention.
Fig. 7 is a transfer gate cross-sectional view of a clamping photodiode of one unit pixel of a CMOS image sensor and a method of fabricating the same of the present invention.
As shown in fig. 6 and 7, P-A type epitaxial layer 21 is formed on the P-type semiconductor substrate 20. To define the active area of the semiconductor substrate 20. Isolation regions 23 are formed on a portion of the epitaxial layer 21.
A purification layer 260 is formed on the gate insulating layer 212 and the isolation region 23. The purification layer 260 may be composed of an insulating layer. Any one of a single layer of an oxide layer and a nitride layer, or a multilayer of at least one oxide layer and at least one nitride layer. The isolation region 23 may be formed by a Shallow Trench Isolation (STI) process or local oxidation of silicon (LO-COS). A gate insulating layer 221 and a gate 223 of the transfer transistor 220 are formed on a portion of the epitaxial layer 21.
In the CMOS image sensor as described above, since the passivation layer 260 protects the isolation region 23 and the gate insulating layer 212 of the active region, clamps the photodiode, forms n-/PoThe clamp photodiodes of the diffusion regions 211 and 213 are not ion-implanted to the gate insulating layer 212.
The image sensor structure of the present invention reduces the number of isolation regions 23 and n-The leakage current generated at the boundary portion between them also reduces the dark current. Therefore, the image sensor according to the present invention can have uniform device characteristics between unit pixels and improve dark current characteristics, charge storage capacity, and other device characteristics.
A method of fabricating a CMOS image sensor according to an embodiment of the present invention will now be described with reference to fig. 8A to 8D.
As shown in fig. 8A, a semiconductor substrate 20 is provided. The semiconductor substrate 20 may include a heavily doped material such as P++A type substrate. On the surface of a semiconductor substrate 20 to be formed into a device, a lightly doped P-The epitaxial layer 21 is grown by an epitaxial process. For the epitaxial layer 21. The clamp photodiode PDD formed therein later may have a deep and large depletion region and thus may have a better ability to collect photocharges or improve photosensitivity. To define an active region, the transfer transistor 220, the reset transistor 230, the drive transistor 240, and the select transistor 250, as well as the active region of the photodiode, an isolation region 23 is formed in a portion of the epitaxial layer 21. The isolation region 23 may be formed by an STI process or a LOCOS process.
Then, a gate insulating layer transfer transistor 220, a reset transistor 230, a driving transistor 240, and a selection transistor 250 of fig. 5. A desired thickness is formed on the epitaxial layer 21 throughout the active region including the active region of the photodiode PD. In one aspect, the gate insulating layer may include a thermal oxide layer grown by a thermal oxidation process.
A conductive gate layer, a high concentration polysilicon layer, is then formed on the gate insulating layer to a desired thickness. In one aspect, the conductive shelf layer may include a high concentration polysilicon layer and a silicide layer formed thereon.
After the gate layer is formed, the conductive gate layer and the gate insulating layer are etched using a mask (not shown) to form gates 223, 233, 243, and 253. The transfer transistor 220 and the gate layer 223, the reset transistor 230, the drive transistor 240, and the selection transistor 250 of fig. 7 having a structure including a gate insulating layer also have the same structure as the transfer transistor 220.
A passivation insulating layer is then deposited by Chemical Vapor Deposition (CVD), low pressure CVD, to a thickness over the semiconductor substrate 20, including the active region of the photodiode PD. In a certain aspect, the passivation insulating layer may be composed of an insulating layer composed of any one of an oxide layer and a nitride layer, or may be composed of a multilayer of at least one oxide layer and at least one nitride layer.
Then, as shown in fig. 8B, the passivation insulating layer is etched by wet or dry etching to form a passivation layer 260. In one aspect, the passivation layer 260 may extend the isolation region 23 to the active region of the clamping photodiode PPp. In other words, the passivation layer 260 covers the isolation region 23 and the gate insulating layer 212 of the active region beside the isolation region 23. In another aspect, the purification layer 260 extends through the boundary region between the active region and the isolation region 23.
As shown in fig. 8C, a photoresist pattern 232 having an opening 231 is formed on the semiconductor substrate 20 to expose an active region of the clamping photodiode PDD. In one aspect, the passivation layer 260 masks the gate insulating layer 212 of the active region-The type diffusion region 211 is substantially exposed at the passivation layer 260.
Then, n-type impurities are implanted into the exposed epitaxial layer 21 at a low concentration and high energy to form n, using the photoresist pattern 232 and the passivation layer 260 as a mask layer-The type diffusion region 211.
As shown in fig. 8D, the photoresist pattern 232 and the purification layer 260 are again usedAs a mask, p-type impurities are implanted into n at medium concentration and low energy- Type diffusion region 211 in which P of the photodiode is formedoAnd a type diffusion region.
Thus, embodiments of the present invention prevent isolation regions 23 and n-Gate insulating layer 212n therebetween- Type diffusion regions 211 and PoThe type diffusion region 213 is not damaged by the n-type and p-type impurity ion implantation, thereby preventing defects from being formed due to damage. Accordingly, the dark current of the CMOS image sensor according to the present invention is reduced.
As described above. In the CMOS image sensor and the method of fabricating the same of the present invention, the gate electrode of the transistor of the CMOS image sensor is formed in the active region of the unit pixel, and the passivation layer composed of an insulating material is formed on the semiconductor substrate and covers a portion of the active region adjacent to the isolation region, separating the active region of the clamp photodiode 210 from the isolation region. Accordingly, impurities forming the secondary region of the photodiode are ion-implanted into the active region of the photodiode, wherein the passivation layer prevents the boundary portion of the active region from being ion-implanted. Therefore, the present invention implants impurities through the boundary portion between the diffusion regions. Damage to the clamping photodiode and the isolation region is prevented, and dark current in the CMOS image sensor is reduced.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
The above embodiments of the present invention should not be construed as limiting the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the protection scope of the claims of the present invention.
Claims (10)
1. A structure of a CMOS image sensor, comprising: forming an isolation region (23) in a semiconductor substrate (20) defining an active region of a unit pixel (200) of a CMOS image sensor; forming a gate electrode (223) on the semiconductor substrate (20); forming a mask layer covering a boundary region of the isolation region; performing ion implantation of impurities using the mask layer; a diffusion region for clamping the photodiode (210) is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region (23).
2. The structure of a CMOS image sensor as in claim 1, characterized by a high doping P of the surface of the clamping photodiode (210) structure+The clamping layer is made of Si/Si02The interface is isolated from the buried N layer of the charge collection region to reduce dark current generated therein.
3. The CMOS image sensor structure of claim 1, further comprising forming a passivation layer (260) over the gate; the passivation layer (260) is composed of an insulating material.
4. The structure of the CMOS image sensor of claim 3, wherein the passivation layer comprises any one of a single layer of oxide or a single layer of nitride; the passivation layer may further include at least one oxide layer and at least one nitride layer of a plurality of layers.
5. A method of fabricating a CMOS image sensor, comprising the steps of:
s1: forming an isolation region (23) in the semiconductor substrate, defining an active region of a unit pixel of the CMOS image sensor;
s2: forming a gate (223) on the semiconductor substrate; forming a mask layer covering the border area of the isolation region (23); performing ion implantation of impurities using the mask layer;
s3: a diffusion region that clamps a photodiode (210) is formed in a portion of the active region, wherein the diffusion region is formed spaced apart from the isolation region.
6. The method of fabricating a CMOS image sensor according to claim 5, wherein the step 2 further comprises forming a passivation layer (260) after the formation of the gate electrode (223); the passivation layer (260) is composed of an insulating material.
7. The method of manufacturing a CMOS image sensor according to claim 5, wherein the passivation layer includes any one of a single oxide layer or a single nitride layer.
8. The method of manufacturing a CMOS image sensor according to claim 5, wherein the passivation layer includes at least one oxide layer and at least one nitride layer of a plurality of layers.
9. The method of manufacturing a CMOS image sensor according to claim 5, wherein the mask layer is a photoresist layer.
10. The method of manufacturing the CMOS image sensor of claim 5, wherein the semiconductor substrate is P++A type silicon substrate having a P type epitaxial layer (21) formed thereon, and the diffusion region of the clamping photodiode (210) has n-A type diffusion region (211); the n of the clamped photodiode (210)-Median shape of diffusion region (211)To PoA type diffusion region (213) that reduces dark current generated on a surface of the semiconductor substrate (20).
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117766556A (en) * | 2023-12-25 | 2024-03-26 | 脉冲视觉(北京)科技有限公司 | Photosensitive device, preparation method thereof and sensor pixel unit |
| CN118016749A (en) * | 2024-04-09 | 2024-05-10 | 长三角物理研究中心有限公司 | Photodiode and photodiode unit of CMOS image sensor |
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| US20050062084A1 (en) * | 2003-09-23 | 2005-03-24 | Han Chang Hun | CMOS image sensor and method for manufacturing the same |
| CN1877847A (en) * | 2005-06-07 | 2006-12-13 | 东部电子株式会社 | CMOS image sensor and method for manufacturing the same |
| CN102683373A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Large-sensitization area CMOS image sensor pixel structure and generation method thereof |
| CN102695008A (en) * | 2012-05-07 | 2012-09-26 | 天津大学 | CMOS image sensor pixel structure for fast transfer of large-size pixel charge |
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| US20050062084A1 (en) * | 2003-09-23 | 2005-03-24 | Han Chang Hun | CMOS image sensor and method for manufacturing the same |
| CN1877847A (en) * | 2005-06-07 | 2006-12-13 | 东部电子株式会社 | CMOS image sensor and method for manufacturing the same |
| CN102695008A (en) * | 2012-05-07 | 2012-09-26 | 天津大学 | CMOS image sensor pixel structure for fast transfer of large-size pixel charge |
| CN102683373A (en) * | 2012-05-10 | 2012-09-19 | 天津大学 | Large-sensitization area CMOS image sensor pixel structure and generation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117766556A (en) * | 2023-12-25 | 2024-03-26 | 脉冲视觉(北京)科技有限公司 | Photosensitive device, preparation method thereof and sensor pixel unit |
| CN118016749A (en) * | 2024-04-09 | 2024-05-10 | 长三角物理研究中心有限公司 | Photodiode and photodiode unit of CMOS image sensor |
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