CN112685802B

CN112685802B - Flash chip reading control method and device and storage medium

Info

Publication number: CN112685802B
Application number: CN202011576074.1A
Authority: CN
Inventors: 沈有琪; 李金亭; 刘西富; 朱文清
Original assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Current assignee: Qingdao Xinxin Microelectronics Technology Co Ltd
Priority date: 2020-12-28
Filing date: 2020-12-28
Publication date: 2022-07-01
Anticipated expiration: 2040-12-28
Also published as: CN112685802A

Abstract

The application discloses a Flash chip reading control method, a Flash chip reading control device and a storage medium. The method is used for solving the problem that the embedded flash in the microcontroller chip is maliciously copied by a third party. In the embodiment of the application, different reading protection is carried out on the embedded flash program aiming at the access of different debugging tools to the chip, and the chip program is ensured not to be erased and rewritten accidentally through configuration parameters in an electromagnetic interference environment.

Description

Flash chip reading control method and device and storage medium

Technical Field

The present application relates to the field of microcontroller chip technologies, and in particular, to a Flash chip read control method, apparatus, and storage medium.

Background

At present, an embedded memory chip (flash) in a microcontroller chip is widely used as a program storage medium, along with the development cost of the chip being higher and higher, the security of the chip program and the stability of the product are more and more important, after the product carrying the chip is produced, a third party manufacturer can read the program in the embedded flash through various debugging tools, repeatedly etch a printed circuit board of the product, burn the read program content into the circuit board and apply the program content to the product, and the purposes of cloning the product and saving the development cost are achieved, and the behavior causes great threat to the development and production of the product.

Disclosure of Invention

The application aims to provide a flash chip reading control method, a flash chip reading control device and a flash chip reading control storage medium, which are used for solving the problem that an embedded flash in a microcontroller chip is maliciously copied by a third party.

In a first aspect, an embodiment of the present application provides a flash chip reading control method, including:

and if the JTAG debugging signal of the JATG debugging tool and the protection level signal of the flash chip are both effective, configuring the operation authority of the JTAG debugging tool into a prohibition authority, wherein the prohibition authority is used for allowing the JTAG debugging tool to read the nonvolatile register sector and prohibiting the JTAG debugging tool from operating the main sector.

If at least one of the JTAG debugging signal and the protection level signal is invalid, configuring the operation authority of the JTAG debugging tool as an permission authority, wherein the permission authority is used for allowing the JTAG debugging tool to operate the main sector and the nonvolatile register sector.

In some possible embodiments, if the operation authority of the JTAG debugging tool is a disable authority, the method further includes:

receiving first indication information which is sent by the JTAG debugging tool and used for changing the forbidding authority into the allowing authority;

and in response to the first indication information, deleting the information in the main sector and changing the prohibition authority into the permission authority.

In some possible embodiments, a permission parameter for indicating the operation permission of the JTAG debugging tool is configured in the non-volatile register sector, and the deleting the information in the main sector and changing the prohibition permission to the permission include:

if the de-erasing protection signal is valid, performing an erasing operation on the non-volatile register sector;

and if the erasing operation is successfully executed and the de-write protection signal is determined to be valid, configuring the permission parameter in the nonvolatile register sector as the permission.

In some possible embodiments, if the operation permission of the JTAG debug tool is an enable permission, the method further includes:

receiving second indication information which is sent by the JTAG debugging tool and used for changing the permission authority into the prohibition authority;

and changing the permission right into the prohibition right in response to the second indication information.

In some possible embodiments, the changing the permission right to the prohibition right includes:

and if the de-erasing protection signal is valid, performing an erasing operation on the nonvolatile register sector.

In some possible embodiments, the method further comprises:

and responding to the configuration operation of the JTAG debugging tool on the de-erasing protection signal and/or the de-writing protection signal, and configuring the corresponding signal.

In some possible embodiments, a central processing unit is disposed in the control chip, a cache unit is associated with the central processing unit, the cache unit allows the JTAG debug tool to write a cache address, and if the control chip is disconnected from the JTAG debug tool, the cache address is used to instruct the central processing unit to read information in the cache address from the main sector and store the information in the cache address into the cache unit, and the method further includes:

and if the JTAG debugging tool is determined to be disconnected after the cache address of the cache unit is changed and is re-connected with the control chip, the central processing unit is forbidden to read information from the main sector based on the cache address in the cache unit.

In some possible embodiments, after the prohibiting the central processor from reading information from the main sector based on the changed cache address, the method further comprises:

and in response to the reset operation of the cache address, allowing the central processor to read information from the main sector based on the cache address in the cache unit.

In some possible embodiments, the serial port debugger and the control chip communicate based on a serial debug interface, and the method further includes:

reading a check password from the nonvolatile register sector aiming at the serial port debugger;

if the verification password is matched with the reference password, allowing the serial port debugger to operate the main sector and the nonvolatile register sector;

and if the verification password is not matched with the reference password, prohibiting the serial port debugger from operating the main sector and the nonvolatile register sector.

The present application also provides a flash chip reading control apparatus, including: a memory and a controller;

the memory for storing a computer program;

the controller is coupled to the memory and configured to perform, based on the computer program:

configuring the operation authority of the JTAG debugging tool into a prohibition authority if the JTAG debugging signal of the JATG debugging tool and the protection level signal of the flash chip are both effective aiming at the JTAG debugging tool, wherein the prohibition authority is used for allowing the JTAG debugging tool to read the nonvolatile register sector and prohibiting the JTAG debugging tool from operating the main sector;

In some possible embodiments, if the operation authority of the JTAG debugging tool is a disable authority, the apparatus is further configured to:

In some possible embodiments, a permission parameter for indicating the operation permission of the JTAG debug tool is configured in the non-volatile register sector, and the deleting the information in the main sector and changing the disable permission to the enable permission are configured to:

In some possible embodiments, if the operation authority of the JTAG debug tool is an enable authority, the apparatus is further configured to:

In some possible embodiments, the changing the permission right to the prohibition right is configured to:

In some possible embodiments, the apparatus is further configured to:

In some possible embodiments, a central processing unit is disposed in the control chip, a cache unit is associated with the central processing unit, the cache unit allows the JTAG debug tool to write a cache address, and if the control chip is disconnected from the JTAG debug tool, the cache address is used to instruct the central processing unit to read information in the cache address from the main sector and store the information in the cache address into the cache unit, and the apparatus is further configured to:

In some possible embodiments, after said inhibiting said central processor from reading information from said main sector based on said changed cache address, said apparatus is further configured to:

In some possible embodiments, the serial port debugger and the control chip communicate based on a serial debug interface, and the apparatus is further configured to:

reading a check password from the nonvolatile register sector for the serial port debugger;

and if the check password is not matched with the reference password, prohibiting the serial port debugger from operating the main sector and the nonvolatile register sector.

In a third aspect, another embodiment of the present application further provides an electronic device, including at least one processor; and a memory communicatively coupled to the at least one processor; the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method for extracting video subtitles provided by the embodiment of the application.

In a fourth aspect, another embodiment of the present application further provides a computer storage medium, where the computer storage medium stores a computer program, and the computer program is used to enable a computer to execute the method for extracting video subtitles in the embodiments of the present application.

In the embodiment of the application, different protection levels are adopted to limit the access authority of the JTAG, the influence of electromagnetic interference on products is prevented by setting the parameters of the register, and the access authority of the serial debugging tool when accessing the chip is limited by a password proofreading mode.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments of the present application will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a device diagram of a flash chip read control method according to an embodiment of the present application;

fig. 2 is a device diagram of a flash chip read control method according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating a method for controlling flash chip read according to an embodiment of the present application, wherein JTAG rights are changed to permission rights;

fig. 4 is a flowchart of a flash chip read control method provided in an embodiment of the present application, where information in a main sector is deleted and a prohibition permission is changed into a permission;

fig. 5 is a device diagram of a flash chip read control method according to an embodiment of the present application;

FIG. 6 is a flowchart illustrating a method for changing the JTAG authority of a flash chip read control method provided by the present application into an allowed authority;

fig. 7 is a schematic diagram illustrating a CPU reading a program in a flash according to the flash chip reading control method provided in the embodiment of the present application;

fig. 8 is a schematic view of an electronic device of a flash chip reading control method according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions of the present application better understood by those of ordinary skill in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings.

It should be noted that the terms "first", "second", and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

The inventor researches and discovers that an embedded flash in a microcontroller chip is widely used as a program storage medium at present, along with the development cost of the chip is higher and higher, the safety of the chip program and the stability of the product are more and more important, after the product carrying the chip is produced, a third party manufacturer can read the program in the embedded flash through various debugging tools, repeatedly carve a printed circuit board of the product, burn the read program content into the circuit board and apply the program content to the product, the purposes of cloning the product and saving the development cost are achieved, and the behavior causes great threat to the development and production of the product.

The inventor researches and discovers that when a product carrying a chip is used in an electromagnetic interference environment, the risk of mistaken erasing and mistaken writing of a flash program embedded in the chip can cause the product to be incapable of being normally used, so that the use stability of the product is influenced.

In view of the above, the present application provides a flash chip reading control method, apparatus, electronic device and storage medium, which are used to solve the above problems. The inventive concept of the present application can be summarized as follows: aiming at the access of different debugging tools to the chip, the embedded flash program is subjected to different read protection, and the chip program is ensured not to be erased and rewritten accidentally by configuring parameters under the electromagnetic interference environment.

As shown in fig. 1, in a normal situation, the central processor 104 accesses the embedded flash memory controller 106 in the embedded flash top-level block diagram 105 through the Test access interface 102 and the serial debug interface 109 through an Advanced Microcontroller Bus Architecture (AMBA) Bus 111 and a Joint Test Action Group (JTAG) 101 through the Test access interface 102 and the serial debug tool 108 through the serial debug interface 109 and through the AMBA Bus 111, and the embedded flash memory controller 106 controls the embedded flash memory unit 107 to perform read, write, erase, and the like.

In the flash chip read control method provided by the application, for access modes of the JTAG and the serial debugging tool, read protection mechanisms are respectively designed to prevent a third party from reading a program embedded in the flash, and the read protection mechanisms and anti-electromagnetic interference of the JTAG and the serial debugging tool are respectively explained below.

First, JTAG

In the embodiment of the application, aiming at the access mode of the JTAG, two protection levels are provided, namely a prohibition authority and an allowance authority, wherein the prohibition authority is used for allowing a JTAG debugging tool to read the nonvolatile register sector and prohibiting the JTAG debugging tool from operating the main sector; the permission permissions are used to allow the JTAG debug tool to operate on the main Sector and the non-volatile register Sector (NVR Sector).

As shown in fig. 2, the diagram includes: the device comprises a register unit 201, a reading protection control unit 202, an erasing protection and writing protection control unit 203, a reading protection level decoding unit 204, a main control unit 205 and a controller and flash interface logic 206; the embedded flash memory unit 107 is provided with a main sector 207 and a nonvolatile register sector 208. After the chip is powered on, the embedded flash memory controller will read the value in the NVR Sector208 and send it to the read protection level decoding Unit 204 to obtain a protection level signal, and the protection level signal will notify the Central Processing Unit (CPU) 104 and the read protection control Unit 202.

When an external JTAG debugging tool is accessed, aiming at the JTAG debugging tool, if a JTAG debugging signal of the JATG debugging tool and a protection level signal of a flash chip are effective, configuring the operation authority of the JTAG debugging tool into a forbidden authority; and if at least one of the JTAG debugging signal and the protection level signal is invalid, configuring the operation authority of the JTAG debugging tool as permission authority.

In the flash chip read control method provided by the present application, JTAG can change its own authority through an APB bus in an AMBA bus, and the following describes in detail the overall process of JTAG changing its own authority.

In one embodiment, JTAG changes permissions to allow permissions as shown in FIG. 3:

in step 301: receiving first indication information which is sent by a JTAG debugging tool and used for changing the prohibition authority into the permission authority;

in step 302: in response to the first indication information, the information in the main sector is deleted and the prohibition authority is changed to the permission authority.

In the flash chip read control method provided by the embodiment of the application, the permission parameter for expressing the operation permission of the JTAG debugging tool is configured in the NVR (network video recorder) Sector.

As shown in fig. 4, deleting the information in the main sector and changing the prohibited right into the permitted right is mainly implemented as the following steps:

in step 401: if the de-erasing protection signal is valid, performing an erasing operation on the non-volatile register sector;

in step 402: if the erase operation is successfully performed and the de-write protection signal is determined to be valid, the permission parameter in the non-volatile register sector is configured as the permission.

In one embodiment, 0 is used to indicate the permission parameter and 1 is used to indicate the prohibition parameter. As shown in fig. 5, when JTAG performs a write operation through the APB bus, and configures the parameter of the read protection 1 to 0 enable register in the register unit as 1, the main control unit determines whether the read protection 1 to 0 enable signal and the erase protection signal sent by the register unit are valid; if the command is valid, the main control unit sends address data and an erasing command indicating the NVR Sector to the flash memory unit through the controller and the flash interface logic, and the flash memory unit executes an erasing operation on the NVR Sector according to the address data and the erasing command; after the erasing operation is completed, the main control unit generates an erasing completion signal.

After the erasing completion signal is generated, if the de-writing protection signal generated by the de-writing protection parameter register in the register unit is valid, the erasing protection and writing protection unit can generate a writing request; after receiving the write-in request, the main control unit generates a write command, write data and address data indicating an NVR (network video recorder) Sector; and the flash memory unit writes the indication permission parameter 0 into the NVR Sector according to the address data, the write command and the write data, and generates a write completion signal.

In one embodiment, after detecting the JTAG change authority, in order to prevent the program of the main sector from being acquired by a third party, the program of the main sector is erased, so as to achieve the purpose of protecting the program.

Therefore, after the write-in completion signal is detected, the main control unit logically sends address data and an erasing command indicating a main sector to the flash memory unit through the controller and the flash interface, and the flash memory unit executes the erasing operation on the main sector according to the address data and the erasing command; after the erasing operation is completed, the main control unit will generate a read protection 1 to 0 enable clear signal and a protection level change completion signal, at this time, the protection level becomes 0, and even though JTAG can read the contents of the main program area, the read data is invalid data after being erased.

In the embodiment of the present application, the flow of JTAG changing the permission to the permission is shown in fig. 6:

in step 601: receiving second indication information which is sent by a JTAG debugging tool and used for changing the permission authority into the prohibition authority;

in step 602: the permission right is changed to the prohibition right in response to the second indication information.

When the main control unit detects that a read protection 0-to-1 enabling signal and an erasure protection signal sent by a register are effective, an erasure protection and write protection unit sends an erasure request, the main control unit sends address data and an erasure command indicating NVR Sector to a flash memory unit through a controller and flash interface logic according to the erasure request, the flash memory unit executes an erasure operation on the NVR Sector according to the address data and the erasure command, the protection level 0 is erased, therefore, the protection level is changed into 1, and the authority of JTAG is changed into a forbidden authority.

The control chip is internally provided with a central processing unit which is associated with a cache unit, the cache unit allows a JTAG debugging tool to write a cache address, if the control chip is disconnected with the JTAG debugging tool, the cache address is used for indicating the central processing unit to read information in the cache address from a main sector and store the information in the cache address into the cache unit, but the mode has the following risk, as shown in figure 7, the CPU can read a program in a flash and place the program in a cache (cache), and the JTAG can access a cache space of 8KB through the CPU. Although only 8KB of data space can be read at a time, JTAG can modify the cache address of the cache. If the cache address of the cache is modified to 0-8k, then the JTAG connection is disconnected, so that the CPU reads the flash execution program normally, and at the moment, the cache can cache the data of 0-8k in the flash. And then JTAG can read out the data in the cache, modify the cache address of the cache into 8k-16k, and disconnect JTAG connection, wherein the cache can possibly cache the 8k-16k data in the flash. Repeating the above operations may read the entire program in the flash.

In view of the above problem, in the embodiment of the present application, if it is determined that the JTAG debug tool is disconnected after changing the cache address of the cache unit and is reconnected to the control chip, the central processing unit is prohibited from reading information from the main sector based on the cache address in the cache unit.

And if the reset operation on the cache address is detected, allowing the central processing unit to read information from the main sector based on the cache address in the cache unit.

Thus, JTAG can only obtain 8k of data in flash at most, thus basically eliminating the possibility of reading all programs in this way.

Anti-electromagnetic interference

The product equipment easily changes a certain bit of the register from 0 to 1 in an electromagnetic interference environment, which easily triggers the erasing or writing action of the flash, so that the erasing protection signal and the writing protection signal are set to prevent electromagnetic interference.

In the embodiment of the application, corresponding signals are configured in response to the configuration operation of the JTAG debugging tool on the de-erasing protection signal and/or the de-writing protection signal. Only when the erasing protection signal and/or the writing protection signal are/is effective, the main control unit can normally initiate erasing or writing actions, and the influence of electromagnetic interference on products is prevented.

Three, serial modulation interface

To serial port debugger, adopt the mode of password check to verify in this application:

after the chip is powered on, the main control unit reads a verification password from the NVR Sector and sends the verification password to the password verification unit in the figure 1; the password verification unit stores a reference password; if the verification password is matched with the reference password, allowing the serial port debugger to operate the main Sector and the NVR Sector; and if the verification password is not matched with the reference password, the serial port debugger is prohibited from operating the main Sector and the NVR Sector.

After the flash chip read control method according to the exemplary embodiment of the present application is introduced, next, an electronic device according to another exemplary embodiment of the present application is introduced.

As will be appreciated by one skilled in the art, aspects of the present application may be embodied as a system, method or program product. Accordingly, various aspects of the present application may be embodied in the form of: an entirely hardware embodiment, an entirely software embodiment (including firmware, microcode, etc.) or an embodiment combining hardware and software aspects that may all generally be referred to herein as a "circuit," module "or" system.

In some possible implementations, an electronic device according to the present application may include at least one processor, and at least one memory. The memory stores program codes, and when the program codes are executed by the processor, the processor executes the steps of the flash chip reading control method according to various exemplary embodiments of the present application described above in the present specification.

The electronic device 130 according to this embodiment of the present application is described below with reference to fig. 8. The electronic device 130 shown in fig. 8 is only an example, and should not bring any limitation to the functions and the scope of use of the embodiments of the present application.

As shown in fig. 8, the electronic device 130 is represented in the form of a general electronic device. The components of the electronic device 130 may include, but are not limited to: the at least one processor 131, the at least one memory 132, and a bus 133 that connects the various system components (including the memory 132 and the processor 131).

Bus 133 represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, a processor, or a local bus using any of a variety of bus architectures.

The memory 132 may include readable media in the form of volatile memory, such as Random Access Memory (RAM)1321 and/or cache memory 1322, and may further include Read Only Memory (ROM) 1323.

Memory 132 may also include a program/utility 1325 having a set (at least one) of program modules 1324, such program modules 1324 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which, or some combination thereof, may comprise an implementation of a network environment.

The electronic device 130 may also communicate with one or more external devices 134 (e.g., keyboard, pointing device, etc.), with one or more devices that enable a user to interact with the electronic device 130, and/or with any devices (e.g., router, modem, etc.) that enable the electronic device 130 to communicate with one or more other electronic devices. Such communication may occur via input/output (I/O) interfaces 135. Also, the electronic device 130 may communicate with one or more networks (e.g., a Local Area Network (LAN), a Wide Area Network (WAN), and/or a public network, such as the internet) via the network adapter 136. As shown, network adapter 136 communicates with other modules for electronic device 130 over bus 133. It should be understood that although not shown in the figures, other hardware and/or software modules may be used in conjunction with electronic device 130, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, among others.

In some possible embodiments, aspects of a method for controlling reading of a Flash chip provided by the present application may also be implemented in the form of a program product including program code for causing a computer device to perform the steps of a method for controlling reading of a Flash chip according to various exemplary embodiments of the present application described above in this specification when the program product is run on the computer device.

The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

The program product for read control of a Flash chip of an embodiment of the present application may employ a portable compact disc read only memory (CD-ROM) and include program code, and may be run on an electronic device. However, the program product of the present application is not limited thereto, and in this document, a readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A readable signal medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Program code for carrying out operations of the present application may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the consumer electronic device, partly on the consumer electronic device, as a stand-alone software package, partly on the consumer electronic device and partly on a remote electronic device, or entirely on the remote electronic device or server. In the case of remote electronic devices, the remote electronic devices may be connected to the consumer electronic devices through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to external electronic devices (e.g., through the internet using an internet service provider).

It should be noted that although several units or sub-units of the apparatus are mentioned in the above detailed description, such division is merely exemplary and not mandatory. Indeed, the features and functions of two or more units described above may be embodied in one unit, according to embodiments of the application. Conversely, the features and functions of one unit described above may be further divided into embodiments by a plurality of units.

Further, while the operations of the methods of the present application are depicted in the drawings in a particular order, this does not require or imply that these operations must be performed in this particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A read control method of a flash chip, wherein the flash is an embedded chip of a control chip, and the flash chip comprises a main sector and a nonvolatile register sector, and the method comprises the following steps:

if at least one of the JTAG debugging signal and the protection level signal is invalid, configuring the operation authority of the JTAG debugging tool as an permission authority, wherein the permission authority is used for allowing the JTAG debugging tool to operate the main sector and the nonvolatile register sector;

the control chip is internally provided with a central processing unit which is associated with a cache unit, the cache unit allows the JTAG debugging tool to write in a cache address, if the control chip is disconnected with the JTAG debugging tool, the cache address is used for indicating the central processing unit to read information in the cache address from the main sector and store the information in the cache address into the cache unit, and the method further comprises the following steps:

2. The method of claim 1, wherein if the operation authority of the JTAG debug tool is a disable authority, the method further comprises:

3. The method of claim 2, wherein a permission parameter for indicating the operation permission of the JTAG debug tool is configured in the non-volatile register sector, and wherein the deleting the information in the master sector and changing the disable permission to the enable permission comprises:

if the erase operation is successfully performed and a de-write protection signal is determined to be valid, the permission parameter in the non-volatile register sector is configured as the permission.

4. The method of claim 1, wherein if the operating permissions of the JTAG debug tool are permission permissions, the method further comprises:

5. The method of claim 4, wherein the changing the permission to the prohibition comprises:

6. The method according to any one of claims 1-5, further comprising:

7. The method according to any one of claims 1 to 5, wherein a serial port debugger and the control chip communicate based on a serial debug interface, the method further comprising:

8. A read control device of flash chip, the flash is the embedded chip of the control chip, the said flash chip includes main sector and nonvolatile register sector, characterized by that, including: a memory and a controller;

the memory for storing a computer program;

the method of any one of claims 1-7.

9. A computer storage medium, characterized in that it stores a computer program for causing a computer to perform the method of any of claims 1-7.