CN112670186A - Chip packaging structure and preparation method thereof - Google Patents
Chip packaging structure and preparation method thereof Download PDFInfo
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- CN112670186A CN112670186A CN202011532156.6A CN202011532156A CN112670186A CN 112670186 A CN112670186 A CN 112670186A CN 202011532156 A CN202011532156 A CN 202011532156A CN 112670186 A CN112670186 A CN 112670186A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 16
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 245
- 229910052751 metal Inorganic materials 0.000 claims abstract description 245
- 238000002161 passivation Methods 0.000 claims abstract description 190
- 238000000034 method Methods 0.000 claims abstract description 34
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 229910000679 solder Inorganic materials 0.000 claims description 11
- 238000000227 grinding Methods 0.000 claims description 3
- 239000011295 pitch Substances 0.000 description 24
- 239000000463 material Substances 0.000 description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 239000003292 glue Substances 0.000 description 6
- 229920000642 polymer Polymers 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
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Abstract
The invention provides a chip packaging structure and a preparation method thereof, wherein the method comprises the following steps: providing a bearing sheet; sequentially forming at least one first passivation layer and at least one second passivation layer on the first surface of the bearing sheet along the thickness direction of the bearing sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals; patterning the first passivation layer to form a first via hole, and forming metal layers in the first via hole, wherein the thickness of each metal layer is larger than that of the corresponding first passivation layer; removing the metal higher than the first passivation layer to enable the remaining metal layer to be flush with the corresponding first passivation layer, and obtaining metal wiring; patterning the second passivation layer to form a second through hole, wherein the metal wirings are electrically connected through the second through hole; and forming a metal bump on the second passivation layer on the topmost layer, wherein the metal bump is electrically connected with each metal wiring through the second through hole. The invention enables the surface of the metal wiring and the corresponding first passivation layer to be flat, improves the precision of the first passivation layer, and can ensure that the minimum line width of the metal wiring is 1 mu m.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a chip packaging structure and a preparation method thereof.
Background
With the diversification of electronic products, devices with various sizes are required, and the preparation of devices such as filters, transformers, capacitors, inductors and the like with micron-sized line widths is limited by the height of the metal bumps, so that the surface of the photoresist covered on the metal bumps is not flat, and the metal line width must be larger than 5 microns to meet the preparation requirement. When the metal line width is less than 5 μm, the metal lines are easily deformed, shorted, broken, and the like, thereby causing the performance failure of the device.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art and provides a chip packaging structure and a preparation method thereof.
In one aspect of the present invention, a method for manufacturing a chip package structure is provided, the method including:
providing a bearing sheet;
sequentially forming at least one first passivation layer and at least one second passivation layer on a first surface of the carrier sheet along the thickness direction of the carrier sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals;
patterning the first passivation layer to form a first via hole, and forming metal layers in the first via hole, wherein the thickness of each metal layer is larger than that of the first passivation layer of the corresponding layer;
removing the metal higher than the first passivation layer to make the remaining metal layer flush with the first passivation layer corresponding to the metal layer, thereby obtaining metal wiring of each layer;
patterning the second passivation layer to form a second through hole, wherein the metal wires of all layers are electrically connected through the second through hole;
and forming a metal bump on the second passivation layer on the topmost layer, wherein the metal bump is electrically connected with each layer of metal wiring through the second via hole so as to prepare the packaging structure.
In some optional embodiments, the removing the metal above the first passivation layer comprises:
and removing the metal higher than the first passivation layer through a grinding process.
In some optional embodiments, the metal wiring has a line width of 1 μm or more and/or a line pitch range of 1 μm or more; and/or the presence of a gas in the gas,
the thickness of the metal wiring is 1 μm or more.
In some alternative embodiments, the metal wiring has a line width and/or a line pitch ranging from 1 μm to 5 μm; and/or the presence of a gas in the gas,
the thickness of the metal wiring is in the range of 1 to 2 μm.
In some optional embodiments, the method further comprises:
forming a third passivation layer on the metal bump, and patterning the third passivation layer to expose a portion of the metal bump;
and forming a solder ball on the exposed metal bump.
In another aspect of the present invention, a package structure of a chip is provided, the package structure including:
a carrier sheet;
the carrier sheet comprises at least one first passivation layer and at least one second passivation layer, wherein the second passivation layer and the first passivation layer are alternately arranged on a first surface of the carrier sheet along the thickness direction of the carrier sheet at intervals;
the first passivation layer is provided with a first through hole, and the second passivation layer is provided with a second through hole;
at least one layer of metal wiring, wherein the metal wiring is arranged in the corresponding first via hole, each layer of metal wiring is flush with the corresponding first passivation layer, and the metal wirings are electrically connected through the second via holes;
and the metal bump is arranged on the second passivation layer at the topmost layer and is electrically connected with each layer of metal wiring through the second via hole.
In some optional embodiments, the metal wiring has a line width of 1 μm or more and/or a line pitch of 1 μm or more.
In some optional embodiments, the metal wiring has a thickness of 1 μm or more.
In some alternative embodiments, the metal wiring has a line width and/or a line pitch ranging from 1 μm to 5 μm; and/or the presence of a gas in the gas,
the thickness of the metal wiring is in the range of 1 to 2 μm.
In some optional embodiments, the package structure further comprises:
a third passivation layer disposed on the metal bump, the third passivation layer having a third via;
and the solder ball is arranged in the third through hole and is electrically connected with the metal bump.
The invention provides a chip packaging structure and a preparation method thereof, wherein the method comprises the following steps: providing a bearing sheet; sequentially forming at least one first passivation layer and at least one second passivation layer on the first surface of the bearing sheet along the thickness direction of the bearing sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals; patterning the first passivation layer to form first via holes, and forming metal layers in the first via holes, wherein the thickness of each metal layer is larger than that of the first passivation layer of the corresponding layer; removing the metal higher than the first passivation layer to enable the remaining metal layer to be flush with the corresponding first passivation layer, and obtaining metal wiring of each layer; patterning the second passivation layer to form a second through hole, wherein the metal wirings are electrically connected through the second through hole; and forming a metal bump on the second passivation layer on the topmost layer, wherein the metal bump is electrically connected with each layer of metal wiring through the second through hole so as to prepare the packaging structure. The invention can flatten the surface of each layer of metal wiring and the corresponding first passivation layer, improve the precision of the first passivation layer, reduce the requirement on the line width of the metal wiring, and the minimum line width of the metal wiring can reach 1 μm.
Drawings
Fig. 1 is a flowchart illustrating a method for manufacturing a chip package structure according to an embodiment of the invention;
fig. 2 to 12 are schematic flow charts illustrating a method for manufacturing a chip package structure according to another embodiment of the invention.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
In one aspect of the present invention, as shown in fig. 1, a method S100 for manufacturing a chip package structure is provided, where the method S100 includes:
and S110, providing a bearing sheet.
Illustratively, in conjunction with fig. 2, a carrier sheet 110 is provided, and the carrier sheet 110 includes a first surface 111 and a second surface 112 oppositely disposed along a thickness direction thereof. In this step, the carrier sheet 110 may be a flat plate made of materials such as silicon, glass, metal, and organic substrate, and those skilled in the art may select carrier sheets made of other materials according to actual needs.
S120, sequentially forming at least one first passivation layer and at least one second passivation layer on the first surface of the bearing sheet along the thickness direction of the bearing sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals.
For example, in this step, a first passivation layer may be formed on the first surface of the carrier sheet along the thickness direction thereof, and then a second passivation layer may be formed on the first passivation layer after the metal wiring is formed on the first passivation layer. Alternatively, after forming the first passivation layer, the first metal wiring and the first passivation layer, a second passivation layer may be formed on the first passivation layer, a second metal wiring may be formed on the second passivation layer, and a second passivation layer may be formed on the second passivation layer. That is to say, the second passivation layer and the first passivation layer are alternately disposed at an interval, and the first passivation layer and the second passivation layer may both have only one layer, or may both have two layers, three layers, or other multiple layers. Hereinafter, a description will be given in detail with reference to the accompanying drawings by taking an example in which the first passivation layer and the second passivation layer have two layers.
As shown in fig. 2, a first passivation layer 121 is formed on the first surface 111 of the carrier sheet 110. In this step, the process of forming the first passivation layer may be deposition, sputtering, or other processes, which is not limited in this embodiment. The first passivation layer may be made of silicon dioxide, silicon nitride, polymer glue, or other materials, and those skilled in the art may select the first passivation layer according to actual needs, which is not limited in this embodiment. It should be noted that the specific thickness of the first passivation layer is not limited in this embodiment, and those skilled in the art can select the thickness according to actual needs.
S130, patterning the first passivation layer to form a first via hole, and forming a metal layer in the first via hole, wherein the thickness of each metal layer is larger than that of the first passivation layer of the corresponding layer.
For example, in this step, as shown in fig. 2, the first passivation layer 121 is patterned to form the first via hole 121a, which may specifically be as follows: first, a patterned first mask layer is formed on the first passivation layer 121, and then, the first passivation layer 121 is etched at a suitable position by using the first mask layer as a mask, so as to form a first via hole 121 a. The material of the first mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the first passivation layer may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, a person skilled in the art may also select other ways to pattern the first passivation layer to form the first via, which is not limited by the embodiment.
For example, in this step, as shown in fig. 3, a metal layer 131 may be formed in the first via hole 121a by using electroplating, electroless plating, sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the like, where the thickness of the metal layer 131 is greater than that of the first passivation layer 121 of the corresponding layer. Of course, a person skilled in the art may select other ways to form the metal layer in the first via, which is not limited by the embodiment.
S140, removing the metal higher than the first passivation layer to enable the remaining metal layer to be flush with the first passivation layer corresponding to the metal layer, and obtaining metal wiring of each layer.
Preferably, the removing of the metals higher than the first passivation layer includes:
and removing the metal higher than the first passivation layer through a grinding process.
Illustratively, in this step, as shown in fig. 4, the metal above the first passivation layer 121 may be removed by a polishing process such as Chemical Mechanical Polishing (CMP), so that the remaining metal layer is flush with the corresponding first passivation layer 121, and the metal wiring 131a is obtained. Of course, a person skilled in the art may also remove the metal above the first passivation layer by other ways, which is not limited by the embodiment.
In this step, the metal wiring may have only one layer, or may have multiple layers, such as two layers, three layers, and the like, and those skilled in the art may select the metal wiring according to actual needs, which is not limited in this embodiment.
In this step, the metal wiring of each layer is flush with the corresponding first passivation layer, so that the surface of the metal wiring and the corresponding first passivation layer is flat, the precision of the first passivation layer is improved, the requirement on the line width of the metal wiring is reduced, and the minimum line width of the metal wiring can reach 1 μm.
Illustratively, as shown in fig. 5, a second passivation layer 141 is formed on the first passivation layer 121. In this step, the process of forming the second passivation layer may be deposition, sputtering, or other processes, which is not limited in this embodiment. The second passivation layer may be made of silicon dioxide, silicon nitride, polymer glue, or other materials, and those skilled in the art may select the second passivation layer according to actual needs, which is not limited in this embodiment. It should be noted that the specific thickness of the second passivation layer is not limited in this embodiment, and those skilled in the art can select the thickness according to actual needs.
S150, patterning the second passivation layer to form a second through hole, wherein the metal wires of all layers are electrically connected through the second through hole.
For example, in this step, as shown in fig. 5, the second passivation layer 141 is patterned to form the second via hole 141a, which may specifically be implemented in the following manner: first, a patterned second mask layer is formed on the second passivation layer 141, and then, the second passivation layer 141 is etched at a suitable position by using the second mask layer as a mask, so as to form a second via hole 141 a. The material of the second mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the second passivation layer may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, a person skilled in the art may also select other ways to pattern the second passivation layer to form the second via, which is not limited by the embodiment.
For example, as shown in fig. 6, a first passivation layer 122 may be further formed on the second passivation layer 141, and the first passivation layer 122 may be patterned to form a first via hole 122 a. Thereafter, as shown in fig. 7, a metal layer 132 is formed in the second via hole 141a and the first via hole 122a, and the thickness of the metal layer 132 is greater than that of the first passivation layer 122 of the corresponding layer. Then, as shown in fig. 8, the metal above the first passivation layer 122 is removed, so that the remaining metal layer is flush with the corresponding first passivation layer 122, and a metal wire 132a is obtained, wherein the metal wire 132a is electrically connected to the metal wire 131a through the second via 141 a. Thereafter, as shown in fig. 9, a second passivation layer 142 is formed on the first passivation layer 122, and the second passivation layer 142 is patterned to form second vias 142 a. In this step, the specific steps of forming the first passivation layer 122, the first via 122a, the metal layer 132, the metal wire 132a, the second passivation layer 142 and the second via 142a may refer to the above descriptions, and are not repeated herein.
And S160, forming a metal bump on the second passivation layer at the topmost layer, wherein the metal bump is electrically connected with each layer of metal wiring through the second via hole so as to prepare the packaging structure.
Illustratively, in this step, as shown in fig. 10, a metal bump 150 may be formed on the second passivation layer 142 by sputtering, electroplating, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and the metal bump 150 is electrically connected to the metal wire 132a through the second via 142a and electrically connected to the metal wire 131a through the second via 141 a. Of course, a person skilled in the art may also form the metal bump on the second passivation layer by other methods, which is not limited by the embodiment. The line width and the line distance of the metal bump 150 may be 5 μm to 300 μm, respectively, or may be set according to actual needs, which is not limited in this embodiment. The height of the metal bump 150 may be in a range from 5 μm to 20 μm, or may be set according to actual needs, which is not limited in this embodiment.
The embodiment can enable the surfaces of each layer of metal wiring and the corresponding first passivation layer to be flat, improve the precision of the first passivation layer, reduce the requirements on the line width of the metal wiring, and enable the line width of the metal wiring to be as small as 1 mu m.
Preferably, the line width of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 10, the line widths of the metal wiring 131a and the metal wiring 132a may each be 1 μm or more. For example, the line width of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the line width of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the line width of the metal wiring according to actual needs, which is not limited in this embodiment.
Preferably, the pitch of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 10, the pitches of the metal wiring 131a and the metal wiring 132a may be each 1 μm or more. For example, the pitch of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the pitch of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the pitch of the metal wirings according to actual needs, and the embodiment does not limit this.
Preferably, the thickness of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 10, the thicknesses of the metal wiring 131a and the metal wiring 132a may each be 1 μm or more. For example, the thickness of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the thickness of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the thickness of the metal wiring according to actual needs, and the embodiment is not limited thereto.
Preferably, the metal wiring has a line width in a range of 1 to 5 μm.
Illustratively, as shown in fig. 10, the line widths of the metal wiring 131a and the metal wiring 132a may each be in a range of 1 μm to 5 μm. For example, the line width of the metal wiring 131a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like, and the line width of the metal wiring 132a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like. Of course, a person skilled in the art may also set a specific value of the line width of the metal wiring according to actual needs, which is not limited in this embodiment.
Preferably, the pitch of the metal wiring is in a range of 1 to 5 μm.
Illustratively, as shown in fig. 10, the pitch of the metal wiring 131a and the metal wiring 132a may each be in a range of 1 μm to 5 μm. For example, the pitch of the metal wiring 131a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like, and the pitch of the metal wiring 132a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like. Of course, a person skilled in the art may also set a specific value of the pitch of the metal wirings according to actual needs, and the embodiment does not limit this.
Preferably, the metal wiring has a thickness in a range of 1 to 2 μm.
Illustratively, as shown in fig. 10, the thickness of the metal wiring 131a and the metal wiring 132a may each range from 1 μm to 2 μm. For example, the thickness of the metal wiring 131a may be 1 μm, 2 μm, 1.5 μm, or the like, and the thickness of the metal wiring 132a may be 1 μm, 2 μm, 1.5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the thickness of the metal wiring according to actual needs, and the embodiment is not limited thereto.
Preferably, the method S100 further includes:
and forming a third passivation layer on the metal bump.
Illustratively, in this step, a third passivation layer 160 is formed on the metal bump 150, as shown in fig. 11. In this step, the process of forming the third passivation layer may be deposition, sputtering, or other processes, which is not limited in this embodiment. The third passivation layer may be made of polymer glue, silicon dioxide, silicon nitride, or other materials, and those skilled in the art may select the third passivation layer according to actual needs, which is not limited in this embodiment. The thickness of the third passivation layer may be in a range of 5 μm to 30 μm, for example, the thickness of the third passivation layer may be 5 μm, 30 μm, 10 μm, 15 μm, 20 μm, or the like. Of course, a person skilled in the art may also set the specific thickness of the third passivation layer according to actual needs, which is not limited in this embodiment.
Patterning the third passivation layer to expose a portion of the metal bump.
For example, in this step, as shown in fig. 11, the third passivation layer 160 is patterned to expose a portion of the metal bump 150, which may be implemented by: a patterned third mask layer is first formed on the third passivation layer 160, and then the third passivation layer 160 is etched at a suitable position by using the third mask layer as a mask, so as to expose a portion of the metal bump 150. The material of the third mask layer may be a photoresist, or other materials may be selected according to actual needs, which is not limited in this embodiment. The process for etching the third passivation layer may be a dry etching process, or may be another process, which is not limited in this embodiment. Of course, a person skilled in the art may also select other ways to pattern the third passivation layer to expose a portion of the metal bump, which is not limited in this embodiment.
And forming a solder ball on the exposed metal bump.
Illustratively, as shown in fig. 12, in this step, a solder ball 170 may be formed on the exposed metal bump 150 by ball-planting, printing, electroplating, electroless plating, or the like. Of course, a person skilled in the art may also form a solder ball on the exposed metal bump by other processes, which is not limited by the embodiment.
In the embodiment, the solder balls are formed on the exposed metal bumps, so that the subsequent use of the packaging structure can be facilitated.
In another aspect of the present invention, a chip package structure is provided, which includes a carrier, at least one first passivation layer, at least one second passivation layer, at least one metal wire, and a metal bump. The package structure may be formed by the preparation method described above, and reference may be made to the related description, which is not described herein again.
Exemplarily, as shown in fig. 12, a chip packaging structure 100 may include a carrier sheet 110, a first passivation layer 121, a second passivation layer 141, a first passivation layer 122, a second passivation layer 142, a metal wire 131a, a metal wire 132a, and a metal bump 150. That is, the package structure 100 includes two first passivation layers, two second passivation layers, and two metal wirings. Wherein, the second passivation layer and the first passivation layer are alternately arranged at intervals on the first surface 111 of the carrier sheet 110 along the thickness direction thereof. The first passivation layer 121 is provided with a first via hole 121a, and the second passivation layer 141 is provided with a second via hole 141 a. The metal wire 131a is disposed in the corresponding first via hole 121a, and the metal wire 131a is flush with its corresponding first passivation layer 121. Similarly, the first passivation layer 122 is provided with a first via 122a, and the second passivation layer 142 is provided with a second via 142 a. The metal wire 132a is disposed in the corresponding first via 122a, the metal wire 132a is flush with the corresponding first passivation layer 122, and the metal wire 132a and the metal wire 131a are electrically connected through the second via 141 a. The metal bump 150 is disposed on the second passivation layer 142 of the uppermost layer, and the metal bump 150 is electrically connected to the metal wire 132a through the second via 142a and electrically connected to the metal wire 131a through the second via 141 a. The line width and the line distance of the metal bump 150 may be 5 μm to 300 μm, respectively, or may be set according to actual needs, which is not limited in this embodiment. The height of the metal bump 150 may be in a range from 5 μm to 20 μm, or may be set according to actual needs, which is not limited in this embodiment.
It should be noted that, in this embodiment, each of the first passivation layer, the second passivation layer, and the metal wiring may have only one layer, or may have two or three layers, and a person skilled in the art may select the passivation layer according to actual needs, which is not limited in this embodiment.
It should be noted that the specific material of each structure is not limited in this embodiment, and those skilled in the art can select the material according to actual needs. For example, the carrier sheet may be made of silicon, glass, metal, an organic substrate, or other materials, the first passivation layer may be made of silicon dioxide, silicon nitride, polymer glue, or other materials, and the second passivation layer may be made of silicon dioxide, silicon nitride, polymer glue, or other materials, which is not limited in this embodiment.
The packaging structure of the chip of the embodiment can enable the surfaces of the metal wiring lines and the corresponding first passivation layer to be flat, improve the precision of the first passivation layer, reduce the requirements on the line width of the metal wiring lines, and enable the line width of the metal wiring lines to be as small as 1 mu m.
Preferably, the line width of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 12, the line widths of the metal wiring 131a and the metal wiring 132a may each be 1 μm or more. For example, the line width of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the line width of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the line width of the metal wiring according to actual needs, which is not limited in this embodiment.
Preferably, the pitch of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 12, the pitches of the metal wiring 131a and the metal wiring 132a may be each 1 μm or more. For example, the pitch of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the pitch of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the pitch of the metal wirings according to actual needs, and the embodiment does not limit this.
Preferably, the thickness of the metal wiring is 1 μm or more.
Illustratively, as shown in fig. 12, the thicknesses of the metal wiring 131a and the metal wiring 132a may each be 1 μm or more. For example, the thickness of the metal wiring 131a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like, and the thickness of the metal wiring 132a may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the thickness of the metal wiring according to actual needs, and the embodiment is not limited thereto.
Preferably, the line width of the metal wiring is in the range of 1 μm to 5 μm.
Illustratively, as shown in fig. 12, the line widths of the metal wiring 131a and the metal wiring 132a may each be in a range of 1 μm to 5 μm. For example, the line width of the metal wiring 131a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like, and the line width of the metal wiring 132a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like. Of course, a person skilled in the art may also set a specific value of the line width of the metal wiring according to actual needs, which is not limited in this embodiment.
Preferably, the pitch of the metal wiring is in the range of 1 μm to 5 μm.
Illustratively, as shown in fig. 12, the pitch of the metal wiring 131a and the metal wiring 132a may each be in a range of 1 μm to 5 μm. For example, the pitch of the metal wiring 131a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like, and the pitch of the metal wiring 132a may be 1 μm, 5 μm, 2 μm, 3 μm, 4 μm, or the like. Of course, a person skilled in the art may also set a specific value of the pitch of the metal wirings according to actual needs, and the embodiment does not limit this.
Preferably, the thickness of the metal wiring is in the range of 1 μm to 2 μm.
Illustratively, as shown in fig. 12, the thickness of the metal wiring 131a and the metal wiring 132a may range from 1 μm to 2 μm. For example, the thickness of the metal wiring 131a may be 1 μm, 2 μm, 1.5 μm, or the like, and the thickness of the metal wiring 132a may be 1 μm, 2 μm, 1.5 μm, or the like. Of course, a person skilled in the art may also set a specific value of the thickness of the metal wiring according to actual needs, and the embodiment is not limited thereto.
Preferably, as shown in fig. 12, the package structure 100 further includes a third passivation layer 160 and a solder ball 170. A third passivation layer 160 is disposed on the metal bump 150, and the third passivation layer 160 is provided with a third via hole 160 a. The thickness of the third passivation layer may range from 5 μm to 30 μm, for example, the thickness of the third passivation layer 160 may be 5 μm, 30 μm, 10 μm, 15 μm, 20 μm, and the like. Of course, a person skilled in the art may also set the specific thickness of the third passivation layer according to actual needs, which is not limited in this embodiment. The solder ball 170 is disposed in the third via 160a and electrically connected to the metal bump 150.
It should be noted that the specific material of each structure is not limited in this embodiment, and those skilled in the art can select the material according to actual needs. For example, the third passivation layer may be made of silicon dioxide, silicon nitride, or other materials, or may be made of polymer glue such as Polyimide (PI), or other materials, which is not limited in this embodiment.
The third passivation layer and the solder balls are arranged, so that the subsequent use of the packaging structure can be facilitated.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (10)
1. A preparation method of a chip packaging structure is characterized by comprising the following steps:
providing a bearing sheet;
sequentially forming at least one first passivation layer and at least one second passivation layer on a first surface of the carrier sheet along the thickness direction of the carrier sheet, wherein the second passivation layers and the first passivation layers are alternately arranged at intervals;
patterning the first passivation layer to form a first via hole, and forming metal layers in the first via hole, wherein the thickness of each metal layer is larger than that of the first passivation layer of the corresponding layer;
removing the metal higher than the first passivation layer to make the remaining metal layer flush with the first passivation layer corresponding to the metal layer, thereby obtaining metal wiring of each layer;
patterning the second passivation layer to form a second through hole, wherein the metal wires of all layers are electrically connected through the second through hole;
and forming a metal bump on the second passivation layer on the topmost layer, wherein the metal bump is electrically connected with each layer of metal wiring through the second via hole so as to prepare the packaging structure.
2. The method of claim 1, wherein the removing metal above the first passivation layer comprises:
and removing the metal higher than the first passivation layer through a grinding process.
3. The method of claim 1,
the line width of the metal wiring is more than or equal to 1 mu m and/or the line distance range is more than or equal to 1 mu m; and/or the presence of a gas in the gas,
the thickness of the metal wiring is 1 μm or more.
4. The method of claim 3,
the range of the line width and/or the line distance of the metal wiring is 1-5 mu m; and/or the presence of a gas in the gas,
the thickness of the metal wiring is in the range of 1 to 2 μm.
5. The method according to any one of claims 1 to 4, further comprising:
forming a third passivation layer on the metal bump, and patterning the third passivation layer to expose a portion of the metal bump;
and forming a solder ball on the exposed metal bump.
6. A chip package structure, comprising:
a carrier sheet;
the carrier sheet comprises at least one first passivation layer and at least one second passivation layer, wherein the second passivation layer and the first passivation layer are alternately arranged on a first surface of the carrier sheet along the thickness direction of the carrier sheet at intervals;
the first passivation layer is provided with a first through hole, and the second passivation layer is provided with a second through hole;
at least one layer of metal wiring, wherein the metal wiring is arranged in the corresponding first via hole, each layer of metal wiring is flush with the corresponding first passivation layer, and the metal wirings are electrically connected through the second via holes;
and the metal bump is arranged on the second passivation layer at the topmost layer and is electrically connected with each layer of metal wiring through the second via hole.
7. The package structure according to claim 6, wherein the metal wiring has a line width of 1 μm or more and/or a line pitch of 1 μm or more.
8. The package structure according to claim 7, wherein a thickness of the metal wiring is 1 μm or more.
9. The package structure according to claim 8, wherein the metal wiring has a line width and/or a line pitch ranging from 1 μm to 5 μm; and/or the presence of a gas in the gas,
the thickness of the metal wiring is in the range of 1 to 2 μm.
10. The package structure of any one of claims 6 to 9, further comprising:
a third passivation layer disposed on the metal bump, the third passivation layer having a third via;
and the solder ball is arranged in the third through hole and is electrically connected with the metal bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011532156.6A CN112670186A (en) | 2020-12-22 | 2020-12-22 | Chip packaging structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011532156.6A CN112670186A (en) | 2020-12-22 | 2020-12-22 | Chip packaging structure and preparation method thereof |
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| CN112670186A true CN112670186A (en) | 2021-04-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113314324A (en) * | 2021-05-21 | 2021-08-27 | 厦门通富微电子有限公司 | Preparation method of transformer packaging structure and packaging structure |
| CN114121793A (en) * | 2021-11-26 | 2022-03-01 | 长电集成电路(绍兴)有限公司 | Multilayer metal wiring layer, preparation method thereof and packaging structure |
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| JP2007103736A (en) * | 2005-10-05 | 2007-04-19 | Tdk Corp | Electronic component, manufacturing method therefor, and semiconductor device |
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| CN106409803A (en) * | 2015-07-27 | 2017-02-15 | 华亚科技股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
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| US6184121B1 (en) * | 1997-07-10 | 2001-02-06 | International Business Machines Corporation | Chip interconnect wiring structure with low dielectric constant insulator and methods for fabricating the same |
| JP2007103736A (en) * | 2005-10-05 | 2007-04-19 | Tdk Corp | Electronic component, manufacturing method therefor, and semiconductor device |
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| CN113314324A (en) * | 2021-05-21 | 2021-08-27 | 厦门通富微电子有限公司 | Preparation method of transformer packaging structure and packaging structure |
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Application publication date: 20210416 |