CN112596798A - Chip starting control circuit and control method - Google Patents
Chip starting control circuit and control method Download PDFInfo
- Publication number
- CN112596798A CN112596798A CN202011559806.6A CN202011559806A CN112596798A CN 112596798 A CN112596798 A CN 112596798A CN 202011559806 A CN202011559806 A CN 202011559806A CN 112596798 A CN112596798 A CN 112596798A
- Authority
- CN
- China
- Prior art keywords
- chip
- loading
- register
- starting
- configuration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 230000002159 abnormal effect Effects 0.000 claims description 23
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Chemical compound BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention discloses a chip start control circuit and a control method, wherein a timer is arranged for timing when a chip loads chip configuration information to a configuration register by using a loading module. If the chip does not receive the loading completion signal of the configuration register within the preset time, allowing the chip to restart; and if the restart times are more than the preset times, allowing the chip to skip the receiving step of the loading completion signal and directly start. The invention utilizes a timer to monitor the chip starting process, allows the chip to be restarted for multiple times, and can skip the step of receiving a loading completion signal to directly start the chip under the condition that the number of times of restarting is exceeded.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a chip starting control circuit and a control method.
Background
The starting process of the chip is a critical part in chip design, and a normal chip must ensure safe and reliable normal starting. However, during the starting process of the chip, unexpected situations such as error crash and the like are inevitable. In the prior art, a mode of restarting for multiple times is utilized to deal with the situation of chip starting failure, and if the chip can not be started finally, the chip is judged to generate errors and the power supply is cut off. Although this method can improve the probability of normal startup of the chip, it cannot provide a means for solving the BUG.
Disclosure of Invention
In order to solve the problems, the invention provides a chip starting control circuit and a control method, which enable a chip to be directly started under the condition of abnormal starting and then DEBUG is carried out, so that the problem of the BUG in the starting process of the chip can be better solved. The specific technical scheme of the invention is as follows:
a chip start control circuit comprises a timer and a processor, wherein the timer is connected with the processor and used for calculating the start time of a chip and generating an interrupt signal according to the start time; the processor performs a chip restart or an abnormal start in a start failure according to the received start time and the interrupt signal. The circuit provided by the invention monitors the chip starting process by using the timer, allows the chip to be restarted for multiple times, and can interrupt the starting process and skip the step of receiving the loading completion signal by using the interrupt program to directly start the chip under the condition that the restarting times are exceeded.
The circuit further comprises a power management module, a global reset register, an AND gate, a read-write memory, a read-only memory, a programmable memory, a loading module and a configuration register, wherein the power management module is connected with the AND gate and used for supplying power to each module in the circuit; the global reset register is connected with the AND gate and is used for triggering reset; the input end of the AND gate is connected with the power management module and the global reset register, and the output end of the AND gate is connected with the processor and the loading module and used for the AND logic operation of the power management module and the global reset register; the read-write memory is connected with the processor and used for recording the starting abnormal information; the read-only memory is connected with the processor and used for setting the repeated starting times; the programmable memory is connected with the loading module and used for storing the configuration information of the chip; the loading module is connected with the AND gate, the programmable memory and the configuration register and is used for loading the chip configuration information into the configuration register; and the configuration register is connected with the loading module and used for applying the chip configuration information to the corresponding circuit and generating a loading completion signal.
A chip start-up control method, the method comprising: s1, after the chip is powered on, the power management unit is used for judging whether the voltage is normal, and if the voltage is normal, the power-on reset signal is cancelled; s2, starting the chip, loading the chip configuration information into the configuration register by using the loading module, and starting timing by using the timer; s3, the chip waits for the register to return a loading completion signal, if the loading completion signal is received within a preset time, the chip is indicated to be started successfully, otherwise the chip is failed to start, if the chip fails to start, the starting process is interrupted, the starting failure times are recorded and compared with the preset times, if the former is less than or equal to the latter, the operation returns to S1, and if the former is greater than the latter, the operation enters S4; s4, the chip skips the receiving step of the loading completion signal and directly starts. The method of the invention uses a timer to monitor the chip starting process, allows the chip to be restarted for a plurality of times, and can skip the step of receiving the loading completion signal when the number of times of restarting is exceeded, so that the chip can be directly started.
Further, in step S1, when the voltage is normal, the chip waits for a set time before deactivating the power-on reset signal. And after a period of time, the voltage can be stabilized, thereby being beneficial to starting the chip.
Further, in step S2, after the loading module loads the chip configuration information into the configuration register, the configuration register turns on a configuration enable signal of the chip, so that the chip configuration information is applied to the corresponding circuit, and then the configuration register generates a loading completion signal.
Further, in step S2, the timer starts timing when the loading module loads the chip configuration information into the configuration register, and ends timing when the configuration register applies the chip configuration information to the corresponding circuit. And a timer is used for timing, so that whether the starting process of the chip is overtime or not can be judged.
Further, in the step S3, before the chip returns to the step S1, the following operations are performed: the chip triggers a reset using a global reset register.
Further, in step S4, the process of the chip skipping the receiving step of the load complete signal is: the chip uses the interrupt program to bypass the receiving of the loading completion signal to complete the starting in the abnormal state, and records the abnormal information in the read-write memory. The loading completion signal is bypassed, so that the chip can still be started under the condition of abnormal starting, and convenience is provided for subsequent DEBUG.
Drawings
Fig. 1 is a circuit diagram illustrating a chip start control circuit according to an embodiment of the present invention.
Fig. 2 is a diagram illustrating a chip start control method according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention. It should be understood that the following specific examples are illustrative only and are not intended to limit the invention.
In the following description, specific details are given to provide a thorough understanding of the embodiments. However, it will be understood by those of ordinary skill in the art that the embodiments may be practiced without these specific details. For example, circuits may be shown in block diagrams in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, structures and techniques may not be shown in detail in order not to obscure the embodiments.
As shown in fig. 1, a chip start control circuit includes a timer and a processor, wherein the timer is connected to the processor and is configured to calculate a start time of a chip and generate an interrupt signal according to the start time; the processor performs a chip restart or an abnormal start in a start failure according to the received start time and the interrupt signal. The starting time is the time consumed from loading the chip configuration information to the configuration register by the loading module to acting the chip configuration information on the corresponding circuit by the configuration register, and is used for judging whether the starting process of the chip is overtime. The circuit described in this embodiment utilizes a timer to monitor the chip start-up process, allows the chip to restart many times, and when exceeding the restart times, the chip can interrupt the start-up process and utilize the interrupt program to skip the step of receiving the loading completion signal, let the chip directly start up, the circuit is simple in structure, easy to implement, makes the chip still start up under the condition of starting abnormity, and provides convenience for subsequent DEBUG.
As one implementation method, the circuit further comprises a power management module, a global reset register, an and gate, a read-write memory, a read-only memory, a programmable memory, a loading module and a configuration register, wherein the power management module is connected with the and gate and used for supplying power to each module in the circuit; the global reset register is connected with the AND gate and is used for triggering reset; the input end of the AND gate is connected with the power management module and the global reset register, and the output end of the AND gate is connected with the processor and the loading module and used for the AND logic operation of the power management module and the global reset register; the read-write memory is connected with the processor and used for recording the starting abnormal information; the read-only memory is connected with the processor and used for setting the repeated starting times; the programmable memory is connected with the loading module and used for storing the configuration information of the chip; the loading module is connected with the AND gate, the programmable memory and the configuration register and is used for loading the chip configuration information into the configuration register; and the configuration register is connected with the loading module and used for applying the chip configuration information to the corresponding circuit and generating a loading completion signal.
As shown in fig. 2, a chip start-up control method includes: s1, after the chip is powered on, the power management unit is used for judging whether the voltage is normal, and if the voltage is normal, the power-on reset signal is cancelled; s2, starting the chip, loading the chip configuration information into the configuration register by using the loading module, and starting timing by using the timer; s3, the chip waits for the register to return a loading completion signal, if the loading completion signal is received within a preset time, the chip is indicated to be started successfully, otherwise the chip is failed to start, if the chip fails to start, the starting process is interrupted, the starting failure times are recorded and compared with the preset times, if the former is less than or equal to the latter, the operation returns to S1, and if the former is greater than the latter, the operation enters S4; s4, the chip skips the receiving step of the loading completion signal and directly starts. The method of the embodiment uses a timer to monitor the chip starting process, allows the chip to be restarted for multiple times, and can skip the loading completion signal to directly start the chip when the number of times of restarting is exceeded.
As one of the implementation methods, in step S1, when the voltage is normal, the chip waits for a set time before deactivating the power-on reset signal. The method of the embodiment can stabilize the voltage after waiting for a period of time, and is beneficial to starting the chip.
As one implementation method, in step S2, after the loading module loads the chip configuration information into the configuration register, the configuration register turns on a configuration enable signal of the chip, so that the chip configuration information is applied to the corresponding circuit, and then the configuration register generates a loading completion signal.
As one of the implementation methods, in step S2, the timer starts to count when the loading module loads the chip configuration information into the configuration register, and ends counting after the configuration register applies the chip configuration information to the corresponding circuit. In the method of this embodiment, a timer is used for timing, so as to determine whether the start process of the chip is overtime.
As one of the implementation methods, before the chip returns to step S1 to execute in step S3, the following operations are performed: the chip triggers a reset using a global reset register.
As one of the implementation methods, in step S4, the process of the chip skipping the receiving step of the load complete signal is: the chip uses the interrupt program to bypass the receiving of the loading completion signal to complete the starting in the abnormal state, and records the abnormal information in the read-write memory. The method provided by the embodiment bypasses the loading completion signal, so that the chip can still be started under the condition of abnormal starting, and convenience is provided for subsequent DEBUG.
The present invention will be described in detail below.
The invention divides the starting process of the chip into four steps: firstly, electrifying; secondly, canceling power-on reset; thirdly, starting the chip and loading the configuration information of the chip; and fourthly, finishing loading the configuration information of the chip, and normally starting the chip.
Firstly, the power supply of the chip is switched on, and the first step of power-on process is realized. And then the power management module judges whether the voltage On the chip is normal or not, if the voltage meets the voltage requirement, the power-On reset signal POR (Power On reset) of the chip is cancelled after the voltage is stabilized for a period of time, and the second step is realized.
After the power-on reset is cancelled, the processor is started from a read only memory (BootROM or BROM), then a loading module (System Loader) loads chip configuration information from a programmable memory (EFUSE/Flash), and transmits the chip configuration information to a register which needs to be configured in the chip. The register is essential for normal work of the chip and mainly used for controlling analog parameters such as voltage of a system, a phase-locked loop and the like. And after the register receives the chip configuration information, opening a chip configuration enabling signal to enable the chip configuration information in the register to be applied to a corresponding circuit, and realizing the third step. Note that the timer starts counting at the same time the processor starts from the BROM. The timer may be a separate module or integrated in the processor, or may be implemented by software.
After that, the register generates a loading completion signal and transmits the loading completion signal to the processor, and if the processor successfully reads the loading completion signal of the register within the time range preset by the timer, the chip is normally started, so that the fourth step is realized. If the processor cannot read the loading completion signal on time due to an error in the process, the timer generates an interrupt signal to the processor, so that the processor interrupts the starting process and enters an exception handling mode. The processor analyzes the existing abnormal information in a read-write processor (SRAM) first, and then writes the currently generated abnormal information into the SRAM for use by subsequent DEBUG. And then, the global reset register and the power management module send a module reset signal to the processor and the loading module through the AND gate, then the reset is triggered, and the chip is restarted. After the Global Reset register writes a specific value, a Global Reset signal (Global Reset) is valid, Reset is released after a plurality of cycles, and the number of cycles can be determined according to the design requirements of a system.
The restarting chip can solve the problem of abnormal starting caused by unstable voltage, so the invention sets the restarting times of the chip in the BROM, on one hand, the probability of normal starting of the chip is improved, and on the other hand, the phenomena of death and the like are prevented. After the number of times of restarting the chip exceeds the set value, the timer still generates an interrupt signal to the processor, so that the processor interrupts the starting process, but does not trigger reset. Instead, the chip bypasses the load completion signal by using the interrupt program to realize the start in the abnormal state, and simultaneously records the abnormal start information into the SRAM. Thus, the purpose that the chip can be started even under abnormal conditions is achieved. This has the advantage that DEBUG can be performed by reading out the contents of the SRAM by various engineering means after the chip is started. Compared with the chip which can be started under the abnormal condition, the chip which can be started under the abnormal condition can not be started to have more DEBUG means, so the chip starting control circuit and the control method based on the software and hardware collaborative design can better solve the BUG encountered in the chip starting process.
In the embodiments provided by the present invention, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form. The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A chip start control circuit is characterized by comprising a timer and a processor, wherein the timer is connected with the processor and used for calculating the start time of a chip and generating an interrupt signal according to the start time; the processor performs a chip restart or an abnormal start in a start failure according to the received start time and the interrupt signal.
2. The chip start-up control circuit of claim 1, further comprising a power management block, a global reset register, an AND gate, a read-write memory, a read-only memory, a programmable memory, a loading block, and a configuration register, wherein,
the power management module is connected with the AND gate and used for supplying power to each module in the circuit;
the global reset register is connected with the AND gate and is used for triggering reset;
the input end of the AND gate is connected with the power management module and the global reset register, and the output end of the AND gate is connected with the processor and the loading module and used for the AND logic operation of the power management module and the global reset register;
the read-write memory is connected with the processor and used for recording the starting abnormal information;
the read-only memory is connected with the processor and used for setting the repeated starting times;
the programmable memory is connected with the loading module and used for storing the configuration information of the chip;
the loading module is connected with the AND gate, the programmable memory and the configuration register and is used for loading the chip configuration information into the configuration register;
and the configuration register is connected with the loading module and used for applying the chip configuration information to the corresponding circuit and generating a loading completion signal.
3. A chip start-up control method implemented by any one of the chip start-up control circuits of claims 1-2, the method comprising:
s1, after the chip is powered on, the power management unit is used for judging whether the voltage is normal, and if the voltage is normal, the power-on reset signal is cancelled;
s2, starting the chip, loading the chip configuration information into the configuration register by using the loading module, and starting timing by using the timer;
s3, the chip waits for the register to return a loading completion signal, if the loading completion signal is received within a preset time, the chip is indicated to be started successfully, otherwise the chip is failed to start, if the chip fails to start, the starting process is interrupted, the starting failure times are recorded and compared with the preset times, if the former is less than or equal to the latter, the operation returns to S1, and if the former is greater than the latter, the operation enters S4;
s4, the chip skips the receiving step of the loading completion signal and directly starts.
4. The chip start-up control method according to claim 3, wherein in step S1, when the voltage is normal, the chip waits for a set time before deactivating the power-on reset signal.
5. The chip start-up control method according to claim 3, wherein in step S2, after the loading module loads the chip configuration information into the configuration register, the configuration register turns on a configuration enable signal of the chip, so that the chip configuration information is applied to a corresponding circuit, and then the configuration register generates a load completion signal.
6. The chip start control method according to claim 3 or 5, wherein in step S2, the timer starts timing when the loading module loads the chip configuration information into the configuration register, and ends timing after the configuration register applies the chip configuration information to the corresponding circuit.
7. The chip start-up control method according to claim 3, wherein in step S3, before the chip returns to step S1, the following operations are performed: the chip triggers a reset using a global reset register.
8. The chip start-up control method according to claim 3, wherein in the step S4, the process of the chip skipping the step of receiving the load completion signal is: the chip uses the interrupt program to bypass the receiving of the loading completion signal to complete the starting in the abnormal state, and records the abnormal information in the read-write memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011559806.6A CN112596798B (en) | 2020-12-25 | 2020-12-25 | Chip start control circuit and control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011559806.6A CN112596798B (en) | 2020-12-25 | 2020-12-25 | Chip start control circuit and control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112596798A true CN112596798A (en) | 2021-04-02 |
| CN112596798B CN112596798B (en) | 2024-06-14 |
Family
ID=75202506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011559806.6A Active CN112596798B (en) | 2020-12-25 | 2020-12-25 | Chip start control circuit and control method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112596798B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113650498A (en) * | 2021-06-30 | 2021-11-16 | 东风汽车集团股份有限公司 | Power-on method and device for electric vehicle, electric vehicle and storage medium |
| CN114879811A (en) * | 2022-07-12 | 2022-08-09 | 苏州云途半导体有限公司 | Chip time sequence control method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090172470A1 (en) * | 2007-12-28 | 2009-07-02 | International Business Machines Corporation | Managing processing of a computing environment during failures of the environment |
| CN101916216A (en) * | 2010-09-08 | 2010-12-15 | 神州数码网络(北京)有限公司 | Device and control method for automatically repairing BOOTROM in embedded operating system |
| JP2014170306A (en) * | 2013-03-01 | 2014-09-18 | Nec Computertechno Ltd | Information processing device, automatic recovery method from startup fault, and automatic recovery program from startup fault |
| US20170255384A1 (en) * | 2016-03-01 | 2017-09-07 | Kabushiki Kaisha Toshiba | Efficient secure boot carried out in information processing apparatus |
| CN107179927A (en) * | 2017-05-12 | 2017-09-19 | 郑州云海信息技术有限公司 | A kind of embedded system start method based on BootRom |
| KR101947487B1 (en) * | 2018-04-12 | 2019-05-02 | 주식회사 케이디티 | monitoring control device for automatic data recovery |
| CN109960599A (en) * | 2017-12-14 | 2019-07-02 | 佛山市顺德区美的电热电器制造有限公司 | Chip system and its house dog self checking method, electrical equipment |
| CN111316235A (en) * | 2019-03-29 | 2020-06-19 | 深圳市大疆创新科技有限公司 | Method for starting system, electronic device and machine-readable storage medium |
-
2020
- 2020-12-25 CN CN202011559806.6A patent/CN112596798B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090172470A1 (en) * | 2007-12-28 | 2009-07-02 | International Business Machines Corporation | Managing processing of a computing environment during failures of the environment |
| CN101916216A (en) * | 2010-09-08 | 2010-12-15 | 神州数码网络(北京)有限公司 | Device and control method for automatically repairing BOOTROM in embedded operating system |
| JP2014170306A (en) * | 2013-03-01 | 2014-09-18 | Nec Computertechno Ltd | Information processing device, automatic recovery method from startup fault, and automatic recovery program from startup fault |
| US20170255384A1 (en) * | 2016-03-01 | 2017-09-07 | Kabushiki Kaisha Toshiba | Efficient secure boot carried out in information processing apparatus |
| CN107179927A (en) * | 2017-05-12 | 2017-09-19 | 郑州云海信息技术有限公司 | A kind of embedded system start method based on BootRom |
| CN109960599A (en) * | 2017-12-14 | 2019-07-02 | 佛山市顺德区美的电热电器制造有限公司 | Chip system and its house dog self checking method, electrical equipment |
| KR101947487B1 (en) * | 2018-04-12 | 2019-05-02 | 주식회사 케이디티 | monitoring control device for automatic data recovery |
| CN111316235A (en) * | 2019-03-29 | 2020-06-19 | 深圳市大疆创新科技有限公司 | Method for starting system, electronic device and machine-readable storage medium |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113650498A (en) * | 2021-06-30 | 2021-11-16 | 东风汽车集团股份有限公司 | Power-on method and device for electric vehicle, electric vehicle and storage medium |
| CN113650498B (en) * | 2021-06-30 | 2023-04-25 | 东风汽车集团股份有限公司 | Power-on method and device of electric vehicle, electric vehicle and storage medium |
| CN114879811A (en) * | 2022-07-12 | 2022-08-09 | 苏州云途半导体有限公司 | Chip time sequence control method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112596798B (en) | 2024-06-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109032822B (en) | Method and device for storing crash information | |
| US7890800B2 (en) | Method, operating system and computing hardware for running a computer program | |
| US20070101166A1 (en) | Method and apparatus for utilizing a microcontroller to provide an automatic order and timing power and reset sequencer | |
| JPS63108434A (en) | Program corrector of read-only-memory for digital data processor | |
| US8151130B2 (en) | Plural voltage level detection upon power drop for switching to standby mode with or without complete state saving interrupt processing | |
| CN112596798B (en) | Chip start control circuit and control method | |
| US20060010282A1 (en) | Method and apparatus to boot a system by monitoring an operating status of a NAND flash memory | |
| US5541943A (en) | Watchdog timer lock-up prevention circuit | |
| US11579977B2 (en) | Data storage device restoring method | |
| US7716524B2 (en) | Restarting an errored object of a first class | |
| CN103890713B (en) | Device and method for managing the register information in processing system | |
| KR100377608B1 (en) | Data processor and method of processing data | |
| US20050229035A1 (en) | Method for event synchronisation, especially for processors of fault-tolerant systems | |
| US7500021B2 (en) | Operation mode control circuit, microcomputer including the same, and control system using the microcomputer | |
| CN111914497A (en) | DSP core module fault recovery method | |
| US7711985B2 (en) | Restarting an errored object of a first class | |
| US6938115B2 (en) | Method and computer device with different criticality | |
| US20040078664A1 (en) | Information processing unit selecting one of reset vector addresses | |
| CN216083689U (en) | Backup system loading management circuit and embedded system | |
| JPS59178552A (en) | Self diagnosis controlling system | |
| CN118069205A (en) | Rollback method, device, equipment and storage medium of programmable logic device version | |
| CN116755919A (en) | Start control method and device, chip and debugging system thereof | |
| CN118819923A (en) | PMIC watchdog control method, system, equipment and storage medium | |
| JPH0120775B2 (en) | ||
| JP2000181510A (en) | Backup data protecting method for programmable controller, and programmable controller |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 519000 2706, No. 3000, Huandao East Road, Hengqin new area, Zhuhai, Guangdong Applicant after: Zhuhai Yiwei Semiconductor Co.,Ltd. Address before: Room 105-514, No.6 Baohua Road, Hengqin New District, Zhuhai City, Guangdong Province Applicant before: AMICRO SEMICONDUCTOR Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |