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CN112542499B - Display panel and manufacturing method thereof - Google Patents

Display panel and manufacturing method thereof Download PDF

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Publication number
CN112542499B
CN112542499B CN202011410199.7A CN202011410199A CN112542499B CN 112542499 B CN112542499 B CN 112542499B CN 202011410199 A CN202011410199 A CN 202011410199A CN 112542499 B CN112542499 B CN 112542499B
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layer
sub
hole
groove
segment
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CN112542499A (en
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夏晨
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The application provides a display panel and a manufacturing method thereof. The display panel comprises a display area and a bending area, and the bending area is positioned at one side of the display area. The display panel includes a flexible substrate and a thin film transistor layer, and a first planarization layer. The thin film transistor layer is disposed on one side of the flexible substrate. The thin film transistor layer includes an inorganic insulating layer and a first metal layer. The first metal layer is arranged on one surface of the inorganic insulating layer, which is far away from the flexible substrate. A hole digging groove is formed in the inorganic insulating layer. The hole digging groove is positioned in the bending area. The hole digging groove exposes the side wall of the inorganic insulating layer. The first metal layer comprises a source electrode, a drain electrode and a first wiring structure. The first wiring structure is located in the bending area. The first wiring structure is disposed on the sidewall. The first flat layer is arranged on one side of the thin film transistor layer away from the flexible substrate. The first flat layer covers the thin film transistor layer and fills the hole digging groove.

Description

Display panel and manufacturing method thereof
Technical Field
The present disclosure relates to display technology, and more particularly, to a display panel and a method for manufacturing the same.
Background
Organic light emitting diode (Organic Light Emitting Diode, OLED) displays have received increasing attention due to their light and thin profile, fast response, wide viewing angle, high contrast, flexibility, etc. And is widely applied to the display fields of mobile phones, flat panels, televisions and the like.
The flexible OLED display device comprises a flexible substrate layer, a thin film transistor layer, an OLED light-emitting layer, a thin film packaging layer and the like from bottom to top. The light-emitting principle of the OLED is to deposit an OLED light-emitting layer between two electrodes, apply a current to the OLED light-emitting layer, and emit light by carrier injection and recombination. In the flexible OLED display technology, after the display panel is bent, defects such as metal wire breakage may be caused in a bending region. Meanwhile, pad Bending (Pad bonding) technology bends a bonding Pad (COF) for placing a Chip On Film (COF), an integrated circuit (Integrated Circuit, IC) Chip bonding Pad of COP (Chip On Pi), a fan-out (Fanout) trace connected to a data signal in a pixel circuit of a display area, and some test circuit areas under an existing display panel together to the lower side of the panel, thereby narrowing the lower frame. However, the metal wire in the Pad bonding region is prone to cracking or breaking during Bending due to insufficient toughness, so that defects such as vertical bright lines and uncontrollable display are generated.
Disclosure of Invention
In view of the foregoing, an object of the present application is to provide a display panel and a method for manufacturing the same, which can prevent the trace of the pad bending region from cracking or breaking during bending.
The application provides a display panel, including display area and bending zone, bending zone is located display area one side, display panel includes: a flexible substrate; the thin film transistor layer is arranged on one surface of the flexible substrate and comprises an inorganic insulating layer and a first metal layer, the first metal layer is arranged on one surface, far away from the flexible substrate, of the inorganic insulating layer, a hole digging groove is formed in the inorganic insulating layer and is positioned in the bending area, the hole digging groove exposes out of the side wall of the inorganic insulating layer, the first metal layer comprises a source electrode, a drain electrode and a first wiring structure, the first wiring structure is positioned in the bending area, and the first wiring structure is arranged on the side wall; and the first flat layer is arranged on one side, far away from the flexible substrate, of the thin film transistor layer, and covers the thin film transistor layer and fills the hole digging groove.
In one embodiment, the hole digging groove comprises a first through hole and a second through hole which are communicated, the first through hole is positioned on one side of the second through hole away from the flexible substrate, and the aperture of the first through hole is larger than that of the second through hole.
In one embodiment, the first routing structure comprises a first sub-segment, a second sub-segment, a third sub-segment, a first connection segment and a second connection segment,
the first subsection is arranged on one surface, far away from the flexible substrate, of the thin film transistor layer, the second subsection is arranged at the bottom of the first through hole, the third subsection is arranged at the bottom of the second through hole, the first connection section is connected between the first subsection and the second subsection, and the second connection section is connected between the second subsection and the third subsection.
In one embodiment, the first flat layer filled in the hole digging groove is provided with a groove, the display panel further comprises a second metal layer, the second metal layer is arranged on one side, far away from the thin film transistor layer, of the first flat layer, the second metal layer comprises a second routing structure located in the bending region, and the second routing structure covers the groove.
In one embodiment, the second wiring structure includes a fourth sub-segment, a fifth sub-segment and a sixth sub-segment, the fourth sub-segment and the fifth sub-segment are disposed on a side of the thin film transistor layer away from the flexible substrate, the sixth sub-segment is connected between the fourth sub-segment and the fifth sub-segment, the fourth sub-segment is located on a side close to the display area, and the sixth sub-segment covers the side wall and the bottom surface of the groove.
In one embodiment, the inner wall of the groove is recessed inwards to form a step surface.
In one embodiment, the display panel further includes a second planarization layer covering the first planarization layer and the second metal layer, the second planarization layer being filled in the groove.
In one embodiment, the thin film transistor layer is provided with isolation grooves, the isolation grooves are located between adjacent pixel groups, and the first flat layer is filled in the isolation grooves.
In one embodiment, the isolation groove comprises a first sub groove and a second sub groove which are communicated, the second sub groove is positioned on one side of the first sub groove away from the flexible substrate, the aperture of the first sub groove ranges from 8 um to 13um, and the aperture of the second sub groove ranges from 15 um to 20um.
The application provides a manufacturing method of a display panel, which comprises the following steps: providing a flexible substrate; forming a thin film transistor layer on one side of the flexible substrate, wherein the step of forming the thin film transistor layer comprises: forming an inorganic insulating layer on one surface of the flexible substrate, forming a hole digging groove on the inorganic insulating layer positioned in a bending region, wherein the hole digging groove exposes the side wall of the inorganic insulating layer, forming a first metal layer on the inorganic insulating layer, the first metal layer comprises a source electrode, a drain electrode and a first wiring structure, and the first wiring structure is positioned in the bending region and is arranged on the side wall; and forming a first flat layer on one side of the thin film transistor layer away from the flexible substrate, wherein the first flat layer covers the thin film transistor layer and fills the hole digging groove.
A display panel comprising a display area and a inflection area, the inflection area being located at one side of the display area, the display panel comprising: a flexible substrate; the thin film transistor layer is arranged on one surface of the flexible substrate and comprises an inorganic insulating layer and a first metal layer, the first metal layer is arranged on one surface, far away from the flexible substrate, of the inorganic insulating layer, a hole digging groove is formed in the inorganic insulating layer and is positioned in the bending area, the hole digging groove exposes out of the side wall of the inorganic insulating layer, the first metal layer comprises a source electrode, a drain electrode and a first wiring structure, the first wiring structure is positioned in the bending area, and the first wiring structure is arranged on the side wall; and the first flat layer is arranged on one side, far away from the flexible substrate, of the thin film transistor layer, and covers the thin film transistor layer and fills the hole digging groove. Through seting up the hole digging groove in the inorganic insulating layer of bending region, expose the lateral wall of inorganic insulating layer to set up on the lateral wall of inorganic insulating layer with first line structure, can reduce when buckling because the membrane layer below the first line structure is uneven and produces the crackle because of the atress about the first line structure that the thick partially leads to.
In addition, the application also provides a manufacturing method of the display panel, and the manufactured flexible display panel has higher bending resistance.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a structure of a display panel provided in the present application.
Fig. 2 is a schematic cross-sectional view of the inflection region of fig. 1.
Fig. 3 is a schematic top view of a bending region of a display panel provided in the present application.
Fig. 4 is a schematic cross-sectional view of another structure of the display panel provided in the present application.
Fig. 5 is a schematic cross-sectional view of still another structure of the display panel provided in the present application.
Fig. 6 is a schematic top view of a display panel provided in the present application.
Fig. 7 is a schematic top view of a spacer groove of a display panel provided in the present application.
Fig. 8 is a schematic cross-sectional view of still another structure of the display panel provided in the present application.
Fig. 9 is a schematic structural view of the isolation trench of fig. 7.
Fig. 10 is a flowchart of a method for manufacturing a display panel provided in the present application.
Detailed Description
The technical solutions in the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, based on the embodiments herein, which are within the scope of the protection of the present application, will be within the skill of the art without undue effort.
In this application, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being directly connected, or may include both the first and second features not being directly connected, but being connected by another feature therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
Referring to fig. 1 and 2, a display panel 100 is provided. The display panel 100 may be an active light emitting display panel, such as an organic light emitting diode display panel, an Active Matrix Organic Light Emitting Diode (AMOLED) display panel, a Passive Matrix Organic Light Emitting Diode (PMOLED) display panel, a quantum dot organic light emitting diode (Quantum dot light emitting diode, QLED) display panel, a Micro light emitting diode (Micro-LED) display panel, a sub-millimeter light emitting diode (Mini-LED) display panel, and the like.
Hereinafter, the present application will be described in detail with reference to an OLED display panel as an example.
The display panel 100 includes a display area DA and a bending area BA located at one side of the display area DA.
The display panel 100 includes a flexible substrate 10, a thin film transistor layer 20, a first planarization layer 30, a second metal layer 40, a second planarization layer 50, and a light emitting layer 60, which are sequentially stacked.
The thin film transistor layer 20 is disposed on one side of the flexible substrate 10. The thin film transistor layer 20 may be provided on the upper surface of the flexible substrate 10 or may be provided on the lower surface of the flexible substrate 10.
The first planarization layer 30 is disposed on a side of the thin film transistor layer 20 away from the flexible substrate 10 and covers the thin film transistor layer 20.
The second metal layer 40 is disposed on a side of the first planarization layer 30 away from the thin film transistor layer 20.
The second planarization layer 50 is located on a side of the second metal layer 40 away from the thin film transistor layer, and covers the first planarization layer 30 and the second metal layer 40.
The light emitting layer 60 is disposed on a side of the second planarization layer 50 remote from the second metal layer 40.
The flexible substrate 10 may be formed of a single flexible organic layer, or may be formed of two or more flexible organic layers. The flexible organic layer is made of one or more materials selected from Polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI) and Polyethersulfone (PES). In one embodiment, the flexible substrate 10 includes a first polyimide layer 11, a first barrier layer 12, a second polyimide layer 13, and a second barrier layer 14, which are sequentially stacked. The materials of the first barrier layer 12 and the second barrier layer 14 are selected from inorganic materials such as silicon dioxide and silicon nitride.
The thin film transistor layer 20 includes an inorganic insulating layer 21 and a first metal layer 22. The inorganic insulating layer 21 is provided on one surface of the flexible substrate 10. The first metal layer 22 is disposed on a side of the inorganic insulating layer 21 away from the flexible substrate 10. Specifically, the thin film transistor layer 20 includes an active layer CL, a first gate insulating layer GI1, a first gate layer GE1, a second gate insulating layer GI2, a second gate layer GE2, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a first metal layer 22, which are stacked in this order. The first metal layer 22 may also be referred to as a source drain metal layer. The inorganic insulating layer 21 refers to all inorganic insulating layers constituting the thin film transistor layer 20, and includes a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer IL1, and a second interlayer insulating layer IL2.
It will be appreciated that the structure of the thin film transistor included in the thin film transistor layer 20 is not limited in this application, and it may be a top gate thin film transistor, a bottom gate thin film transistor, a double gate thin film transistor as shown in fig. 1, or a single gate thin film transistor.
A hole digging groove 21a is formed in the inorganic insulating layer 21. The cutout 21a is located in the inflection region DA. The perforated groove 21a exposes the sidewall 210 of the inorganic insulating layer 21. The depth of the hole digging groove 21a is not limited, and the hole digging groove may penetrate through the inorganic insulating layer 21 to expose the upper surface of the flexible substrate 10, may penetrate through the inorganic insulating layer 21 and extend into the flexible substrate 10, or may be a blind hole formed in the inorganic insulating layer 21, and does not penetrate through the inorganic insulating layer 21.
In one embodiment, the burring groove 21a is formed by forming the first and second through holes DH1 and DH2 in the inorganic insulating layer 21 located at the inflection region BA. The first through hole DH1 and the second through hole DH2 communicate. Therefore, the process difficulty can be reduced, and the yield can be improved. The first through hole DH1 is located on a side of the second through hole DH2 remote from the flexible substrate 10. The first via DH1 has a larger pore diameter than the second via DH 2. Thereby, the side wall 210 is formed in a stepped shape.
The depth of the first and second through holes DH1 and DH2 is not limited in the present application. In one embodiment, the first via DH1 may penetrate to the first gate insulating layer GI1, and the second via DH2 may penetrate the inorganic insulating layer 21 and expose the upper surface of the flexible substrate 10.
The first metal layer 22 includes a source SE, a drain DE and a first wiring structure 221. The source electrode SE and the drain electrode DE are located in the display area DA. The first wiring structure 221 is located in the bending area BA. The first routing structure 221 is disposed on the sidewall 210. The first wiring structure 221 is used for providing a driving signal for the thin film transistor layer 20. In one embodiment, the first routing structure 221 may be electrically connected to the source electrode SE.
Referring to fig. 2, the first routing structure 221 includes a first sub-segment 2211, a second sub-segment 2212, a third sub-segment 2213, a first connection segment 2214 and a second connection segment 2215. The first sub-segment 2211 is located on the side of the third sub-segment 2213 near the display area DA. The second sub-segment 2212 is located between the first sub-segment 2211 and the third sub-segment 2213. The first connection segment 2214 is connected between the first sub-segment 2211 and the second sub-segment 2212. The second connection segment 2215 is connected between the second sub-segment 2212 and the third sub-segment 2213. The first subsection 2211 is disposed on a side of the thin film transistor layer 20 remote from the substrate 10. Specifically, the first subsection 2211 is arranged in the same layer as the source SE and the drain DE. The second sub-section 2212 is disposed at the bottom of the first through hole DH 1. The third subsection 2213 is disposed at the bottom of the second through hole DH 2. By forming the sidewall 210 in a stepped shape, the first wiring structure 221 is formed in a plurality of bent segments, and bending resistance can be enhanced.
The material of the first planarization layer 30 is an organic photoresist material. The first flat layer 30 is provided with a groove 31. The depth of the groove 31 is not limited in this application. The grooves 31 may extend through the entire first flat layer 30, or may be blind holes formed in the first flat layer 30.
Referring to fig. 1 and 2 again, the second metal layer 40 includes a connection electrode 41 and a second trace structure 42. The connection electrode 41 electrically connects the thin film transistor layer 20 and the light emitting layer 60. The second trace structure 42 is located in the bending area BA. In one embodiment, the second routing structure 42 may be electrically connected with the connection electrode 41 and provide the VDD signal to the connection electrode 41. The connection electrodes 41 are distributed in a net shape in the plane, thereby improving the uniformity of luminance in the plane. The second wiring structure 42 is disposed on a side of the first wiring structure 221 away from the display area DA. Specifically, referring to fig. 3, the plurality of second wiring structures 42 and the plurality of first wiring structures 221 are alternately arranged in the bending area BA. In one embodiment, the first wiring structure 221 is further provided with a through hole 221a for releasing bending stress. The second trace structure 42 is further provided with a through hole 42a for releasing bending stress.
Referring to fig. 1 and 2 again, the second trace structure 42 covers the recess 31. The second trace structure 42 includes a fourth sub-segment 421, a fifth sub-segment 422, and a sixth sub-segment 423. The fourth 421 and fifth 422 sub-segments are provided on the side of the thin film transistor layer 20 remote from the substrate 10. The sixth sub-segment 423 connects the fourth sub-segment 421 and the fifth sub-segment 422. The fourth subsection 421 is located on a side adjacent to the display area DA. The sixth sub-segment 423 covers the side wall and the bottom surface of the groove 31.
Additionally, in one embodiment, the first routing structure 221 has a first end for connecting to a drive assembly, e.g., a third sub-segment 2213. The second trace structure 42 also has a second end for connecting to a drive assembly, e.g., a sixth sub-segment 423. The first end and the second end are located in different layers to prevent interference between the wirings.
The second planarization layer 50 covers the first planarization layer 30 and the second metal layer 40 and fills in the groove 31. The material of the second planarization layer 50 is an inorganic insulating material.
The light emitting layer 60 includes an organic light emitting diode display device and a pixel defining layer. The OLED display device includes an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, a cathode, and the like, which are sequentially stacked. The anode of the OLED display device is electrically connected to the thin film transistor layer 20.
It is understood that the number of through holes constituting the burrow grooves 21a is not limited in the present application. In other embodiments of the present application, referring to fig. 4, the hole digging groove 21a may also include only one through hole. In other embodiments, the cutout groove 21a may further include two or more through holes.
Referring to fig. 5, in another embodiment of the present application, the inner wall of the groove 31 may also have a step surface 311. Specifically, the groove 31 may include two first openings 31a and second openings 31b communicating with each other. The second opening 31b is located on the side of the first opening 31a remote from the flexible substrate 10. The first opening 31a and the second opening 31b are different in size, thereby forming the stepped surface 311. In other embodiments of the present application, the inner wall of the groove 31 may have a plurality of stepped surfaces 311 having different heights.
Referring to fig. 6 to 8, the display panel 100 includes a plurality of pixels PX disposed in a display area DA. A plurality of pixels PX arranged in the first direction X constitute one pixel group PG. In one embodiment, the first direction X is an extension direction of the first gate electrode GE1 and the second gate electrode GE 2.
An isolation trench 201 is formed in the inorganic insulating layer 21 of the thin film transistor layer 20 located in the display area DA. The first planarization layer 30 is filled in the isolation trench 201. Thereby, the bending resistance of the display area DA is improved.
The depth of isolation trenches 201 is not limited in this application. In one embodiment of the present application, the isolation trench 201 may extend through the inorganic insulating layer 21 of the entire thin film transistor layer 20. In other embodiments of the present application, the isolation trench 201 may not penetrate the inorganic insulating layer 21 of the thin film transistor layer 20, i.e., may be a blind via formed in the inorganic insulating layer 21.
In one embodiment, each isolation slot 201 includes a first sub-slot 201a and a second sub-slot 201b in communication. The second sub-groove 201b is located on the side of the first sub-groove 201a remote from the flexible substrate 10. By forming the isolation groove 201 in two steps, the process difficulty can be reduced while ensuring the depth of the isolation groove.
Referring to fig. 1 and 9, the first sub-groove 201a and the second sub-groove 201b each have a truncated cone shape with a diameter gradually decreasing from a direction away from the flexible substrate 10 toward a direction closer to the flexible substrate 10. The aperture D1 of the first sub-groove 201a ranges from 8 to 13um, i.e., the diameter of the top surface of the first sub-groove 201a on the side away from the flexible substrate 10 ranges from 8 to 13um. The aperture D2 of the second sub-groove 201b ranges from 15 to 20um, i.e., the diameter of the top surface of the second sub-groove 201b on the side away from the flexible substrate 10 ranges from 8 to 13um. The apertures of the first sub-slot 201a and the second sub-slot 201b determine the width of the isolation slot 201 between two adjacent rows of pixels. Therefore, it takes into consideration the pitch between the pixel units PX in design. When the width of the isolation groove 201 between the adjacent two pixel groups PG is too wide, the material of the first passivation layer 30 overflows to the pixels PX. When the width of the isolation groove 201 between the adjacent two rows of the pixel groups PG is too narrow, it cannot function to improve the bending performance.
Referring to fig. 1, fig. 2, and fig. 10, the present application also provides a method for manufacturing a display panel, which is used for manufacturing the display panel of the present application. The manufacturing method of the display panel comprises the following steps:
s1: a flexible substrate 10 is provided.
The flexible substrate 10 may be formed of a single flexible organic layer, or may be formed of two or more flexible organic layers. The flexible organic layer is made of one or more materials selected from polyimide, polyethylene naphthalate, polyethylene terephthalate, polyarylate, polycarbonate, polyetherimide and polyethersulfone. In one embodiment, the flexible substrate 10 includes a first polyimide layer 11, a first barrier layer 12, a second polyimide layer 13, and a second barrier layer 14, which are sequentially stacked. The materials of the first barrier layer 12 and the second barrier layer 14 are selected from inorganic materials such as silicon dioxide and silicon nitride.
S2: a thin film transistor layer 20 is formed on one side of the flexible substrate 10. Wherein the step of forming the thin film transistor layer 20 includes: an inorganic insulating layer 21 is formed on one side of the flexible substrate 10, and a hole digging groove 21a is formed on the inorganic insulating layer 21 located at the bending area BA. The perforated groove 21a exposes the sidewall 210 of the inorganic insulating layer 21. A first metal layer 22 is formed on the inorganic insulating layer 21.
The thin film transistor layer 20 may be provided on the upper surface of the flexible substrate 10 or may be provided on the lower surface of the flexible substrate 10.
Specifically, the thin film transistor layer 20 includes an active layer CL, a first gate insulating layer GI1, a first gate layer GE1, a second gate insulating layer GI2, a second gate layer GE2, a first interlayer insulating layer IL1, a second interlayer insulating layer IL2, and a first metal layer 22, which are stacked in this order. The first metal layer 22 may also be referred to as a source drain metal layer. The inorganic insulating layer 21 refers to all inorganic insulating layers constituting the thin film transistor layer 20, and includes a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer IL1, and a second interlayer insulating layer IL2.
It will be appreciated that the structure of the thin film transistor included in the thin film transistor layer 20 is not limited in this application, and it may be a top gate thin film transistor, a bottom gate thin film transistor, a double gate thin film transistor as shown in fig. 1, or a single gate thin film transistor.
The depth of the hole digging groove 21a is not limited, and the hole digging groove may penetrate through the inorganic insulating layer 21 to expose the upper surface of the flexible substrate 10, may penetrate through the inorganic insulating layer 21 and extend into the flexible substrate 10, or may be a blind hole formed in the inorganic insulating layer 21, and does not penetrate through the inorganic insulating layer 21.
In one embodiment, the burring groove 21a is formed by forming the first and second through holes DH1 and DH2 in the inorganic insulating layer 21 located at the inflection region BA. The first through hole DH1 and the second through hole DH2 communicate. Therefore, the process difficulty can be reduced, and the yield can be improved. The first through hole DH1 is located on a side of the second through hole DH2 remote from the flexible substrate 10. The first via DH1 has a larger pore diameter than the second via DH 2. Thereby, the side wall 210 is formed in a stepped shape.
The depth of the first and second through holes DH1 and DH2 is not limited in the present application. In one embodiment, the first via DH1 may penetrate to the first gate insulating layer GI1, and the second via DH2 may penetrate the inorganic insulating layer 21 and expose the upper surface of the flexible substrate 10.
The first metal layer 22 includes a source SE, a drain DE and a first wiring structure 221. The source electrode SE and the drain electrode DE are located in the display area DA. The first wiring structure 221 is located in the bending area BA. The first routing structure 221 is disposed on the sidewall 210. The first wiring structure 221 is used for providing a driving signal for the thin film transistor layer 20. In one embodiment, the first routing structure 221 may be electrically connected to the source electrode SE.
Referring to fig. 2, the first routing structure 221 includes a first sub-segment 2211, a second sub-segment 2212, a third sub-segment 2213, a first connection segment 2214 and a second connection segment 2215. The first sub-segment 2211 is located on the side of the third sub-segment 2213 near the display area DA. The second sub-segment 2212 is located between the first sub-segment 2211 and the third sub-segment 2213. The first connection segment 2214 is connected between the first sub-segment 2211 and the second sub-segment 2212. The second connection segment 2215 is connected between the second sub-segment 2212 and the third sub-segment 2213. The first subsection 2211 is disposed on a side of the thin film transistor layer 20 remote from the substrate 10. Specifically, the first subsection 2211 is arranged in the same layer as the source SE and the drain DE. The second sub-section 2212 is disposed at the bottom of the first through hole DH 1. The third subsection 2213 is disposed at the bottom of the second through hole DH 2. By forming the sidewall 210 in a stepped shape, the first wiring structure 221 is formed in a plurality of bent segments, and bending resistance can be enhanced.
It is understood that the number of through holes constituting the burrow grooves 21a is not limited in the present application. In other embodiments of the present application, referring to fig. 4, the hole digging groove 21a may also include only one through hole. In other embodiments, the cutout groove 21a may further include two or more through holes.
Referring to fig. 2, the first routing structure 221 includes a first sub-segment 2211, a second sub-segment 2212, a third sub-segment 2213, a first connection segment 2214 and a second connection segment 2215. The first sub-segment 2211 is located on the side of the third sub-segment 2213 near the display area DA. The second sub-segment 2212 is located between the first sub-segment 2211 and the third sub-segment 2213. The first connection segment 2214 is connected between the first sub-segment 2211 and the second sub-segment 2212. The second connection segment 2215 is connected between the second sub-segment 2212 and the third sub-segment 2213. The first subsection 2211 is disposed on a side of the thin film transistor layer 20 remote from the substrate 10. Specifically, the first subsection 2211 is arranged in the same layer as the source SE and the drain DE. The second sub-section 2212 is disposed at the bottom of the first through hole DH 1. The third subsection 2213 is disposed at the bottom of the second through hole DH 2. By forming the sidewall 210 in a stepped shape, the first wiring structure 221 is formed in a plurality of bent segments, and bending resistance can be enhanced.
Referring to fig. 3, a through hole 221a is further formed in the first wiring structure 221 for releasing the bending stress.
Referring to fig. 6 to 8, the display panel 100 includes a plurality of pixels PX disposed in a display area DA. The plurality of pixels 71 arranged in the first direction constitute one pixel group PG. In one embodiment, the first direction is the extension direction of the gate.
An isolation trench 201 is formed in the inorganic insulating layer 21 of the thin film transistor layer 20 located in the display area DA. The first planarization layer 30 is filled in the isolation trench 201. Thereby, the bending resistance of the display area DA is improved.
The depth of isolation trenches 201 is not limited in this application. In one embodiment of the present application, the isolation trench 201 may extend through the inorganic insulating layer 21 of the entire thin film transistor layer 20. In other embodiments of the present application, the isolation trench 201 may not penetrate the inorganic insulating layer 21 of the thin film transistor layer 20, i.e., may be a blind via formed in the inorganic insulating layer 21.
In one embodiment, each isolation slot 201 includes a first sub-slot 201a and a second sub-slot 201b in communication. The second sub-groove 201b is located on the side of the first sub-groove 201a remote from the flexible substrate 10. By forming the isolation groove 201 in two steps, the process difficulty can be reduced while ensuring the depth of the isolation groove.
Referring to fig. 1 and 9, the first sub-groove 201a and the second sub-groove 201b are each in the shape of a circular truncated cone, and the diameters thereof gradually decrease from the direction away from the flexible substrate 10 toward the direction toward the flexible substrate 10. The aperture D1 of the first sub-groove 201a ranges from 8 to 13um, i.e., the diameter of the top surface of the first sub-groove 201a on the side away from the flexible substrate 10 ranges from 8 to 13um. The aperture D2 of the second sub-groove 201b ranges from 15 to 20um, i.e., the diameter of the top surface of the second sub-groove 201b on the side away from the flexible substrate 10 ranges from 8 to 13um. The apertures of the first sub-slot 201a and the second sub-slot 201b determine the width of the isolation slot 201 between two adjacent rows of pixels. Therefore, it takes into consideration the pitch between the pixel units PX in design. If the width of the isolation groove 201 between two adjacent pixel groups PG is too wide, the material of the first passivation layer 30 overflows to the pixels PX. If the width of the isolation groove 201 between the adjacent two rows of the pixel groups PG is too narrow, the effect of improving the bending performance cannot be played.
The first via DH1 is fabricated using the same mask as the first sub-trench 201 a. The second via DH2 is fabricated using the same mask as the second sub-trench 201b. Thus, the photomask can be saved and the number of steps can be reduced.
S3: a first planarization layer 30 is formed on a side of the thin film transistor layer 20 away from the flexible substrate 10, the first planarization layer 30 covering the thin film transistor layer 20 and filling the hole-digging groove 21a.
The material of the first planarization layer 30 is an organic photoresist material.
In one embodiment, the first planar layer covers isolation trenches 201. Thereby, the bending resistance of the display area DA is improved.
S4: a groove 31 is provided in the first flat layer 30 filled in the cutout groove 21a.
The material of the first planarization layer 30 is an organic photoresist material. The first flat layer 30 is provided with a groove 31. The depth of the groove 31 is not limited in this application. The grooves 31 may extend through the entire first flat layer 30, or may be blind holes formed in the first flat layer 30.
Referring to fig. 5, in another embodiment of the present application, the inner wall of the groove 31 may also have a step surface 311. Specifically, the groove 31 may include two first openings 31a and second openings 31b communicating with each other. The second opening 31b is located on the side of the first opening 31a remote from the flexible substrate 10. The first opening 31a and the second opening 31b are different in size, thereby forming the stepped surface 311. In other embodiments of the present application, the inner wall of the groove 31 may have a plurality of stepped surfaces 311 having different heights.
In one embodiment, in step S4, the first planarization layer 30 is filled in the isolation trench 201.
S5: and forming a second metal layer on one side of the first flat layer far away from the thin film transistor layer, wherein the second metal layer comprises a second wiring structure positioned in the bending region, and the second wiring structure covers the groove.
Referring to fig. 1 and 2 again, the second metal layer 40 includes a connection electrode 41 and a second trace structure 42. The connection electrode 41 electrically connects the thin film transistor layer 20 and the light emitting layer 60. The second trace structure 42 is located in the bending area BA. In one embodiment, the second routing structure 42 may be electrically connected with the connection electrode 41 and provide the VDD signal to the connection electrode 41. The connection electrodes 41 are distributed in a net shape in the plane, thereby improving the uniformity of luminance in the plane. The second wiring structure 42 is disposed on a side of the first wiring structure 221 away from the display area DA. Specifically, referring to fig. 3, the plurality of second wiring structures 42 and the plurality of first wiring structures 221 are alternately arranged in the bending area BA. In one embodiment, the first wiring structure 221 is further provided with a through hole 221a for releasing bending stress. The second trace structure 42 is further provided with a through hole 42a for releasing bending stress.
The second trace structure 42 covers the recess 31. The second trace structure 42 includes a fourth sub-segment 421, a fifth sub-segment 422, and a sixth sub-segment 423. The fourth 421 and fifth 422 sub-segments are provided on the side of the thin film transistor layer 20 remote from the substrate 10. The sixth sub-segment 423 connects the fourth sub-segment 421 and the fifth sub-segment 422. The fourth subsection 421 is located on a side adjacent to the display area DA. The sixth sub-segment 423 covers the side wall and the bottom surface of the groove 31.
Additionally, in one embodiment, the first routing structure 221 has a first end for connecting to a drive assembly, e.g., a third sub-segment 2213. The second trace structure 42 also has a second end for connecting to a drive assembly, e.g., a sixth sub-segment 423. The first end and the second end are located in different layers to prevent interference between the wirings.
S6: a second planarization layer is formed on a side of the first planarization layer and the second metal layer remote from the first planarization layer.
The second planarization layer 50 covers the first planarization layer 30 and the second metal layer 40 and fills in the groove 31. The material of the second planarization layer 50 is an inorganic insulating material.
S7: and forming a light-emitting layer on one side of the second flat layer away from the second metal layer.
The light emitting layer 60 includes an organic light emitting diode display device and a pixel defining layer. The OLED display device includes an anode, a hole injection layer, a hole transport layer, an organic light emitting layer, an electron transport layer, an electron injection layer, a cathode, and the like, which are sequentially stacked. The anode of the OLED display device is electrically connected to the thin film transistor layer 20.
It is to be understood that the above-described order of steps for the method is for illustration only and that the steps of the method of the invention are not limited to the order specifically described above unless otherwise specifically indicated.
The application provides a display panel, it includes display area and bending zone, bending zone is located display area one side, display panel includes: a flexible substrate; the thin film transistor layer is arranged on one surface of the flexible substrate and comprises an inorganic insulating layer and a first metal layer, the first metal layer is arranged on one surface, far away from the flexible substrate, of the inorganic insulating layer, a hole digging groove is formed in the inorganic insulating layer and is positioned in the bending area, the hole digging groove exposes out of the side wall of the inorganic insulating layer, the first metal layer comprises a source electrode, a drain electrode and a first wiring structure, the first wiring structure is positioned in the bending area, and the first wiring structure is arranged on the side wall; and the first flat layer is arranged on one side, far away from the flexible substrate, of the thin film transistor layer, and covers the thin film transistor layer and fills the hole digging groove. Through seting up the hole digging groove in the inorganic insulating layer of bending region, expose the lateral wall of inorganic insulating layer to set up on the lateral wall of inorganic insulating layer with first line structure, can reduce when buckling because the membrane layer below the first line structure is uneven and produces the crackle because of the atress about the first line structure that the thick partially leads to.
In addition, through setting up the recess in the first flat layer of bending zone, make bending zone second walk the line structure and distribute and be the wave and walk the line on first flat layer, and first line structure and second walk line structure and arrange in bending zone alternately, can effectively strengthen bending performance.
And, through forming the isolation groove in the thin film transistor layer of the display area, and filling the isolation groove with the first flat layer, the stress release during bending can be further assisted, and the effect of increasing the bending resistance of the display area is achieved.
In addition, the application also provides a manufacturing method of the display panel, and the manufactured flexible display panel has higher bending resistance.
The foregoing has provided a detailed description of embodiments of the present application, with specific examples being set forth herein to provide a thorough understanding of the present application. Meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.

Claims (6)

1. A display panel, the display panel including a display area and a bending area, the bending area being located at one side of the display area, the display panel comprising:
a flexible substrate;
the thin film transistor layer is arranged on one surface of the flexible substrate;
the thin film transistor layer comprises an inorganic insulating layer and a first metal layer, and the first metal layer is arranged on one surface of the inorganic insulating layer, which is far away from the flexible substrate;
the inorganic insulating layer is provided with a hole digging groove corresponding to the bending area, the hole digging groove comprises a first through hole and a second through hole which are communicated, the first through hole is positioned at one side of the second through hole far away from the flexible substrate, the aperture of the first through hole is larger than that of the second through hole, the hole digging groove exposes out of the side wall of the inorganic insulating layer, the first metal layer comprises a source electrode, a drain electrode and a first wiring structure positioned in the bending area, the first wiring structure is arranged on the side wall and is formed into bent sections through the side wall, at least one section of the first wiring structure is arranged at the bottom of the hole digging groove, and the first wiring structure is provided with a first hole;
the inorganic insulating layer is provided with an isolation groove corresponding to the display area, the isolation groove is positioned between adjacent pixel groups, the isolation groove comprises a first subslot and a second subslot which are communicated, the second subslot is positioned on one side of the first subslot far away from the flexible substrate, the aperture range of the first subslot is 8-13 um, and the aperture range of the second subslot is 15-20 um; the first through hole and the first sub-slot are manufactured by adopting the same mask, and the second through hole and the second sub-slot are manufactured by adopting the same mask;
the display panel further comprises a first flat layer, the first flat layer is arranged on one side, far away from the flexible substrate, of the thin film transistor layer, the first flat layer covers the thin film transistor layer and fills the hole digging groove and the isolation groove, a groove is formed in the first flat layer, the display panel further comprises a second metal layer, the second metal layer is arranged on one side, far away from the thin film transistor layer, of the first flat layer, the second metal layer comprises a second wiring structure located in the bending area, the second wiring structure covers the groove, and a second hole is formed in the second wiring structure;
the grooves are formed in one side, far away from the display area, of the hole digging grooves, and the second wiring structures and the first wiring structures are alternately arranged in the bending area.
2. The display panel of claim 1, wherein the first routing structure comprises a first sub-segment, a second sub-segment, a third sub-segment, a first connection segment, and a second connection segment,
the first subsection is arranged on one surface, far away from the flexible substrate, of the thin film transistor layer, the second subsection is arranged at the bottom of the first through hole, the third subsection is arranged at the bottom of the second through hole, the first connection section is connected between the first subsection and the second subsection, and the second connection section is connected between the second subsection and the third subsection.
3. The display panel of claim 1, wherein the second routing structure includes a fourth sub-segment, a fifth sub-segment, and a sixth sub-segment, the fourth sub-segment and the fifth sub-segment being disposed on a side of the thin film transistor layer away from the flexible substrate, the sixth sub-segment being connected between the fourth sub-segment and the fifth sub-segment, the fourth sub-segment being located on a side near the display area, the sixth sub-segment covering a sidewall and a bottom surface of the recess.
4. The display panel of claim 3, wherein the inner wall of the recess is recessed inward to form a stepped surface.
5. The display panel of claim 1, further comprising a second planarization layer covering the first planarization layer and the second metal layer, the second planarization layer filling in the recess.
6. A method of manufacturing a display panel, comprising the steps of:
providing a flexible substrate;
forming a thin film transistor layer on one side of the flexible substrate; wherein the step of forming the thin film transistor layer includes: forming an inorganic insulating layer on one surface of the flexible substrate, forming a hole digging groove on the inorganic insulating layer positioned in a bending region, wherein the hole digging groove is formed by forming a first through hole and a second through hole which are communicated with each other in the inorganic insulating layer positioned in the bending region, the first through hole is positioned on one side of the second through hole away from the flexible substrate, the aperture of the first through hole is larger than that of the second through hole, and the hole digging groove exposes the side wall of the inorganic insulating layer; forming a first metal layer on the inorganic insulating layer, wherein the first metal layer comprises a source electrode, a drain electrode and a first wiring structure positioned in the bending region, the first wiring structure is arranged on the side wall and is formed into bent multi-sections through the side wall, at least one section of the first wiring structure is arranged at the bottom of the hole digging groove, and a first hole is formed in the first wiring structure; the step of forming a thin film transistor layer further includes: an isolation groove is formed in the inorganic insulating layer located in the display area, the isolation groove comprises a first sub groove and a second sub groove which are communicated, the second sub groove is located on one side, far away from the flexible substrate, of the first sub groove, the aperture range of the first sub groove is 8-13 um, and the aperture range of the second sub groove is 15-20 um; the first through hole and the first sub-slot are manufactured by adopting the same mask, and the second through hole and the second sub-slot are manufactured by adopting the same mask; and
forming a first flat layer on one side of the thin film transistor layer far away from the flexible substrate, wherein the first flat layer covers the thin film transistor layer and fills the hole digging groove and the isolation groove, a groove is formed in the first flat layer, the display panel further comprises a second metal layer, the second metal layer is arranged on one side of the first flat layer far away from the thin film transistor layer, the second metal layer comprises a second wiring structure located in the bending region, the second wiring structure covers the groove, and a second hole is formed in the second wiring structure;
the grooves are formed in one side, far away from the display area, of the hole digging grooves, and the second wiring structures and the first wiring structures are alternately arranged in the bending area.
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