CN112447842A - Planar gate MOSFET and manufacturing method thereof - Google Patents
Planar gate MOSFET and manufacturing method thereof Download PDFInfo
- Publication number
- CN112447842A CN112447842A CN201910804058.4A CN201910804058A CN112447842A CN 112447842 A CN112447842 A CN 112447842A CN 201910804058 A CN201910804058 A CN 201910804058A CN 112447842 A CN112447842 A CN 112447842A
- Authority
- CN
- China
- Prior art keywords
- region
- doping concentration
- doped region
- planar gate
- effective doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims description 14
- 238000009827 uniform distribution Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000002019 doping agent Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000036962 time dependent Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The disclosure relates to a planar gate MOSFET and a manufacturing method thereof, belonging to the field of semiconductors, which can improve the reliability of an insulated gate dielectric layer and reduce the specific on-resistance of the planar gate MOSFET. The planar gate MOSFET comprises an insulated gate dielectric layer and a doped region positioned below the insulated gate dielectric layer, wherein the doped region is a variable doped region with variable effective doping concentration.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a planar gate MOSFET and a method for manufacturing the same.
Background
The existing planar gate technology is to perform uniform doping with concentration higher than that of an epitaxial layer in a JFET area so as to obtain low specific on-resistance. However, when the same voltage is applied, the lateral spread of the electric field is reduced by the highly doped JFET region, the electric field intensity in the insulated gate dielectric layer is increased, the reliability of the insulated gate dielectric layer is deteriorated, and the device is prone to failure. On the contrary, if the reliability of the insulated gate dielectric layer of the device needs to be ensured, the existing planar gate technology cannot ensure sufficiently low specific on-resistance.
Disclosure of Invention
The invention aims to provide a planar gate MOSFET and a manufacturing method thereof, which can improve the reliability of an insulated gate dielectric layer and reduce the specific on-resistance of the planar gate MOSFET.
According to a first embodiment of the present disclosure, a planar gate MOSFET is provided, which includes an insulated gate dielectric layer and a doped region located below the insulated gate dielectric layer, wherein the doped region is a variable doped region with a variable effective doping concentration.
Optionally, the variable doping region includes a surface region with a low effective doping concentration and a highly doped region with a high effective doping concentration, wherein the highly doped region is located below the surface region.
Optionally, the effective doping concentration variation within the surface region and the highly doped region is at least one of: uniform distribution, step change, and continuous change.
Optionally, the planar gate MOSFET includes an epitaxial region, and the effective doping concentration of the surface region is less than or equal to the effective doping concentration of the epitaxial region.
Optionally, the effective doping concentration of the surface region is 1% to 100% of the effective doping concentration of the epitaxial region.
Optionally, the planar gate MOSFET includes an epitaxial region, and an effective doping concentration of the highly doped region is greater than an effective doping concentration of the epitaxial region.
Optionally, the effective doping concentration of the high-doping region is 1-100 times of the effective doping concentration of the epitaxial region.
Optionally, the planar gate MOSFET includes a well region, and a thickness of the variable doping region is greater than or equal to a doping depth of the well region.
Optionally, the planar gate MOSFET is a planar gate SiC MOSFET or a planar gate silicon type MOSFET.
According to a second embodiment of the present disclosure, there is provided a method of manufacturing a planar gate MOSFET, the method including: forming a doped region of a planar gate MOSFET, wherein the doped region is a variable doped region with variable effective doping concentration; and forming an insulated gate dielectric layer on the doped region.
Optionally, the forming a doped region of a planar gate MOSFET includes: a highly doped region having a high effective doping concentration and a surface region having a low effective doping concentration on the highly doped region are formed.
Optionally, the effective doping concentration variation within the surface region and the highly doped region is at least one of: uniform distribution, step change, and continuous change.
Optionally, the forming a doped region of a planar gate MOSFET includes: and forming the doped region of the planar gate MOSFET by epitaxial growth or ion implantation.
By adopting the technical scheme, the doping area is formed by the variable doping area, so that the charge centers formed on the surface of the variable doping area are fewer when the variable doping area is exhausted by properly setting the effective doping concentration change of the variable doping area, the potential difference between the surface of the variable doping area and the insulated gate dielectric layer is effectively reduced, the electric field intensity born by the insulated gate dielectric layer is reduced, and the reliability of the insulated gate dielectric layer is improved. Moreover, by properly setting the effective doping concentration change of the variable doping region, the natural depletion width of the JFET region can be effectively reduced, the effective area of the JFET region is increased, and smaller JFET resistance is provided, so that the specific on-resistance can be effectively reduced, and the lower specific on-resistance means smaller chip area, namely better performance and lower cost. Therefore, the method is also applicable to the requirement of expecting to obtain lower specific on-resistance under the condition of the same reliability requirement of the insulated gate dielectric layer, and the requirement of expecting to improve the reliability of the insulated gate dielectric layer under the condition of the same reliability requirement of the insulated gate dielectric layer, and the two requirements can be realized by adjusting the effective doping concentration distribution of the variable doping region.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
fig. 1 illustrates an exemplary cross-sectional view of a planar gate MOSFET according to an embodiment of the disclosure.
Fig. 2 illustrates yet another exemplary cross-sectional view of a planar gate MOSFET according to an embodiment of the disclosure.
Fig. 3 shows a flow chart of a method of manufacturing a planar gate MOSFET according to an embodiment of the present disclosure.
Fig. 4a-4j illustrate in cross-sectional view a process flow for manufacturing a planar gate MOSFET according to one embodiment of the present disclosure.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
According to an embodiment of the present disclosure, a planar gate MOSFET is provided, which includes an insulated gate dielectric layer and a doped region located below the insulated gate dielectric layer, wherein the doped region is a variable doped region with a variable effective doping concentration.
Fig. 1 illustrates an exemplary cross-sectional view of a planar gate MOSFET according to an embodiment of the disclosure. As shown in fig. 1, the planar gate MOSFET includes, in order from top to bottom, a source metal region 310, an insulating dielectric isolation layer 309, a polysilicon gate electrode region 308, an insulating gate dielectric layer 307, a contact region 306 of a second conductivity type, a source region 305 of a first conductivity type, a well region 304 of a second conductivity type, a variable doped region 303 of a first conductivity type, an epitaxial region 302 of a first conductivity type, a substrate region 301 of a first conductivity type, and a drain metal region 311.
The effective doping concentration of the variable doping region 303 may vary by at least one of: step change and continuous change.
In the present disclosure, the effective doping concentration refers to the effective part after compensation of the P-type impurity and the N-type impurity, for example, the P-type doping is 2 x 1013cm-3N-type doping of 3 x 1013cm-3The semiconductor is N-type with an effective doping concentration of (3-2) × 1013cm-3＝1013cm-3。
By adopting the technical scheme, since the doping region is formed by the variable doping region 303, by properly setting the effective doping concentration change of the variable doping region 303, the number of charge centers formed on the surface of the variable doping region 303 when the variable doping region 303 is depleted can be reduced, the potential difference between the surface of the variable doping region 303 and the insulated gate dielectric layer 307 can be effectively reduced, the electric field intensity borne by the insulated gate dielectric layer 307 can be reduced, and the reliability of the insulated gate dielectric layer 307 can be improved. Moreover, by properly setting the effective doping concentration change of the variable doping region 303, the natural depletion width of the JFET region can be effectively reduced, the effective area of the JFET region is increased, and smaller JFET resistance is provided, so that the specific on-resistance can be effectively reduced, and the lower specific on-resistance means smaller chip area, namely better performance and lower cost. Therefore, the present disclosure is also applicable to the requirement of obtaining a lower specific on-resistance under the condition of the same requirement on the reliability of the insulated gate dielectric layer, and the requirement of improving the reliability of the insulated gate dielectric layer under the condition of the same requirement on the specific on-resistance, both of which can be realized by adjusting the effective doping concentration distribution of the variable doping region 303.
Fig. 2 illustrates yet another exemplary cross-sectional view of a planar gate MOSFET according to an embodiment of the disclosure. As shown in fig. 2, the variable doped region 303 includes a surface region 3031 having a low effective doping concentration and a highly doped region 3032 having a high effective doping concentration, wherein the highly doped region 3032 is located below the surface region 3031. The effective dopant concentration variations within the surface region 3031 and the highly doped region 3032 may each be at least one of: uniform distribution, step change, and continuous change.
The planar gate MOSFET shown in fig. 2 has the following advantageous effects:
(1) the inventors of the present disclosure have found that Time Dependent Dielectric Breakdown (TDDB), also known as time dependent breakdown, occurs in the dielectric layer. The length of time from the onset of the applied electric field to the breakdown of the dielectric layer is related to the strength of the applied electric field. The stronger the electric field, the shorter the time. When the device is in reverse withstand voltage, high working voltage is applied to the drain electrode, the JFET area is rapidly depleted, doped N-type impurities all lose electrons, and positively charged charge centers are formed, wherein the number of the charge centers near the surface plays a main role in surface potential. Compared with the prior art, the surface region 3031 of the variable doping region 303 under the insulated gate dielectric layer 307 has lower effective doping concentration, and fewer charge centers are formed on the surface of the surface region 3031 when the surface region 3031 is exhausted, so that the potential difference between the surface of the surface region 3031 and the insulated gate dielectric layer 307 is effectively reduced, the electric field intensity borne by the insulated gate dielectric layer 307 is reduced, and the reliability of the insulated gate dielectric layer 307 is improved.
(2) When the planar gate MOSFET works in the forward direction, the on-resistance is mainly composed of the channel resistance RCHJFET resistor RJFETExtended resistance, drift region resistance RDRIFTAnd (4) forming. Compared with the prior art, the variable doping region 303 consisting of the surface region 3031 with low effective doping concentration and the high doping region 3032 with high effective doping concentration exists below the insulated gate dielectric layer 307, the high doping region 3032 can effectively reduce the natural depletion width of the JFET region and increase the effective area of the JFET region, meanwhile, the high effective doping concentration enables the resistivity to be smaller, and the extra JFET resistance brought by the surface region 3031 can be compensated by the high doping region 3032, so that the lower JFET resistance can be provided by the present disclosure. The thin layer with high effective doping concentration formed by the variable doping region 303 below the well region 304 can slightly increase the peak field strength of the adjacent base region when the planar gate MOSFET is in voltage resistance, and the increase of the critical breakdown field strength of the material with high effective doping concentration can make up the point, so that the actual breakdown voltage is not influenced. When the planar gate MOSFET works in the forward direction, the high-effective doping concentration thin layer below the well region 304 can be used as a current expansion layer to accelerate the current collection of electrons flowing into the drift region from the JFET region and reduce the expansion resistance of the planar gate MOSFET, so that the specific on-resistance is effectively reduced.
In the present disclosure, the effective doping concentration of the surface region 3031 is less than or equal to the effective doping concentration of the epitaxial region 302 to improve the reliability of the insulated gate dielectric layer 307. For example, the effective doping concentration of the surface region 3031 may be 1% to 100% of the effective doping concentration of the epitaxial region 302.
In the present disclosure, the effective doping concentration of the highly doped region 3032 is greater than the effective doping concentration of the epitaxial region 302 to effectively reduce the specific on-resistance. For example, the effective doping concentration of the heavily doped region 3032 may be 1-100 times the effective doping concentration of the epitaxial region 302.
In addition, the thickness of the variable doping region 303 is greater than or equal to the doping depth of the well region 304, so that when the planar gate MOSFET works in the forward direction, a thin layer with high effective doping concentration formed below the well region 304 by the high doping region 3032 of the variable doping region 303 can be used as a current expansion layer, current collection of electrons flowing into a drift region from a JFET region is accelerated, the expansion resistance of the planar gate MOSFET is reduced, and the specific on-resistance is effectively reduced.
The planar gate MOSFET according to the embodiments of the present disclosure may be a planar gate SiC MOSFET or a planar gate silicon type MOSFET. SiC is a third generation semiconductor material whose material properties can withstand higher electric field strengths. For the SiC material device, the protection requirement on the insulating gate dielectric layer is high, and the method can be well applied to the SiC material device. Likewise, the present disclosure is equally applicable to other semiconductor materials, such as silicon materials.
Fig. 3 shows a flow chart of a method of manufacturing a planar gate MOSFET according to an embodiment of the present disclosure. As shown in fig. 3, the method comprises the steps of:
in step S31, forming a doped region of the planar gate MOSFET, wherein the doped region is a variable doped region with a variable effective doping concentration; and
in step S32, an insulated gate dielectric layer is formed on the doped region.
By adopting the technical scheme, the doping area is formed by the variable doping area, so that the charge centers formed on the surface of the variable doping area are fewer when the variable doping area is exhausted by properly setting the effective doping concentration change of the variable doping area, the potential difference between the surface of the variable doping area and the insulated gate dielectric layer is effectively reduced, the electric field intensity born by the insulated gate dielectric layer is reduced, and the reliability of the insulated gate dielectric layer is improved. Moreover, by properly setting the effective doping concentration change of the variable doping region, the natural depletion width of the JFET region can be effectively reduced, the effective area of the JFET region is increased, and smaller JFET resistance is provided, so that the specific on-resistance can be effectively reduced, and the lower specific on-resistance means smaller chip area, namely better performance and lower cost. Therefore, the method is also applicable to the requirement of expecting to obtain lower specific on-resistance under the condition of the same reliability requirement of the insulated gate dielectric layer, and the requirement of expecting to improve the reliability of the insulated gate dielectric layer under the condition of the same reliability requirement of the insulated gate dielectric layer, and the two requirements can be realized by adjusting the effective doping concentration distribution of the variable doping region.
Fig. 4a-4j illustrate in cross-sectional view a process flow for manufacturing a planar gate MOSFET according to one embodiment of the present disclosure. The process flow is exemplified by that the manufacturing material of the planar gate MOSFET is SiC material, the first conductivity type is N-type, and the second conductivity type is P-type.
In fig. 4a, N-type SiC substrate region 301 is formed and N-type epitaxial region 302 is formed on the N-type SiC substrate region. The parameters of the epitaxial region 302 are related to the voltage withstanding requirements of the planar gate MOSFET. Generally, the higher the withstand voltage requirement, the lower the effective doping concentration of the epitaxial region 302, and the thicker the thickness of the epitaxial region 302. The effective doping concentration of the epitaxial region 302 is typically 1013cm-3～1017cm-3The thickness is generally 5 μm or more.
Then in fig. 4b, a variable doped region 303 is formed by epitaxial growth or ion implantation.
In the epitaxial growth, the variable doping can be realized by adjusting the amount of the doping impurities. Ion implantation can directly achieve variable doping profiles, and low surface concentration of the variable doping region 303 can be achieved by impurity compensation implantation. The effective doping concentration of the surface region 3031 of the variable doped region 303 should be less than or equal to the effective doping concentration of the epitaxial region 302, typically 1% to 100% of the effective doping concentration of the epitaxial region 302, and the thickness of the surface region 3031 should be greater than or equal to 50 nm. The effective doping concentration of the highly doped region 3032 of the variable doped region 303 is generally 1 to 100 times that of the epitaxial region 302. Wherein the effective doping concentration variation within the surface region 3031 and the highly doped region 3032 may be at least one of: uniform distribution, step change, and continuous change.
Then in fig. 4c, P-type well regions 304 are formed by selective area implantation. The effective doping concentration of the P-well 304 is typically 1016cm-3～1019cm-3The thickness is generally 0.5 μm or more.
Then in fig. 4d, N + source regions 305 are formed by selective area implantation. The effective doping concentration of the N + source region 305 is typically 1018cm-3～1021cm-3The thickness is generally 0.2 μm or more.
Then in fig. 4e, P + contact regions 306 are formed by selective area implantation. The effective doping concentration of the P + contact region 306 is typically 1017cm-3～1020cm-3The thickness is generally 0.4 μm or more.
Then in fig. 4f, an insulated gate dielectric layer 307 is formed by thermal oxygen growth or deposition. The insulated gate dielectric layer 307 may be silicon dioxide, and the thickness is typically 0.01 μm to 0.3 μm.
Then in fig. 4g, polysilicon is deposited and portions of the polysilicon are etched by photolithography to form polysilicon gate electrode regions 308. The polysilicon is typically heavily doped and has a sheet resistance typically less than 100 ohms per sheet.
Then in fig. 4h, an insulating dielectric isolation layer 309 is formed by photolithographic etching. The insulating dielectric isolation layer 309 may typically be silicon dioxide or silicon nitride and is typically 0.1 μm to 3 μm thick.
Then in fig. 4i, a front side metal is deposited, forming source metal region 310. The front metal can be aluminum or other metal, and the thickness is about 4 μm.
Then in fig. 4j, a back metal is deposited, forming drain metal region 311. The back metal may be silver or other metal, and has a thickness of about 1 μm.
It will be understood by those skilled in the art that the specific values of the thickness, effective doping concentration, etc. mentioned in the above process flow are merely examples, and the disclosure is not limited thereto. In practice, the values of thickness, effective doping concentration, etc. will vary depending on the specific performance requirements of the planar gate MOSFET.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, various possible combinations will not be separately described in this disclosure.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.
Claims (13)
1. The planar gate MOSFET is characterized by comprising an insulated gate dielectric layer and a doped region positioned below the insulated gate dielectric layer, wherein the doped region is a variable doped region with variable effective doping concentration.
2. The planar gate MOSFET of claim 1, wherein the variable doped region comprises a surface region having a low effective doping concentration and a highly doped region having a high effective doping concentration, wherein the highly doped region is located below the surface region.
3. The planar gated MOSFET of claim 2 wherein the effective dopant concentration variations within the surface region and the highly doped region are at least one of: uniform distribution, step change, and continuous change.
4. The planar gate MOSFET of claim 2 comprising an epitaxial region, wherein the surface region has an effective doping concentration less than or equal to an effective doping concentration of the epitaxial region.
5. The planar gated MOSFET of claim 4 wherein the effective doping concentration of the surface region is between 1% and 100% of the effective doping concentration of the epitaxial region.
6. The planar gate MOSFET of claim 2, comprising an epitaxial region, wherein the highly doped region has an effective doping concentration greater than an effective doping concentration of the epitaxial region.
7. The planar gate MOSFET of claim 6, wherein the highly doped region has an effective doping concentration 1-100 times that of the epitaxial region.
8. The planar-gate MOSFET of any of claims 1-7, comprising a well region, wherein the thickness of the variable doped region is greater than or equal to the doping depth of the well region.
9. The planar gate MOSFET of any of claims 1 to 7, wherein the planar gate MOSFET is a planar gate SiC MOSFET or a planar gate silicon type MOSFET.
10. A method of fabricating a planar gate MOSFET, the method comprising:
forming a doped region of a planar gate MOSFET, wherein the doped region is a variable doped region with variable effective doping concentration; and
and forming an insulated gate dielectric layer on the doped region.
11. The method of claim 10, wherein forming the doped region of the planar gate MOSFET comprises:
a highly doped region having a high effective doping concentration and a surface region having a low effective doping concentration on the highly doped region are formed.
12. The method according to claim 10 or 11, wherein the effective doping concentration variation within the surface region and the highly doped region is at least one of: uniform distribution, step change, and continuous change.
13. The method of claim 10 or 11, wherein forming the doped region of the planar gate MOSFET comprises:
and forming the doped region of the planar gate MOSFET by epitaxial growth or ion implantation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910804058.4A CN112447842A (en) | 2019-08-28 | 2019-08-28 | Planar gate MOSFET and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910804058.4A CN112447842A (en) | 2019-08-28 | 2019-08-28 | Planar gate MOSFET and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112447842A true CN112447842A (en) | 2021-03-05 |
Family
ID=74741720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910804058.4A Pending CN112447842A (en) | 2019-08-28 | 2019-08-28 | Planar gate MOSFET and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112447842A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257897A (en) * | 2021-06-10 | 2021-08-13 | 北京中科新微特科技开发股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN113707722A (en) * | 2021-10-26 | 2021-11-26 | 北京世纪金光半导体有限公司 | Semiconductor device based on self-alignment and manufacturing method thereof |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082812A (en) * | 1998-06-22 | 2000-03-21 | Denso Corp | Silicon carbide semiconductor device and manufacture thereof |
| US20040119076A1 (en) * | 2002-12-20 | 2004-06-24 | Sei-Hyung Ryu | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors and methods of fabricating vertical JFET limited silicon carbide metal- oxide semiconductor field effect transistors |
| US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
| CN102194883A (en) * | 2010-03-19 | 2011-09-21 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| US20120292742A1 (en) * | 2011-05-20 | 2012-11-22 | Sumitomo Electric Industries, Ltd. | Semiconductor device |
| CN103890953A (en) * | 2012-03-23 | 2014-06-25 | 松下电器产业株式会社 | Semiconductor element |
| CN104538450A (en) * | 2014-12-29 | 2015-04-22 | 中国科学院半导体研究所 | SiC VDMOSFET structure with low specific on-resistance and manufacturing method thereof |
| US20150263145A1 (en) * | 2014-03-14 | 2015-09-17 | Cree, Inc. | Igbt structure for wide band-gap semiconductor materials |
| US20170025530A1 (en) * | 2015-02-27 | 2017-01-26 | Purdue Research Foundation | METHODS OF REDUCING THE ELECTRICAL AND THERMAL RESISTANCE OF SiC SUBSTRATES AND DEVICES MADE THEREBY |
| CN106898652A (en) * | 2017-03-09 | 2017-06-27 | 电子科技大学 | A kind of carborundum VDMOS device |
| US20170345891A1 (en) * | 2016-05-31 | 2017-11-30 | Cree, Inc. | Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods |
| US20180040701A1 (en) * | 2015-02-20 | 2018-02-08 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
| CN107919384A (en) * | 2016-10-07 | 2018-04-17 | 丰田自动车株式会社 | Semiconductor devices |
-
2019
- 2019-08-28 CN CN201910804058.4A patent/CN112447842A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082812A (en) * | 1998-06-22 | 2000-03-21 | Denso Corp | Silicon carbide semiconductor device and manufacture thereof |
| US20040119076A1 (en) * | 2002-12-20 | 2004-06-24 | Sei-Hyung Ryu | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors and methods of fabricating vertical JFET limited silicon carbide metal- oxide semiconductor field effect transistors |
| US20060192256A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | High-voltage power semiconductor device |
| CN102194883A (en) * | 2010-03-19 | 2011-09-21 | 株式会社东芝 | Semiconductor device and method of manufacturing the same |
| US20120292742A1 (en) * | 2011-05-20 | 2012-11-22 | Sumitomo Electric Industries, Ltd. | Semiconductor device |
| CN103890953A (en) * | 2012-03-23 | 2014-06-25 | 松下电器产业株式会社 | Semiconductor element |
| US20150263145A1 (en) * | 2014-03-14 | 2015-09-17 | Cree, Inc. | Igbt structure for wide band-gap semiconductor materials |
| CN104538450A (en) * | 2014-12-29 | 2015-04-22 | 中国科学院半导体研究所 | SiC VDMOSFET structure with low specific on-resistance and manufacturing method thereof |
| US20180040701A1 (en) * | 2015-02-20 | 2018-02-08 | Sumitomo Electric Industries, Ltd. | Silicon carbide semiconductor device |
| US20170025530A1 (en) * | 2015-02-27 | 2017-01-26 | Purdue Research Foundation | METHODS OF REDUCING THE ELECTRICAL AND THERMAL RESISTANCE OF SiC SUBSTRATES AND DEVICES MADE THEREBY |
| US20170345891A1 (en) * | 2016-05-31 | 2017-11-30 | Cree, Inc. | Super junction power semiconductor devices formed via ion implantation channeling techniques and related methods |
| CN107919384A (en) * | 2016-10-07 | 2018-04-17 | 丰田自动车株式会社 | Semiconductor devices |
| CN106898652A (en) * | 2017-03-09 | 2017-06-27 | 电子科技大学 | A kind of carborundum VDMOS device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113257897A (en) * | 2021-06-10 | 2021-08-13 | 北京中科新微特科技开发股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN113707722A (en) * | 2021-10-26 | 2021-11-26 | 北京世纪金光半导体有限公司 | Semiconductor device based on self-alignment and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4744958B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP4761942B2 (en) | Semiconductor device | |
| US8466513B2 (en) | Semiconductor device with enhanced mobility and method | |
| US20210005744A1 (en) | Semiconductor device and method for manufacturing the same | |
| JP6802454B2 (en) | Semiconductor devices and their manufacturing methods | |
| JP4948784B2 (en) | Semiconductor device and manufacturing method thereof | |
| US11791408B2 (en) | Semiconductor device | |
| KR101912030B1 (en) | Combined gate and source trench formation and related structure | |
| CN110190128B (en) | MOSFET device with silicon carbide double-side deep L-shaped base region structure and preparation method thereof | |
| CN112447842A (en) | Planar gate MOSFET and manufacturing method thereof | |
| KR20140044075A (en) | Semiconductor device and method manufacturing the same | |
| JP4049095B2 (en) | Semiconductor device and manufacturing method thereof | |
| US20210134989A1 (en) | Semiconductor device and method of manufacturing thereof | |
| CN117374125A (en) | Trench MOSFET device and preparation process thereof | |
| JP5037103B2 (en) | Silicon carbide semiconductor device | |
| JP7150609B2 (en) | Short channel trench power MOSFET | |
| JP7167717B2 (en) | semiconductor equipment | |
| CN111916502B (en) | Split-gate power MOSFET device with high-doping layer and preparation method thereof | |
| KR20140062868A (en) | Semiconductor device and method manufacturing the same | |
| CN112838131A (en) | Schottky diode based on silicon carbide planar MOS structure | |
| CN113410299A (en) | High-voltage-resistance n-channel LDMOS device and preparation method thereof | |
| CN112289845A (en) | Semiconductor device with JFET area layout design | |
| CN210325806U (en) | Semiconductor device with JFET (junction field effect transistor) area layout design | |
| CN113410281B (en) | P-channel LDMOS device with surface voltage-resistant structure and preparation method thereof | |
| JP7507248B2 (en) | Mosfet with saturated contact and method for forming a mosfet with saturated contact - Patents.com |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |