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CN112420529A - Package and method of forming a package - Google Patents

Package and method of forming a package Download PDF

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Publication number
CN112420529A
CN112420529A CN202011352636.4A CN202011352636A CN112420529A CN 112420529 A CN112420529 A CN 112420529A CN 202011352636 A CN202011352636 A CN 202011352636A CN 112420529 A CN112420529 A CN 112420529A
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CN
China
Prior art keywords
chip
coupler
layer
package
couplers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202011352636.4A
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Chinese (zh)
Other versions
CN112420529B (en
Inventor
李维平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Yibu Semiconductor Co ltd
Original Assignee
Shanghai Yibu Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Yibu Semiconductor Co ltd filed Critical Shanghai Yibu Semiconductor Co ltd
Priority to CN202011352636.4A priority Critical patent/CN112420529B/en
Publication of CN112420529A publication Critical patent/CN112420529A/en
Priority to KR1020210163984A priority patent/KR102665954B1/en
Priority to US17/535,984 priority patent/US11973061B2/en
Priority to TW110144187A priority patent/TWI782803B/en
Priority to US17/535,987 priority patent/US12087737B2/en
Priority to US17/535,985 priority patent/US20220173074A1/en
Application granted granted Critical
Publication of CN112420529B publication Critical patent/CN112420529B/en
Priority to KR1020230116745A priority patent/KR102666026B1/en
Priority to KR1020230116744A priority patent/KR102666025B1/en
Priority to KR1020230116743A priority patent/KR102752941B1/en
Priority to US18/413,020 priority patent/US20240153918A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
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    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Auxiliary Devices For And Details Of Packaging Control (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a package and a method for forming the same. A method of forming a package, comprising: placing a first chip layer over a carrier, the first chip layer including a plurality of first chips facing down and a plurality of chip couplers between the plurality of first chips; placing and assembling a second chip layer on the first chip layer, the second chip layer comprising a plurality of second chips facing down; molding all chip layers above the carrier; removing the carrier to form a packaging main body, and adding a rewiring layer and a bump below the packaging main body; and dividing the package main body to form a plurality of the packages.

Description

Package and method of forming a package
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a package and a method for forming the same.
Background
In the situation that the required functions of semiconductor integrated circuits are more and more increased and the required computation speed is faster, the industry has started to increase the investment in the development of chip stacking technology to find more effective solutions in the chip stacking technology. However, conventional Wafer Level Packaging (WLP) technology does not enable stacking of chips. In the conventional chip stacking technology, stacking is mostly completed in final assembly, and technologies such as Through Silicon Vias (TSVs), Through Glass Vias (TGVs), Through Glass vias (TMVs), Through Mold Vias (TMVs), or Wire-bonds (Wire-bonds) are required to vertically connect the stacked chips. The packaging process of the conventional stacking technique is complicated and costly.
Disclosure of Invention
Embodiments of the present invention provide a solution for forming a package including a plurality of chips stacked.
In one aspect, the present invention provides a method of forming a package, which may include: placing a first chip layer over a carrier, the first chip layer including a plurality of first chips facing down and a plurality of chip couplers between the plurality of first chips; placing and assembling a second chip layer on the first chip layer, the second chip layer comprising a plurality of second chips facing down; molding the first chip layer and the second chip layer over the carrier; removing the carrier to form a packaging main body, and adding a rewiring layer and a bump below the packaging main body; and dividing the package main body to form a plurality of the packages.
The package may include a first chip, a second chip placed over the first chip and assembled over the divided chip couplers, and divided chip couplers, wherein the second chip may be electrically coupled to the first chip through the divided chip couplers and the re-wiring layer.
The package may include a first chip, a second chip, and a chip coupler, wherein the second chip is placed over the first chip and assembled over the chip coupler, wherein the second chip is electrically coupleable to the first chip through the chip coupler and the redistribution layer.
In another aspect, the present invention provides a method of forming a package, which may include: placing a first chip layer over a carrier, the first chip layer including a plurality of first chip couplers and a first plurality of chips facing down; placing and assembling at least one second chip layer over the first chip layer, each second chip layer comprising a plurality of second chips facing down and a plurality of second chip couplers; placing and assembling a third chip layer on the at least one second chip layer, the third chip layer comprising a plurality of third chips facing down; molding the first chip layer, the at least one second chip layer, and the third chip layer over the carrier; removing the carrier to form a packaging main body, and adding a rewiring layer and a bump below the packaging main body; and dividing the package main body to form a plurality of the packages.
The package may include a first chip, at least one second chip, a third chip, a divided first chip coupler, and at least one divided second chip coupler, wherein the at least one divided second chip coupler is assembled over the divided first chip coupler, the at least one second chip is placed over the first chip, and the third chip is placed over the at least one second chip, wherein the third chip may be electrically coupled to the at least one second chip through the at least one divided second chip coupler, the divided first chip coupler, and the third chip may be electrically coupled to the first chip through the at least one divided second chip coupler, the divided first chip coupler, and the wiring layer, and the at least one second chip can be electrically coupled to the first chip through the divided first chip coupler and the re-wiring layer, or the at least one second chip can be electrically coupled to the first chip through the at least one divided second chip coupler, the divided first chip coupler and the re-wiring layer.
The package may include a first chip, at least one second chip assembled over the first chip coupler, a third chip placed over the first chip, a first chip coupler and at least one second chip coupler, wherein the third chip may be electrically coupled to the at least one second chip through the at least one second chip coupler, the first chip coupler, the third chip may be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler and the re-wiring layer, and the at least one second chip may be electrically coupled to the first chip through the first chip coupler and the re-wiring layer, or the at least one second chip can be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler, and the redistribution layer.
A portion of the plurality of first chip couplers may be integrally formed with at least one second chip coupler stacked thereon.
A portion of the plurality of first chip couplers may be the same in area in a horizontal direction as at least one second chip coupler stacked thereon.
A portion of the plurality of first chip couplers may be different in area in a horizontal direction from at least one second chip coupler stacked thereon.
In yet another aspect, the present invention provides a package comprising: a rewiring layer including a first side and a second side; a plurality of bumps disposed on a first side of the redistribution layer; a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer; a first chip connector and a second chip connector which are placed and assembled on the second side of the rewiring layer and are respectively placed and assembled horizontally on both sides of the first chip; and a second chip and a third chip respectively including a front surface and a back surface, the second chip having a front surface facing downward being placed and assembled on the back surface of the first chip and above the first chip coupler, and the third chip having a front surface facing downward being placed and assembled on the back surface of the first chip and above the second chip coupler, wherein the package is molded into a plastic package structure. Wherein the second chip is electrically coupled to the first chip through the first chip coupler and the redistribution layer, and the third chip is electrically coupled to the first chip through the second chip coupler and the redistribution layer.
In yet another aspect, the present invention provides a package comprising: a rewiring layer including a first side and a second side; a plurality of bumps disposed on a first side of the redistribution layer; a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer; a first chip connector placed and assembled on the second side of the rewiring layer and horizontally placed and assembled on a side surface of the first chip; at least one second chip coupler placed and assembled over the first chip coupler; at least one second chip comprising a front side and a back side, the at least one second chip being placed face down on the back side of the first chip and assembled over the first chip coupler; and a third chip placed over the back side of the at least one second chip and assembled over the at least one second chip coupler, wherein the package is molded into a plastic encapsulated structure. Wherein the at least one second chip is electrically coupled to the first chip through the first chip coupler and the redistribution layer, or the at least one second chip is electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler and the redistribution layer, wherein the third chip is electrically coupleable to the at least one second chip through the at least one second chip coupler and the first chip coupler, or the third chip is electrically coupleable to the at least one second chip through the at least one second chip coupler, wherein the third chip is electrically coupleable to the first chip through the at least one second chip coupler, the first chip coupler and the redistribution layer.
In yet another aspect, the present invention provides a package comprising: a rewiring layer including a first side and a second side; a plurality of bumps disposed on a first side of the redistribution layer; a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer; a first chip coupler placed and assembled on a second side of the rewiring layer, and horizontally placed and assembled on one side of the first chip; a cross-layer chip connector placed and assembled on a second side of the redistribution layer, and horizontally placed and assembled on the other side of the first chip; at least one second chip comprising a front side and a back side, the at least one second chip being placed face down over the back side of the first chip and assembled over the first chip coupler; at least one second chip coupler placed and assembled over the first chip coupler; and a third chip placed over the back side of the at least one second chip and assembled over the cross-layer chip coupler, wherein the package is molded into a plastic encapsulated structure. Wherein the at least one second chip is electrically coupleable to the first chip through the first chip coupler and the redistribution layer, or the at least one second chip can be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler, and the re-wiring layer, wherein the third chip is electrically coupleable to the at least one second chip by the cross-layer chip coupler, the redistribution layer, the first chip coupler, and the at least one second chip coupler, or the third chip can be electrically coupled to the at least one second chip through the cross-layer chip coupler, the redistribution layer, and the first chip coupler, wherein the third chip is electrically coupleable to the first chip through the cross-layer chip coupler and the redistribution layer.
The embodiment of the invention realizes the stacking of the chips by using the chip connector and the one-stop WLP process without using the technology of vertically connecting the chips such as TSV and the like in the functional chips. Thus, the complexity and manufacturing cost of the three-dimensional multi-layer chip package is reduced.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present invention will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. Several embodiments of the invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Fig. 1 to 3 show schematic cross-sectional views of forming a package according to a first embodiment of the invention.
Fig. 4 to 5 show schematic cross-sectional views of forming a package according to a second embodiment of the invention.
Fig. 6 to 8 show schematic cross-sectional views of forming a package according to a third embodiment of the present invention.
Fig. 9 to 11 show schematic cross-sectional views of forming a package according to a fourth embodiment of the present invention.
Fig. 12 to 13 show schematic cross-sectional views of forming a package according to a fifth embodiment of the present invention.
Fig. 14 shows a flow chart of a method of forming a package according to an embodiment of the invention.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present invention may repeat reference numerals and/or characters in the various embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms, such as "below …," "below …," "lower," "above …," "upper," "above …," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component (or elements) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, herein, the term "assembly" refers to the implementation of circuit coupling between the various electronic devices. The term "chip" may refer to various types of chips, such as logic chips, storage chips, and the like.
Fig. 14 shows a flow chart of a method of forming a package according to an embodiment of the invention. The method comprises the following four steps:
step 100: the chip layer is placed on a carrier and assembled.
Step 200: and carrying out molding treatment on the chip layer.
Step 300: the carrier is removed to form a package main body, and a rewiring layer and bumps are added.
Step 400: the package main body is divided to form a package.
In some embodiments, the carrier is a high surface flatness component, and at least one chip layer may be stacked on the carrier. After the molding process is performed on the chip layer, a plastic package structure may be formed on the carrier. In some embodiments, the material used for the molding process may include solid or liquid molding materials starting from epoxy resins, organic polymers, or other compounds with or without silicon-based or glass fillers.
In some embodiments, the step of removing the carrier, the step of adding the rewiring layer and the bumps, and the step of dividing the package body are steps known in Wafer Level Packaging (WLP).
Various embodiments of the present invention will be described below based on the above-described method and with reference to various figures.
Fig. 1 to 3 show schematic cross-sectional views of forming a package according to a first embodiment of the invention.
As shown in fig. 1, two chip layers are placed on a carrier 10. The first chip layer includes a plurality of first chips 11 and a plurality of chip couplers 13. The second chip layer includes a plurality of second chips 12.
The first chip 11 and the chip connectors 13 may be first placed on the carrier 10 at intervals in the horizontal direction, and then the second chip 12 may be placed and assembled on the first chip 11 and the chip connectors 13. The chip includes a front side and a back side. In the art, a surface having, for example, bumps is considered a front surface. In some embodiments, the first chip 11 and the second chip 12 are placed face down.
Herein, a chip connector may be used to electrically couple different electronic devices, including, for example, various devices such as chips, redistribution layers, and other chip connectors; the electronic device to which the chip connector is coupled is typically not in the same chip layer as the chip connector. In some embodiments, the chip couplers may be made of a material such as glass or silicon. In some embodiments, the chip couplers may be active or passive coupling devices. For example, the chip coupler may have several through holes 18 in the vertical direction. The via 18 may be filled with a conductive dielectric. In some embodiments, conductive traces may be provided on both the upper and lower surfaces of the chip connector to electrically couple different vias on one surface.
Adhesive dots (adhesive dots) may also be provided between the different chip layers, such as adhesive dots 14 shown in fig. 1. The adhesive dots serve to separate and secure the different chip layers. In some embodiments, the adhesive dots are made of a non-conductive medium. In some embodiments, the description of the adhesive dots will be omitted.
Fig. 2 shows the structure of the package main body after steps 200 and 300 are performed.
As shown in fig. 2, two chip layers are molded, thereby forming a mold structure 15. After removing the carrier 10, a rewiring layer 16 may be added under the package body, and bumps 17 may be added under the rewiring layer 16.
Fig. 3 shows the structure of the package after performing step 400.
The package includes two segmented chip connectors, two second chips and a first chip. The two second chips can be electrically coupled to the first chip through the two divided chip couplers and the rewiring layer, respectively.
Fig. 4 to 5 show schematic cross-sectional views of forming a package according to a second embodiment of the invention. The second embodiment is a variation of the first embodiment.
Fig. 4 shows the structure of the package main body after steps 200 and 300 are performed. In the package main body, a plurality of first chips 21, a plurality of second chips 22, and a plurality of chip connectors 23 are included.
Fig. 5 shows the structure of the package after performing step 400.
The package includes a chip connector, a second chip, and a first chip. The second chip can be electrically coupled to the first chip through the chip coupler and the rewiring layer.
Fig. 6 to 8 show schematic cross-sectional views of forming a package according to a third embodiment of the present invention.
As shown in fig. 6, three chip layers are placed on the carrier 30. The first chip layer includes a plurality of first chips 31 and a plurality of first chip couplers 33. The second chip layer includes a plurality of second chips 32 and a plurality of second chip connectors 34. The third chip layer includes a plurality of third chips 35.
It is possible to first place the plurality of first chips 31 and the plurality of first chip connectors 33 on the carrier 10, then the plurality of second chips 32 and the plurality of second chip connectors 34 on the first chip 11 and the chip connectors 13 and finally the plurality of third chips 35 on the plurality of second chips 32 and the plurality of second chip connectors 34. In some embodiments, the first chip 31, the second chip 32, and the third chip 35 are placed face down.
In some embodiments, the package structure as shown in fig. 6 to 8 may comprise a plurality of second chip layers. Each of the plurality of second chip layers includes a plurality of second chips and a plurality of second chip couplers. A plurality of layers of second chip connectors may be stacked on the first chip connectors 33. In some embodiments, in the stack formed by the plurality of layers of the second chip couplers and the first chip coupler 33, the area of each layer of the chip couplers in the horizontal direction may not be completely the same. For example, in the stack formed by the plurality of layers of the second chip couplers and the first chip couplers 33, the area of the chip couplers in any one layer in the horizontal direction may be smaller or larger than the area of the chip couplers below the chip couplers in the horizontal direction.
Fig. 7 shows the structure of the package main body after steps 200 and 300 are performed.
As shown in fig. 7, three chip layers are molded to form a plastic encapsulated structure. After removing the carrier 30, a rewiring layer 36 may be added under the package body, and a bump 37 may be added under the rewiring layer 36.
Fig. 8 shows the structure of the package after performing step 400.
The package may include a segmented first chip coupler, a segmented second chip coupler, a third chip, a second chip, and a first chip. In some embodiments, the package may include a segmented first chip coupler, at least one segmented second chip coupler, a third chip, at least one second chip, and a first chip.
Since the conductive line may be provided on the surface of the divided first chip connector, the third chip may be electrically coupled to the at least one second chip through the at least one divided second chip connector, the divided first chip connector. The third chip may be further electrically coupled to the first chip through at least one of the divided second chip coupler, the divided first chip coupler, and the re-wiring layer. The at least one second chip may be electrically coupled to the first chip through the divided first chip connector and the re-wiring layer, or the at least one second chip may be electrically coupled to the first chip through the at least one divided second chip connector, the divided first chip connector and the re-wiring layer.
Fig. 9 to 11 show schematic cross-sectional views of forming a package according to a fourth embodiment of the present invention.
As shown in fig. 9, three chip layers are placed on the carrier 40. The first chip layer comprises a plurality of first chips 41, a plurality of first chip couplers 44, a plurality of cross-layer chip couplers 45, wherein the thickness of the cross-layer chip couplers 45 exceeds at least one chip layer. The second chip layer includes a plurality of second chips 42. The third chip layer includes a plurality of third chips 43. In some embodiments, the cross-layer chip connector may be a plurality of chip connectors stacked together, or may be an integrally formed chip connector. In some embodiments, in the case where a plurality of chip couplers are stacked together, the area of each of the chip couplers in the horizontal direction may be the same or different. In some embodiments, where the cross-layer chip couplers are integrally formed, the cross-layer chip couplers may have a stepped shape, a pyramidal shape, or other shapes.
First plurality of first chips 41, plurality of cross-layer chip couplers 45, and plurality of first chip couplers 44 may be first placed on carrier 40, then second plurality of chips 42 may be placed and assembled on first plurality of chips 41 and first plurality of chip couplers 44, and finally third plurality of chips 43 may be placed and assembled on second plurality of chips 42 and cross-layer chip couplers 45. In some embodiments, first chip 41, second chip 42, and third chip 43 are placed face down.
In some embodiments, the package structure as shown in fig. 9 to 11 may comprise a plurality of second chip layers. Each of the plurality of second chip layers includes a plurality of second chips and a plurality of second chip couplers. A plurality of layers of second chip connectors may be stacked on the first chip connectors 44. In some embodiments, the area of each layer of chip couplers in the horizontal direction may not be exactly the same in the stack formed by the layers of second chip couplers and first chip couplers 44. For example, in the stack formed by the plurality of layers of the second chip connectors and the first chip connectors 44, the area of the chip connectors in any one layer in the horizontal direction may be smaller or larger than the area of the chip connectors below the chip connectors in the horizontal direction.
Fig. 10 shows the structure of the package main body after steps 200 and 300 are performed.
As shown in fig. 10, three chip layers are molded to form a plastic encapsulated structure. After removing carrier 40, a redistribution layer 46 may be added under the package body, and bumps 47 may be added under redistribution layer 46.
Fig. 11 shows the structure of the package after performing step 400.
The package may include a segmented first chip coupler, a segmented cross-layer chip coupler, a third chip, a second chip, and a first chip. In some embodiments, the package may include a segmented first chip coupler, at least one segmented second chip coupler, a segmented cross-layer chip coupler, a third chip, at least one second chip, and a first chip.
The at least one second chip may be electrically coupled to the first chip through the divided first chip connector and the re-wiring layer, or the at least one second chip may be electrically coupled to the first chip through the at least one divided second chip connector, the divided first chip connector and the re-wiring layer. The third chip may be electrically coupled to the at least one second chip through the divided cross-layer chip connector, the re-wiring layer, the divided first chip connector, and the at least one divided second chip connector, or the third chip may be electrically coupled to the at least one second chip through the divided cross-layer chip connector, the re-wiring layer, and the divided first chip connector. The third chip may be electrically coupled to the first chip through the split cross-layer chip coupler and the rewiring layer.
Fig. 12 to 13 show schematic cross-sectional views of forming a package according to a fifth embodiment of the present invention. The fifth embodiment is a variation of the fourth embodiment.
Fig. 12 shows the structure of the package main body after steps 200 and 300 are performed.
As shown in fig. 12, the chip layer of the package main body is molded, thereby forming a mold structure. The package body includes three chip layers, a plurality of bumps 56, and a rewiring layer 57. The first chip layer includes a plurality of first chips 51, a plurality of first chip couplers 55, a plurality of cross-layer chip couplers 54, wherein the thickness of the cross-layer chip couplers 54 exceeds at least one chip layer. The second chip layer includes a plurality of second chips 52. The third chip layer includes a plurality of third chips 53. In some embodiments, in the case where a plurality of chip couplers are stacked together, the area of each of the chip couplers in the horizontal direction may be the same or different. In some embodiments, where the cross-layer chip couplers are integrally formed, the cross-layer chip couplers may have a stepped shape, a pyramidal shape, or other shapes.
First, the plurality of first chips 51, the plurality of cross-layer chip connectors 54, and the plurality of first chip connectors 55 may be placed on the carrier, then the plurality of second chips 52 may be placed and assembled on the plurality of first chips 51 and the plurality of first chip connectors 55, and finally the plurality of third chips 53 may be placed and assembled on the plurality of second chips 52 and the plurality of cross-layer chip connectors 54. In some embodiments, first chip 51, second chip 52, and third chip 53 are placed face down.
In some embodiments, the package structure as shown in fig. 12 to 13 may comprise a plurality of second chip layers. Each of the plurality of second chip layers includes a plurality of second chips and a plurality of second chip couplers. A plurality of layers of second chip connectors may be stacked on the first chip connectors 55. In some embodiments, the area of each layer of chip couplers in the horizontal direction may not be exactly the same in the stack formed by the layers of the second chip couplers and the first chip couplers 55. For example, in the stack formed by the plurality of layers of the second chip connectors and the first chip connectors 55, the area of the chip connectors in any one layer in the horizontal direction may be smaller or larger than the area of the chip connectors below the chip connectors in the horizontal direction.
Fig. 13 shows the structure of the package after performing step 400.
The package may include a first chip connector, a cross-layer chip connector, a third chip, a second chip, and a first chip. In some embodiments, the package may include a first chip coupler, at least one second chip coupler, a cross-layer chip coupler, a third chip, at least one second chip, and a first chip.
The at least one second chip may be electrically coupled to the first chip through the first chip coupler and the re-wiring layer, or the at least one second chip may be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler and the re-wiring layer. The third chip may be electrically coupled to the at least one second chip by the cross-layer chip connector, the rerouting layer, the first chip connector, and the at least one second chip connector, or the third chip may be electrically coupled to the at least one second chip by the cross-layer chip connector, the rerouting layer, and the first chip connector. The third chip may be electrically coupled to the first chip by a cross-layer chip coupler and a redistribution layer.
In various embodiments of the present invention, the individual chips may be coupled to various circuit structures outside the package using not only chip connectors and/or redistribution layers, but also chip connectors and/or redistribution layers and bumps.
As is well known to those skilled in the art, the bumps may be made of a conductive material or solder, including Cu, Ni, Au, Ag, etc., or other alloy materials, as well as other materials. In some embodiments, the bumps may have the form of pads, but may have other possible forms.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the various aspects of the present invention. Those skilled in the art should appreciate that they may readily use and devise other arrangements and structures that are designed to carry out the same purposes and/or achieve the same advantages of the embodiments described herein as a basis for the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (25)

1. A method of forming a package, the method comprising:
placing a first chip layer over a carrier, the first chip layer including a plurality of first chips facing down and a plurality of chip couplers between the plurality of first chips;
placing and assembling a second chip layer on the first chip layer, the second chip layer comprising a plurality of second chips facing down;
molding the first chip layer and the second chip layer over the carrier;
removing the carrier to form a packaging main body, and adding a rewiring layer and a bump below the packaging main body; and
dividing the package main body to form a plurality of the packages.
2. The method of claim 1, wherein the plurality of chip couplers are active or passive coupling devices.
3. The method of claim 1, wherein the plurality of chip couplers are arranged to include at least one through hole in a vertical direction.
4. The method of claim 1, wherein the package comprises a first chip, a second chip, and a singulated chip coupler, wherein the second chip is placed over the first chip and assembled over the singulated chip coupler, wherein the second chip is electrically coupleable to the first chip through the singulated chip coupler and the redistribution layer.
5. The method of claim 1, wherein the package comprises a first chip, a second chip, and a chip coupler, wherein the second chip is placed over the first chip and assembled over the chip coupler, wherein the second chip is electrically coupleable to the first chip through the chip coupler and the redistribution layer.
6. A method of forming a package, the method comprising:
placing a first chip layer over a carrier, the first chip layer including a plurality of first chip couplers and a first plurality of chips facing down;
placing and assembling at least one second chip layer over the first chip layer, each second chip layer comprising a plurality of second chips facing down and a plurality of second chip couplers;
placing and assembling a third chip layer on the at least one second chip layer, the third chip layer comprising a plurality of third chips facing down;
molding the first chip layer, the at least one second chip layer, and the third chip layer over the carrier;
removing the carrier to form a packaging main body, and adding a rewiring layer and a bump below the packaging main body; and
dividing the package main body to form a plurality of the packages.
7. The method of claim 6, wherein the plurality of first chip couplers are active or passive coupling devices and the plurality of second chip couplers are active or passive coupling devices.
8. The method of claim 6, wherein the plurality of first chip couplers and the plurality of second chip couplers are arranged to contain at least one through hole in a vertical direction.
9. The method of claim 6, wherein the package comprises a first chip, at least one second chip, a third chip, a segmented first chip coupler, and at least one segmented second chip coupler,
wherein the at least one segmented second chip coupler is assembled over the segmented first chip coupler, the at least one second chip is placed over the first chip, the third chip is placed over the at least one second chip,
wherein the third chip is electrically coupleable to the at least one second chip through the at least one segmented second chip coupler, the segmented first chip coupler,
the third chip can be electrically coupled to the first chip through the at least one divided second chip coupler, the divided first chip coupler, and the re-wiring layer, and
the at least one second chip can be electrically coupled to the first chip through the divided first chip coupler and the re-wiring layer, or the at least one second chip can be electrically coupled to the first chip through the at least one divided second chip coupler, the divided first chip coupler and the re-wiring layer.
10. The method of claim 6, wherein the package comprises a first chip, at least one second chip, a third chip, a first chip coupler, and at least one second chip coupler,
wherein the at least one second chip coupler is assembled over the first chip coupler, the at least one second chip is placed over the first chip, the third chip is placed over the at least one second chip,
wherein the third chip is electrically coupleable to the at least one second chip through the at least one second chip coupler, the first chip coupler,
the third chip can be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler, and the re-wiring layer, and
the at least one second chip can be electrically coupled to the first chip through the first chip coupler and the redistribution layer, or the at least one second chip can be electrically coupled to the first chip through the at least one second chip coupler, the first chip coupler, and the redistribution layer.
11. The method of claim 6, wherein a portion of the plurality of first chip couplers are integrally formed with at least one second chip coupler stacked thereon.
12. The method of claim 6, wherein a portion of the plurality of first chip couplers is the same area in a horizontal direction as at least one second chip coupler stacked thereon.
13. The method of claim 6, wherein a portion of the plurality of first chip couplers is different in area in a horizontal direction from at least one second chip coupler stacked thereon.
14. A package, comprising:
a rewiring layer including a first side and a second side;
a plurality of bumps disposed on a first side of the redistribution layer;
a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer;
a first chip connector and a second chip connector which are placed and assembled on the second side of the rewiring layer and are respectively placed and assembled horizontally on both sides of the first chip; and
a second chip and a third chip respectively including a front surface and a back surface, the second chip with the front surface facing downward being placed and assembled over the back surface of the first chip and the first chip coupler, the third chip with the front surface facing downward being placed and assembled over the back surface of the first chip and the second chip coupler,
wherein the package is molded into a plastic structure.
15. The package of claim 14, wherein the second chip is electrically coupled to the first chip by the first chip coupler and the redistribution layer, and the third chip is electrically coupled to the first chip by the second chip coupler and the redistribution layer.
16. The package of claim 14, wherein the first chip couplers are active or passive coupling devices and the second chip couplers are active or passive coupling devices.
17. The package of claim 14, wherein the first and second chip couplers are arranged to contain at least one through-hole in a vertical direction.
18. A package, comprising:
a rewiring layer including a first side and a second side;
a plurality of bumps disposed on a first side of the redistribution layer;
a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer;
a first chip connector placed and assembled on the second side of the rewiring layer and horizontally placed and assembled on a side surface of the first chip;
at least one second chip coupler placed and assembled over the first chip coupler;
at least one second chip comprising a front side and a back side, the at least one second chip being placed face down on the back side of the first chip and assembled over the first chip coupler; and
a third chip placed over the back side of the at least one second chip and assembled over the at least one second chip coupler,
wherein the package is molded into a plastic structure.
19. The package of claim 18, wherein the at least one second chip is electrically coupleable to the first chip by the first chip coupler and the redistribution layer or the at least one second chip is electrically coupleable to the first chip by the at least one second chip coupler, the first chip coupler, and the redistribution layer,
wherein the third chip is electrically coupleable to the at least one second chip by the at least one second chip coupler and the first chip coupler, or the third chip is electrically coupleable to the at least one second chip by the at least one second chip coupler,
wherein the third chip is electrically coupleable to the first chip through the at least one second chip coupler, the first chip coupler, and the redistribution layer.
20. The package of claim 18, wherein the first chip coupler is an active or passive coupling device and the at least one second chip coupler is an active or passive coupling device.
21. The package of claim 18, wherein the plurality of first chip couplers and the at least one second chip coupler are arranged to contain at least one through hole in a vertical direction.
22. A package, comprising:
a rewiring layer including a first side and a second side;
a plurality of bumps disposed on a first side of the redistribution layer;
a first chip including a front surface and a back surface, the front surface of the first chip being placed and assembled on the second side of the redistribution layer;
a first chip coupler placed and assembled on a second side of the rewiring layer, and horizontally placed and assembled on one side of the first chip;
a cross-layer chip connector placed and assembled on a second side of the redistribution layer, and horizontally placed and assembled on the other side of the first chip;
at least one second chip comprising a front side and a back side, the at least one second chip being placed face down over the back side of the first chip and assembled over the first chip coupler;
at least one second chip coupler placed and assembled over the first chip coupler; and
a third chip placed over the back side of the at least one second chip and assembled over the cross-layer chip coupler,
wherein the package is molded into a plastic structure.
23. The package of claim 22, wherein the at least one second chip is electrically coupleable to the first chip by the first chip coupler and the redistribution layer or the at least one second chip is electrically coupleable to the first chip by the at least one second chip coupler, the first chip coupler, and the redistribution layer,
wherein the third chip is electrically coupleable to the at least one second chip by the cross-layer chip coupler, the re-routing layer, the first chip coupler, and the at least one second chip coupler, or the third chip is electrically coupleable to the at least one second chip by the cross-layer chip coupler, the re-routing layer, and the first chip coupler,
wherein the third chip is electrically coupleable to the first chip through the cross-layer chip coupler and the redistribution layer.
24. The package of claim 22, wherein the first chip coupler is an active or passive coupling device, the cross-layer chip coupler is an active or passive coupling device, and the at least one second chip coupler is an active or passive coupling device.
25. The package of claim 22, wherein the plurality of first chip couplers, the cross-layer chip coupler, and the at least one second chip coupler are arranged to contain at least one through-hole in a vertical direction.
CN202011352636.4A 2020-11-27 2020-11-27 Package and method of forming a package Active CN112420529B (en)

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CN202011352636.4A CN112420529B (en) 2020-11-27 2020-11-27 Package and method of forming a package
KR1020210163984A KR102665954B1 (en) 2020-11-27 2021-11-25 A package and a method of forming the package
US17/535,984 US11973061B2 (en) 2020-11-27 2021-11-26 Chip package including stacked chips and chip couplers
TW110144187A TWI782803B (en) 2020-11-27 2021-11-26 Packaging piece and method of forming packaging piece
US17/535,987 US12087737B2 (en) 2020-11-27 2021-11-26 Method of forming chip package having stacked chips
US17/535,985 US20220173074A1 (en) 2020-11-27 2021-11-26 Chip Package and Method of Forming Chip Packages
KR1020230116745A KR102666026B1 (en) 2020-11-27 2023-09-04 A package and a method of forming the package
KR1020230116744A KR102666025B1 (en) 2020-11-27 2023-09-04 A package and a method of forming the package
KR1020230116743A KR102752941B1 (en) 2020-11-27 2023-09-04 A package and a method of forming the package
US18/413,020 US20240153918A1 (en) 2020-11-27 2024-01-15 Method of Forming Packages of Stacked Chips

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