CN112363766B - Content holding system, method and medium for ultra-low power consumption memory of integrated circuit - Google Patents
Content holding system, method and medium for ultra-low power consumption memory of integrated circuit Download PDFInfo
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Abstract
The invention discloses a content holding system, a method and a storage medium of an integrated circuit ultra-low power consumption memory, belonging to the integrated circuit design industry. The system comprises: power management module, CPU, data handling subsystem. The data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module. The data carrying controller is used for carrying the data in the main memory to the data compression and decompression module for compression after receiving the data carrying instruction sent by the CPU, and carrying the data decompressed by the data compression and decompression module to the main memory after being electrified. The data compression and decompression module is used for compressing data in the main memory conveyed by the data conveying controller and decompressing data in the nonvolatile memory. The application of the invention reduces the power consumption and improves the response speed on the premise of not losing data.
Description
Technical Field
The application relates to the technical field of integrated circuit design, in particular to a system, a method and a medium for maintaining the content of an ultra-low power consumption memory of an integrated circuit.
Background
In embedded systems, there is a very demanding requirement for low power consumption. In particular, for static power consumption during a system silence period, it is often desirable to have the static power consumption as close to 0 as possible, so that the standby time in a battery-powered state can be prolonged. At the same time, the demands on the application require that the system be able to respond to external signals and respond immediately.
One technique introduced in modern integrated circuit design is then: sleep. The technical requirement is that different parts of the integrated circuit chip are independently powered, and when the system enters a sleep state, the power supply of as many parts as possible in the system is completely cut off, so that the power consumption of the system in the sleep state is ensured to be very low, but the method sacrifices the response speed of the system.
On the premise of pursuing extremely low power consumption, the problem that data is lost after the main memory is powered off, and the power-down power consumption of the memory cannot be 0 by using the IP held by the memory is faced. And the content in the main memory is stored in the nonvolatile memory, so that the time is required for the content to be read from the nonvolatile memory to restore to the main memory after the content is awakened. In particular, the time to recover from memory can affect the response speed of the system. Such response speeds are often dictated by protocol or regulatory requirements and are not tolerant. In addition, insufficient response speed in some high real-time systems can lead to very serious disasters.
Disclosure of Invention
The content holding method of the memory with ultra-low power consumption of the integrated circuit solves the problems that data loss is caused after the main memory is powered off, the power consumption of the memory cannot be 0 by using the IP held by the memory, and the response speed is low.
In order to solve the problems, the invention adopts a technical scheme that: an integrated circuit ultra-low power memory content retention system is provided that includes a power management module, a CPU, and a data handling subsystem. The data handling subsystem includes a main memory, a non-volatile memory, a data handling controller, and a data compression and decompression module. The data carrying controller is used for carrying the data in the main memory to the data compression and decompression module for compression after receiving the data carrying instruction sent by the CPU; and after the power is on, the decompressed data of the data compression decompression module is transported to a main memory. The data compression and decompression module is used for compressing data in the main memory conveyed by the data conveying controller and decompressing the data in the read nonvolatile memory. The data handling controller is directly connected to the main memory and the data handling controller is directly connected to the non-volatile memory. After the CPU sends out the data carrying instruction, the integrated circuit only keeps the power supply of the data carrying subsystem, and after the data compressed by the data compression and decompression module is stored in the nonvolatile memory, the power supply of the data carrying subsystem is interrupted. After receiving the system recovery request, the power management module firstly turns on the power of the data handling subsystem, and after the data handling subsystem carries the data decompressed by the data compression decompression module to the main memory, turns on the power of other modules except the data handling subsystem in the integrated circuit. The data compression and decompression module compresses the data in the main memory carried by the data carrying controller and decompresses the data in the read nonvolatile memory, wherein the data compression and decompression module decompresses or compresses the data by using an LZ4 algorithm, and decompresses or compresses the data stream format after removing the data head and the sum check code by using a standard LZ4 data stream format.
The invention adopts another technical scheme that: an ultra-low power memory content retention method for an integrated circuit is provided. It comprises the following steps: a data reading step of carrying data in the main memory to a data compression and decompression module by a data carrying controller according to a data carrying instruction sent by the CPU, compressing the data in the main memory by the data compression and decompression module, and storing the compressed data in a nonvolatile memory; and a data writing step of reading the data in the nonvolatile memory to a data compression and decompression module according to a recovery request of the system, decompressing the data in the nonvolatile memory by using the data compression and decompression module, and carrying the decompressed data to the main memory by using a data carrying controller.
In another aspect of the application, a computer readable storage medium is provided having computer instructions stored therein, wherein the computer instructions are operative to perform a method of content retention for an integrated circuit ultra low power memory in the aspects.
The technical scheme of the application has the following beneficial effects: the computer system reduces the power consumption on the premise of not losing data when entering a sleep or wake-up state, improves the response speed of the system, reduces the wake-up delay of the system, does not damage the efficient compression, and meets the application requirement of strict time requirements.
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FIG. 1 is a schematic diagram of an embodiment of an ultra low power memory content retention system for an integrated circuit according to the present invention;
FIG. 2 is a schematic diagram of an embodiment of the data compression decompression module according to the present invention using the LZ4 algorithm;
FIG. 3 is a schematic diagram of an embodiment of a method for maintaining content of an ultra low power memory of an integrated circuit according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making clear and defining the scope of the present invention.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
With the rapid development of computer systems, the requirement for low power consumption is increasing, and it is desirable that the static power consumption be as close to 0 as possible. Therefore, the standby time in the battery power supply state can be prolonged, and the application requirements require that the system can respond to external signals and immediately respond. And the computer system has the problem of data loss after main power failure and slow response speed when a large amount of data is read and written.
FIG. 1 is a schematic diagram of an embodiment of an ultra low power memory content retention system for an integrated circuit according to the present invention.
In this embodiment, an integrated circuit ultra low power memory content retention system includes: power management module, CPU, data handling subsystem. Further comprises:
the data handling subsystem comprises a main memory, a nonvolatile memory, a data handling controller and a data compression and decompression module.
The data carrying controller is used for carrying the data in the main memory to the data compression and decompression module for compression after receiving the data carrying instruction sent by the CPU; and after the power is on, the decompressed data of the data compression decompression module is transported to a main memory.
The data compression and decompression module is used for compressing the data in the main memory conveyed by the data conveying controller and decompressing the data in the read nonvolatile memory.
In one embodiment of the present invention, the data handling subsystem includes a main memory RAM, a non-volatile memory FLASH, a data handling controller, a data compression decompression module, a memory controller, a bus controller, and the like when performing integrated circuit design. The memory controller converts the read, write, etc. commands issued by the memory device into identifiable signals, and the bus controller manages the use of the bus.
In one embodiment of the invention, the data-handling controller is directly connected to the main memory RAM, and the data-handling controller is directly connected to the nonvolatile memory FLASH. The middle does not pass through other logic modules except the data compression and decompression module, so that the data handling controller has the capability of reading 4 bytes per clock cycle. The non-bus type circuit avoids the risk of bus waiting delay, so that the read channel of the RAM of the main memory reaches the theoretical limit bandwidth, the carrying speed is improved, and the working time is shortened. The data carrying controller is directly connected with the nonvolatile memory, so that only the data carrying controller carries out data carrying work between the main memory RAM and the nonvolatile memory, and therefore, the data compression and decompression module can complete reading/writing of the main memory RAM within 1 clock cycle, and no extra cache circuit is needed.
In a specific embodiment of the present invention, the data compression and decompression module performs data compression and decompression by using the LZ4 algorithm, where the LZ4 algorithm focuses on the compression and decompression speed, and performs matching search and encoding with a minimum number of steps, so as to increase the data stream bandwidth as much as possible, and because the algorithm is implemented inside the chip, the standard LZ4 data stream format is used to remove the data header and the data stream format after the sum check code for data decompression or compression.
In one specific embodiment of the invention, the non-volatile memory FLASH has the capability of 4-wire parallel operation. If the time consumed for the preparation operation is not taken into consideration, in the prior art, at most 4 bits of data can be read/written for one cycle of the nonvolatile memory FLASH, that is, data obtained from the main memory RAM with one cycle requires at least 8 clock cycles to be written into the nonvolatile memory FLASH, and vice versa. Roughly estimating the amount of 8KB of data requires 250us to operate at a clock frequency of 64 MHz. A large amount of power in this 250us time is consumed in the operation of the non-volatile memory FLASH, whose operating speed is determined by the process architecture and cannot be changed in most scenarios. Therefore, the data volume required to be read and written through the nonvolatile memory FLASH is reduced through data compression, the whole process is accelerated, and the purpose of saving power consumption is achieved.
In a specific embodiment of the present invention, before the computer goes to sleep, after the data handling controller receives the data handling instruction sent by the CPU, the power management module interrupts the power supply of other parts of the computer system except the data handling subsystem, the data handling controller starts to work, the data handling controller compresses the data stored in the RAM of the main memory that is handled by the data handling controller through the LZ4 algorithm, and after the compression, a compressed packet is obtained and written into the FLASH of the nonvolatile memory, after all the data stored in the RAM of the main memory is handled and stored into the FLASH of the nonvolatile memory, the data compression work is completed, at this time, the data handling subsystem is powered down, and the computer goes to sleep. This process facilitates the computer to go to sleep without causing data loss.
In a specific embodiment of the present invention, when a computer needs to wake up, after a power management module receives a system restoration request triggered by an integrated circuit or an external signal, a power supply of a data handling subsystem is turned on first, a data compression and decompression module decompresses data stored in a read nonvolatile memory FLASH through an algorithm to obtain source data before compression, the source data transfers the data stored in the decompressed nonvolatile memory FLASH to a main memory RAM through a data handling controller, all the data stored in the nonvolatile memory FLASH are transferred and stored to the main memory RAM, the data decompression work is completed, and at this time, other subsystems such as a CPU of the computer are powered on, so that the computer wakes up to enter a working state. This process facilitates the rapid recovery of data after the computer wakes up.
FIG. 2 is a schematic diagram of an embodiment of the data compression decompression module employing LZ4 algorithm according to the present invention
In this particular embodiment, the data compression decompression module performs data compression decompression using an LZ4 algorithm. When two RAMs are arranged in the integrated circuit, double of the RAM bandwidth can be directly obtained, the RAM0 mainly stores source data, the rest of space is used for buffering, the RAM1 is used for storing hash tables of LZ4 algorithm matching characters and distances, and the LZ4 algorithm searches matching character strings by calculating the hash tables. The hash table uses the structure of (Key, value) to represent the mapping relationship. Key is a 4 byte binary number. Value is 4 bytes to indicate the location of the data in the data block.
In this particular embodiment, the data block format of the LZ4 algorithm includes: a token of 1 byte, a character string length identifier of 0-N bytes, an uncompressed character string of 0-M bytes, an offset of 2 bytes and a matching length of 0-Z bytes. The LZ4 algorithm uses a sliding window and a read-ahead buffer to achieve data compression decompression. The read-ahead buffer is used to hold the first 4 bytes of current input data, i.e. 32bits, just as wide as one RAM read. Then, after hash calculation is performed on the 4 bytes, it is determined whether the current byte has occurred in the sliding window. If it appears in the sliding window, a match can be made. The sliding window search then continues backwards. The distance between the current byte and the byte appearing before is used to represent the actual data after the whole sliding is finished, thereby realizing the compression of the data. The data volume after the LZ4 algorithm is compressed is generally about 1/2-1/3 of the original data volume, and the sleeping/recovering time of the whole system can be shortened to be less than 150 us.
In this particular embodiment, the width of the sliding window in the LZ4 algorithm is variable. The longer the window, the higher the average compression ratio. Typically this window length may be 20 bytes or tens of KB. Longer windows require increased time required to traverse the sliding window. The memory space required by the hash table is also increased, and the probability of hash collisions occurring is also increased. The width of the sliding window is thus selected to be 8KB, which is the minimum amount of data to be saved, and compression can be completed with one sliding at the minimum data.
In this particular embodiment, the hash algorithm needs to specify the size of the data block for the hash calculation first. I.e. data is compressed in pages. Page size is typically 4 KB-32 KB. Therefore, 8KB as large as a sliding window can be directly used as an operation object of a single page. After the hash calculation is completed, the information such as the matching distance needs to be calculated, and then the information is packaged and stored in a nonvolatile memory FLASH.
In this embodiment, when decompression is performed, since the data stored in the nonvolatile memory FLASH is continuous stream information, the data amount of not more than 8KB is read at a time first and stored in the RAM buffer, and then decompression is started. And one part of data blocks in the data are non-repeated data, and are directly copied into the RAM of the original data recovery area, and the other part of the data are repeated data, so that an uncompressed data segment can be quickly found out through the distance, and then copied into the RAM of the original data recovery area, and the decompression is completed. The LZ4 algorithm has low operation amount required by decompression, so that the bottleneck of the whole system cannot occur in the process of data decompression.
In this particular embodiment, the hash table need not be handled. It is dynamically generated and eliminated, stored in RAM and discarded after use.
FIG. 3 is a schematic diagram of an embodiment of a method for maintaining content of an ultra low power memory of an integrated circuit according to the present invention.
In this embodiment, the method for maintaining the content of the memory with ultra-low power consumption of the integrated circuit mainly comprises: an ultra-low power memory content retention method for an integrated circuit is provided. It comprises the following steps: before the computer goes to sleep, the data carrying controller receives the data carrying instruction sent by the CPU, carries the data in the main memory to the data compression and decompression module for compression, and writes the data in the compressed main memory into the nonvolatile memory. And in the data writing step, when the computer needs to wake up, after the power management module receives a system recovery request triggered by the integrated circuit or an external signal, the data compression and decompression module decompresses the data in the nonvolatile memory by reading the data in the nonvolatile memory, and the decompressed data in the nonvolatile memory is transported to the main memory through the data transport controller.
In a specific embodiment of the present application, the method for maintaining the content of the memory with ultra-low power consumption of the integrated circuit of the present application includes a process S101, a data reading step, including: before the computer goes to sleep, after the data handling controller receives the data handling instruction sent by the CPU, the power management module interrupts the power supply of other parts of the computer system except the data handling subsystem. The data handling controller carries data in the main memory to a data compression and decompression module for compression, the data compression and decompression module adopts an LZ4 algorithm for compression, the LZ4 algorithm compresses data in the RAM of the main memory through matching characters and distances, and the compressed data in the main memory is written into the nonvolatile memory. Since the data compression and decompression module can complete the read/write of the main memory within 1 clock cycle, no additional cache circuit is required. In a purely hardware integrated circuit design, the CPU of the chip has been powered down before going to sleep, and the main memory RAM of the chip is actually freed up in large amounts. There is thus a large amount of memory space to provide data space for lossless data compression/decompression algorithms to store the dictionary required for data compression/decompression. This process facilitates the computer to go to sleep without causing data loss.
In a specific embodiment of the present application, the method for maintaining the content of the memory with ultra-low power consumption of the integrated circuit of the present application includes a process S102, a data reading step, including: when the computer needs to wake up, after the power management module receives a system recovery request triggered by an integrated circuit or an external signal, the data compression decompression module decompresses the data in the nonvolatile memory by reading the data in the nonvolatile memory, and at the moment, the data in the nonvolatile memory, namely the compressed package, is very low in operation amount required by the LZ4 algorithm decompression, so that the bottleneck of the whole system cannot occur in the process of data decompression. The LZ4 algorithm decompresses the data in the nonvolatile memory FLASH through the matched characters and the distances, wherein one part of the data blocks are non-repeated data and are directly copied into the original data recovery area RAM, the other part of the data blocks are repeated data, uncompressed data segments can be quickly found through the distances and then copied into the original data recovery area RAM, and the decompressed data in the nonvolatile memory FLASH are transported to the main memory RAM through the data transport controller. This process facilitates the rapid recovery of data after the computer wakes up.
The content holding system of the integrated circuit ultra-low power consumption memory provided by the invention can be used for executing the content holding method of the integrated circuit ultra-low power consumption memory described in any embodiment, and the implementation principle and the technical effect are similar and are not repeated here.
In another embodiment of the invention, a computer readable storage medium storing computer instructions is characterized in that the computer instructions are operative to perform the integrated circuit ultra low power memory content retention method described in any of the embodiments.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the present invention and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present invention.
Claims (8)
1. An integrated circuit ultra-low power consumption memory content holding system comprises a power management module, a CPU and a data handling subsystem, and is characterized in that,
The data carrying subsystem comprises a main memory, a nonvolatile memory, a data carrying controller and a data compression and decompression module;
The data carrying controller is used for reading the data in the main memory by adopting a non-bus circuit after receiving the data carrying instruction sent by the CPU, and carrying the read data to the data compression and decompression module for compression; and after being electrified, the data decompressed by the data compression and decompression module is transported to the main memory, wherein,
After the CPU issues a data-handling instruction, the integrated circuit only retains power to the data-handling subsystem,
After the data handling subsystem carries the data decompressed by the data compression and decompression module to the main memory, other module power supplies except the data handling subsystem in the integrated circuit are turned on;
The data compression and decompression module is used for compressing the data in the main memory and decompressing the data in the nonvolatile memory, which are carried by the data carrying controller.
2. The integrated circuit ultra low power consumption memory content holding system according to claim 1, wherein after storing all of the data compressed by the data compression decompression module in the nonvolatile memory, power supply to the data handling subsystem is interrupted.
3. The integrated circuit ultra low power consumption memory content retention system according to claim 1, wherein the data handling controller is directly connected to the main memory and the data handling controller is directly connected to the non-volatile memory.
4. The integrated circuit ultra low power consumption memory content retention system according to claim 1, wherein the power management module first turns on the power to the data handling subsystem after receiving a system resume request.
5. The system of claim 1, wherein the data compression and decompression module compresses data in the main memory and decompresses data in the read nonvolatile memory carried by the data carrying controller, including decompressing or compressing according to LZ4 algorithm.
6. The system of claim 5, wherein the step of decompressing or compressing the memory contents according to the LZ4 algorithm comprises,
The standard LZ4 data stream format is used to remove the header and the data stream format after the checksum for decompression or compression.
7. A content holding method for an ultra-low power memory of an integrated circuit is characterized by comprising the steps of,
The data carrying subsystem comprises a main memory, a nonvolatile memory, a data carrying controller and a data compression and decompression module;
A data reading step of reading data in the main memory by using a non-bus circuit according to a data transfer instruction sent by a CPU, transferring the read data to the data compression and decompression module, compressing the data in the main memory by using the data compression and decompression module, storing the compressed data in the nonvolatile memory,
After the CPU issues a data-handling instruction, the integrated circuit only retains power to the data-handling subsystem,
After the data handling subsystem carries the data decompressed by the data compression and decompression module to the main memory, other module power supplies except the data handling subsystem in the integrated circuit are turned on; and
And a data writing step, namely reading the data in the nonvolatile memory to the data compression and decompression module according to a recovery request of the system, decompressing the data in the nonvolatile memory by using the data compression and decompression module, and carrying the decompressed data into the main memory by using the data carrying controller.
8. A computer readable storage medium storing computer instructions operable to perform the integrated circuit ultra low power memory content retention method of claim 7.
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| US6243831B1 (en) * | 1998-10-31 | 2001-06-05 | Compaq Computer Corporation | Computer system with power loss protection mechanism |
| CN1177279C (en) * | 2002-10-21 | 2004-11-24 | 威盛电子股份有限公司 | DRAM data maintaining method and relative device |
| US8645738B2 (en) * | 2009-10-27 | 2014-02-04 | Nokia Corporation | Nonvolatile device |
| US20110296095A1 (en) * | 2010-05-25 | 2011-12-01 | Mediatek Inc. | Data movement engine and memory control methods thereof |
| DE112011105700T5 (en) * | 2011-10-01 | 2014-07-17 | Intel Corporation | Quick Sleep and Quick Recovery for a platform of computer system |
| CN103064503B (en) * | 2012-12-24 | 2016-03-09 | 上海新储集成电路有限公司 | SOC (system on a chip) and buffer thereof |
| CN105094827B (en) * | 2015-07-24 | 2018-08-28 | 上海新储集成电路有限公司 | A kind of method that processor starts |
| CN106484074B (en) * | 2016-09-30 | 2019-09-10 | 邦彦技术股份有限公司 | Nonvolatile memory device, nonvolatile memory method, computer system, and method for implementing standby or hibernation |
| CN110096460A (en) * | 2018-01-30 | 2019-08-06 | 北京京东尚科信息技术有限公司 | The method, apparatus and circuit of internal storage data protection |
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