CN112345924B

CN112345924B - Scan chain control circuit

Info

Publication number: CN112345924B
Application number: CN202011188517.XA
Authority: CN
Inventors: 孙腾达; 俞日龙
Original assignee: Shanghai Zhaoxin Semiconductor Co Ltd
Current assignee: Shanghai Zhaoxin Semiconductor Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2024-09-03
Anticipated expiration: 2040-10-30
Also published as: CN112345924A

Abstract

The invention provides a scan chain control circuit, comprising: the chip test is carried out through the interface on the test circuit board without carrying out the test through the external lead of the lead end, when the scanning chain control circuit is under the action of the pin shift clock, the scanning chain control circuit inputs the pin input data to the scanning chain test circuit and outputs the test data after the test is carried out; when the scan chain control circuit is under the action of the register shift clock signal, the scan chain control circuit inputs the register input data to the scan chain test circuit for testing and outputs the tested test data. The invention can realize the test data input/output control of the scan chain test circuit, and can also test whether the chip can operate correctly when the test pins are not easy to expose or contact poorly besides improving the test flexibility.

Description

Scan chain control circuit

Technical Field

The present invention relates to integrated circuit testing circuits, and more particularly to a control circuit for a scan chain testing circuit of an integrated circuit chip.

Background

With the continuous development of large-scale integrated circuit chip technology, the chip integration level is higher and higher; with this, the difficulty of chip testing is increasing. The scan chain test circuit has the advantages of high reliability, accurate test and the like, is widely applied to integrated circuit chip test, and becomes an essential component in modern chip design. However, the scan chain test circuit has a plurality of test pins, and the existing test method needs external leads when testing, so that the test difficulty is high. Especially when the chip is packaged on the printed circuit board, the test pins are not easy to be completely exposed or the contact of the test pins is poor due to the chip packaging, and the like, so that the test difficulty is increased.

Disclosure of Invention

The present invention provides a scan chain control circuit, and more particularly, to a scan chain control circuit integrating pins of a scan chain test circuit. Under the condition that the test pins are not exposed after the chip is packaged, the data input/output control of the scan chain test circuit can be realized, and the test flexibility is improved.

In a preferred embodiment, the present invention provides a scan chain control circuit comprising: the chip test is carried out through the interface on the test circuit board without carrying out the test through the external lead of the lead end, when the scanning chain control circuit is under the action of the pin shift clock, the scanning chain control circuit inputs the pin input data to the scanning chain test circuit and outputs the test data after the test is carried out; when the scan chain control circuit is under the action of the register shift clock signal, the scan chain control circuit inputs the register input data to the scan chain test circuit for testing and outputs the tested test data.

In some embodiments, the scan chain control circuit described above can be applied to a joint test workgroup (Joint Test Action Group, JTAG) Debug interface and/or a serial line Debug (SERIAL WIRE Debug, SWD) interface.

In some embodiments, the input pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit.

In some embodiments, the pin input data is uniformly transferred from the scan chain test circuit pin to the scan chain control circuit and then transferred to the scan chain test circuit.

In some embodiments, the scan chain control circuit is capable of generating the register input data by the scan chain control circuit and transmitting the register input data to the scan chain test circuit.

In some embodiments, the output pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit.

In some embodiments, the test data after the pin input data test transmitted from the scan chain test circuit pins is uniformly transmitted to the scan chain control circuit and output through an interface on the test circuit board.

In some embodiments, the test data generated by the scan chain control circuit and tested by the register input data is transmitted to the scan chain control circuit and output via an interface on the test circuit board.

In some embodiments, the scan chain control circuit outputs test data after testing the pin input data transmitted by the scan chain test circuit pins under the action of a pin shift clock.

In some embodiments, when the scan chain control circuit operates in the original test mode, the scan chain control circuit outputs test data after testing the pin input data transmitted by the scan chain test circuit pins under the action of a pin shift clock.

In some embodiments, the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under the action of a register shift clock.

In some embodiments, when the scan chain control circuit operates in the scan mode, the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under the action of a register shift clock.

In some embodiments, when the scan chain control circuit operates in the original test mode, the scan chain control circuit can be switched to the scan mode by a reset operation and restarting.

In some embodiments, when the scan chain control circuit operates in the scan mode, the scan chain control circuit can be switched to the original test mode by a reset operation and restarting.

Drawings

Fig. 1 is a basic schematic diagram of a scan chain test circuit according to the present invention.

Fig. 2 is a schematic diagram of a scan chain control circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a data selector according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a clock controller according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a mode controller according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a scan chain control circuit clock signal according to an embodiment of the invention.

FIG. 7 is a flow chart of a scan chain control circuit according to an embodiment of the invention.

Fig. 8 is a schematic diagram of a scan chain test circuit packaged on a PCB according to an embodiment of the invention.

Wherein the symbols in the drawings are briefly described as follows:

100-scan chain test circuit; 200-scan chain control circuit; 202 to external equipment; 204 to a register controller; 206-data selector; 208 to a clock controller; 210 to a mode controller; 212. 212-1, 212-2, 212-3, 212-4 to scan chain test circuits; 214-register clock control module; 216 to a register mode control module; 400. 402, 406, 408, 500, 502-D flip-flops; 404. 410-gating clock circuit; 412 to a clock oscillator (Phase Locked Loop, PLL); 414 to a first data selector; 416 to second data selector; 504 to a third data selector; 506 to fourth data selectors; reg_scan_in [ n:0] to register input data; reg_scan_out [ n:0] to the register output data; SCAN_IN [ n:0] -input data; SCAN_EN-enable clock signals; ip_clk to shift clock; DFT_ON-mode test clock signals; SE-mode scan enable clock signal; SCAN_OUT [ n:0] -output data; IC1, IC 2-integrated design circuit to be tested; DFF-D flip-flops; input_0 and input_1 … input_n to Input pins; output_0, output_1 … output_n to Output pins; the SI_0 and the SI_1 … SI_n are respectively input into the scan chain test circuits; TCK-test clock signal; shift_clk to register Shift clock signals; ext_clk to pin shift clocks; PLL-clock oscillator; ICG-gating clock circuit; func_clk to a functional clock signal; scan_mode_dp-mode test backup clock signal; scan_en_dp to mode Scan enable back-up clock signal; SE_i-the mode scan enable clock signal originally controlling the scan chain test circuit; DFT_ON_i-test mode clock signals originally controlling the scan chain test circuit; test_mode to Test mode signal; t1-a first period of time; t2-second time period; t3 to a third period; t4 to a fourth period; t5 to a fifth period; s702, S704, S706, S708, S710 to flow steps.

Detailed Description

The following detailed description of the invention refers to the accompanying drawings, which illustrate specific embodiments of the invention.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "coupled" as used herein includes any direct or indirect electrical connection. Accordingly, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Certain terms are used throughout the description and claims to refer to particular components and assemblies. Those of skill in the art will appreciate that a hardware manufacturer may refer to the same components and elements by different names. The specification and claims do not identify differences in names, but rather differences in functions of the components and the members.

Fig. 1 is a basic schematic diagram of a scan chain test circuit according to the present invention. IN chip design, the chip test circuit may include a plurality of SCAN chain test circuits (as shown IN fig. 1, the SCAN chain test circuits may be a plurality of SCAN chain test circuits having input pins si_0, si_1, si_2, si_ … si_n and output pins so_0, so_1, so_2, so_ … so_n) as shown IN fig. 1, and each SCAN chain test circuit is coupled to a respective input/output pin (PAD pin) and inputs data to be tested (scan_in [ N:0 ]) or outputs test data (scan_out [ N:0 ]) under the action of a shift clock (ip_clk) for a designer to analyze the chip design.

However, when the chip is packaged on the PCB board, the input/output pins (PAD pins) of the chip design may not be exposed due to package coverage or may have poor contact due to the package. Finally, inconvenient testing or inaccurate testing data can be caused, chip design can not be well analyzed, and testing cost and difficulty are increased. When a chip is packaged on a PCB board, in particular, the following conditions may occur, which may lead to inaccurate testing. Firstly, the input pins of the scan chain test circuit of si_1 are not exposed due to packaging (as shown in fig. 1, drawing an "X" on the PAD pins indicates that the pins are not exposed), so that the tester cannot perform subsequent testing by externally connecting leads from the circuit board. Second, the output pins of the scan chain test circuit of si_2 may not be exposed (as shown in fig. 1), which may also cause the tester to fail to perform subsequent testing from the external leads on the circuit board. Further, even if the pins are exposed, the pins may be in poor contact (as shown in fig. 1, the pins are drawn on PAD pins to indicate poor contact), which may result in inaccurate testing and poor chip design analysis. Furthermore, the three conditions can occur simultaneously, so that the test data is inaccurate, and the test cost and the test difficulty are increased.

Accordingly, fig. 2 is a schematic diagram of a scan chain control circuit according to an embodiment of the present invention. The scan chain control circuit 200 can be applied to the scan chain test circuit 212 for controlling the integrated circuit chip, so as to realize the data input/output control of the scan chain test circuit and improve the test flexibility. As shown in fig. 2, the scan chain control circuit 200 includes: a register controller 204, a data selector 206, a clock controller 208, and a mode controller 210; the register controller 204 also includes a register clock control module 214 and a register mode control module 216. The clock controller 208 is coupled to the register controller 204 and the mode controller 210, receives an enable clock signal (scan_en) and a register Shift clock signal (shift_clk) output from the register controller 204, receives a mode SCAN enable clock Signal (SE) output from the mode controller 210, and outputs a Shift clock signal (ip_clk); The mode controller 210 is coupled to the register controller 204, receives the enable clock signal (scan_en), and outputs a mode test clock signal (dft_on) and the mode SCAN enable clock Signal (SE); a data selector 206 coupled to the scan chain test circuit 212 and the register controller 204; when the enable clock signal received by the data selector 206 is at the first level, the data selector 206 selects a register input data (reg_scan_in [ n:0 ]) as an input data (scan_in [ n:0 ]) to be input to the SCAN chain test circuit 212; When the enable clock signal received by the data selector 206 is at the second level, the data selector 206 selects a pin input data (SI_0, SI_1 … SI_n) as the input data (SCAN_IN [ n:0 ]) to be input to the SCAN chain test circuit 212. Here, the mode test clock signal (dft_on) and the mode SCAN enable clock Signal (SE) outputted from the mode controller 210 are output signals for controlling the output data of the input data (scan_in [ n:0 ]) after the input data is tested by the SCAN chain test circuit 212. In some embodiments, as partially shown in fig. 6, the test mode clock signal (dft_on) is pulled up to a high level signal by the mode controller 210 after receiving the test clock signal TCK signal (generated by the external device 202 in the test state) for 3 clock signals, and the mode scan enable clock Signal (SE) is pulled up to a high level signal by the mode controller 210 after receiving the TCK signal for 4 clock signals, or the test mode clock signal (dft_on) and the mode scan enable clock Signal (SE) are pulled up to a high level signal by the mode controller 210 after a plurality of clock cycles of the TCK signal and the test mode clock signal (dft_on) is pulled up to a high level signal before the mode scan enable clock Signal (SE). It should be noted that, the test mode clock signal (dft_on) is pulled up to a high level signal 1 clock period before the mode scan enable clock Signal (SE), and those skilled in the art can configure the test mode clock signal (dft_on) according to the actual needs, and the invention is not limited thereto.

The test mode clock signal (DFT_ON) and a mode SCAN enable clock Signal (SE) are pulled high to indicate that the output data (SCAN_OUT [ n:0] shown in FIG. 2) after being tested by the SCAN chain test circuit 212 can be output to the SCAN chain control circuit 200 shown in FIG. 2 and finally output to the external device for analysis by the designer. It should be noted that the test mode clock signal (DFT_ON) and a mode SCAN enable clock Signal (SE) are used to control the output of the test output data (SCAN_OUT [ n:0] shown in FIG. 2).

In some embodiments, a mode scan enable clock signal (SE_i) and a mode test clock signal (DFT_i) of an original control scan chain test circuit are similar to the pull-up principle of the test mode clock signal (DFT_ON) and the mode scan enable clock Signal (SE). The mode scan enable clock signal (se_i) and the mode test clock signal (dft_i) of the original control scan chain test circuit may be raised to a high level signal after receiving the TCK signal and the mode test clock signal (dft_i) is raised to a high level signal before the mode scan enable clock signal (se_i) of the original control scan chain test circuit. It should be noted here that the mode test clock signal (dft_i) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock signal (se_i) of the original control scan chain test circuit. Those skilled in the art can configure the related mode signal control module of the original scan chain test circuit according to the product requirement, and the invention is not limited thereto. For the description of this part, please refer to fig. 5, and the description thereof is omitted.

As shown in FIG. 2, the scan chain test circuit 212 is an integrated circuit chip test circuit, and includes n+1 (n is equal to or greater than 0 and is an integer) scan chains, and test data is Input via an Input pin (Input Pad) and output via an output pin. The single scan chain test circuit may comprise: an Input pin (e.g., input_0, input_1, …, input_n), a plurality of serially connected flip-flops (e.g., may be D-type flip-flops (D TYPE FLIP-flop, DFF)), an Output pin (e.g., output_0, output_1, …, output_n), or any other type of integrated circuit chip scan chain test circuit, without limitation.

It should be noted that, as shown in fig. 2, the Input pins (e.g., input_0, input_1, …, input_n) of the scan chain test circuit 212 can be respectively coupled to the plurality of Input terminals of the data selector 206, and the data selector 206 can control the scan chain test circuit 212 to transmit the test data (see fig. 3 for details, which are not repeated herein). Therefore, when the chip is packaged on the printed circuit board, even if the Input pins (for example, input_0, input_1, …, input_n) of the scan chain test circuit 212 are in poor contact due to coverage or soldering, the related signals can still be transmitted to the scan chain control circuit 200 through the wiring on the test circuit board, so that the scan chain control circuit 200 can be used to transmit test data to the scan chain test circuit to realize test requirements, thereby avoiding adverse factors of test and greatly improving test efficiency.

It should be noted that, the data selector 206 may also receive the register input data (reg_scan_in [ n:0 ]) transmitted by the register controller 204, and input the register input data (reg_scan_in [ n:0 ]) transmitted by the register controller 204 to the scan chain test circuit 212 under the action of the control signal (see fig. 3 for details, which are not repeated herein). Alternatively, when the scan chain test pins of the chip package to the printed circuit board are covered or in bad contact, the register input data (reg_scan_in [ n:0 ]) may still be used to input test data to the scan chain test circuit 212 for testing. Furthermore, the n+1bits register input data (reg_scan_in [ n:0 ]) can be a high-low level signal to achieve the correspondence between the register input data (reg_scan_in [ n:0 ]) and the scan chain test circuit (the contents of which are described with reference to fig. 3 and are not repeated herein), so that the test is more flexible.

It should be further noted that the Input pins (e.g., input_0, input_1, …, input_n) of the scan chain test circuit 212 shown in fig. 2 may also be connected to the corresponding scan chain test circuit. Those skilled in the art can also realize the test requirements by using artificial external leads directly in the case that the Input pins (e.g., input_0, input_1, …, input_n) of the scan chain test circuit 212 are exposed. For simplicity of drawing, fig. 2 does not show all connection relationships, but a person skilled in the art can configure the connection relationships according to actual needs, and the invention is not limited thereto.

The input mode of the test data described in the above embodiment greatly eliminates uncertain factors of the test on the basis of meeting the original test requirements, improves the accuracy and flexibility of the test, reduces the test difficulty of the testers, improves the test efficiency, and has a certain technical effect.

The data selector 206 inputs test data (SCAN_IN [ n:0 ]) to the SCAN chain test circuit 212; under the action of the shift clock signal (IP_CLK), the mode test clock signal (DFT_ON) and the mode SCAN enable clock Signal (SE), the test data (SCAN_IN [ n:0 ]) is shifted IN the SCAN chain test circuit for scanning, and the test data (SCAN_OUT [ n:0 ]) is Output to the register controller 204 via an Output pin (Output Pad), and the register controller 204 records the test data and integrates (Reg_scan_out [ n:0 ]) for outputting to the external device 202. More details about the shift clock signal (ip_clk), the mode test clock signal (dft_on) and the mode scan enable clock Signal (SE) will be described in detail in fig. 4 and 5, and will not be repeated here.

Regarding the output test data (scan_out [ n:0 ]), it should be noted that: the shift clock signal (IP_CLK) controls the shift of the input test data (SCAN_IN [ n ] 0 ]) among a plurality of serially connected flip-flops (e.g., which may be D-flip-flops (DFFs)) of the SCAN chain test circuit 212 for scanning. The mode test clock signal (DFT_ON) and the mode SCAN enable clock Signal (SE) control the input test data (SCAN_IN [ n:0 ]) to be output after being tested by the SCAN chain test circuit 212. For related technical details of the mode test clock signal (DFT_ON) and the mode SCAN enable clock Signal (SE) control the output of the input test data (SCAN_IN [ n:0 ]) after the test of the SCAN chain test circuit 212, please refer to FIG. 5, and details thereof are not repeated herein.

Also, regarding the output test data (scan_out [ n:0 ]) it is to be noted that: as shown in FIG. 2, the Output pins (e.g., output_0, output_1, …, output_n) of the scan chain test circuit may be directly connected to the register controller 204 and integrate the data Output for analysis by a designer. In some embodiments, the designer may also directly connect the leads to the Output pins (e.g., output_0, output_1, …, output_n) and connect the relevant test devices (e.g., visual analysis devices such as logic analyzers) to Output test data, so that the designer can configure himself according to the actual needs, and the invention is not limited thereto.

The external device 202 may be a visual test analysis device, such as: may be a logic analyzer, an oscilloscope, or other type of test analysis device, without limitation.

The register controller 204 may further include instruction registers and/or data registers, and those skilled in the art may configure a plurality of D flip-flops and/or a plurality of gate structures according to actual use conditions to meet the requirements of actual test circuit configuration, but the present invention is not limited thereto.

In some embodiments, the first level is a high level; the second level is a low level. In addition, although the first level and the second level in fig. 2 are respectively represented by logic "1" and logic "0", they may be a power level (e.g. level "VDD") and a ground level (e.g. level "0") of the transistor or any level that allows the data selector 106 to identify whether to select the test data from the first input terminal or the second input terminal, which is not limited in the present invention.

In some embodiments, the scan chain control circuit described above may be applied to a joint test group (Joint Test Action Group, JTAG) Debug interface and/or a serial line Debug (SERIAL WIRE Debug, SWD) interface, as the invention is not limited in this respect.

Fig. 3 is a schematic diagram of a data selector according to an embodiment of the invention. The data selector 206 may be a combination of a plurality of data selectors. As shown in fig. 3, the data selector 206 is a combination of n+1 (n is greater than or equal to 0 and is an integer) data selectors, a first input terminal of the data selector 206 is coupled to the scan chain test circuit 212, and receives the pin input data (si_0, si_ … si_n) of n+1 (n is greater than or equal to 0 and is an integer) bits (bits) transmitted from the scan chain test circuit 212; a second input terminal and a third input terminal are coupled to the register controller 204, and receive the register input data (Reg_scan_in [ n:0 ]) and the enable clock signal (SCAN_EN) of n+1 (n.gtoreq.0 and is an integer) bits (bit) transmitted from the register controller 204. The third input terminal is a control signal terminal, and a person skilled in the art can set the control signal terminal (the third input terminal) according to the actual configuration, so that the data selector 206 recognizes that the test data is to be selected from the first input terminal or the second input terminal, which is not limited in the present invention.

When the enable clock signal received by the data selector 206 from the register controller 204 is at a first level (e.g., a high level "1"), the data selector 206 selects the n+1-bit register input data (reg_scan_in [ n:0 ]) as input data (scan_in [ n:0 ]) to be input to the SCAN chain test circuit 212; when the enable clock signal received by the data selector 206 from the register controller 204 is at a second level (e.g., a low level "0"), the data selector 206 selects the n+1-bit pin input data (si_0, si_1 … si_n) as input data (scan_in [ n:0 ]) to be input to the SCAN chain test circuit 212.

It should be noted that the n+1 scan chain test circuit includes n+1 input pins and n+1 output pins. As shown in fig. 2, input_0 is an Input pin of the 0 th scan chain test circuit, and output_0 is an Output pin of the 0 th scan chain test circuit; input_1 is the Input pin of the 1 st scan chain test circuit, and output_1 is the Output pin … of the 1 st scan chain test circuit; and so on, input_n is the Input pin of the nth scan chain test circuit, and output_n is the Output pin of the nth scan chain test circuit. Input data of n+1 input pins included in the n+1 scan chain test circuits may be uniformly configured through the data selector 206, and output data of n+1 output pins included in the n+1 scan chain test circuits may be uniformly output to the external device 202 through the register controller 204 for analysis; the data input/output control of the scan chain test circuit 212 is realized, and the test flexibility is improved.

The register input data (reg_scan_in [ n:0 ]), the pin input data (si_0, si_1 … si_n), the test input data (scan_in [ n:0 ]), the test output data (scan_out [ n:0 ]), and the test data IN which the register output data (reg_scan_out [ n:0 ]) are n+1 bits (bits) correspond to the n+1 SCAN chain test circuits. The data selector 206 is a combination of n+1 data selectors, and corresponds to the n+1 scan chain test circuits.

The n+1 bit (bits) of test data (SCAN_IN [ n:0 ]) may be selected for testing by a single SCAN chain test circuit of n+1 SCAN chain test circuits. IN other words, the n+1 bit (bits) of test data (scan_in [ n:0 ]) may be used to test all of the n+1 SCAN chain test circuits, or only one and/or several of the n+1 SCAN chain test circuits may be used to test all of the n+1 SCAN chain test circuits. Those skilled in the art can configure themselves according to actual test requirements, and the present invention is not limited thereto.

For example, assume that the scan chain test circuit 212 is a test circuit having 4 scan chains (including 0 th, 1 st, 2 nd, and 3 rd), and the 1 st and 3 rd scan chain test circuits are tested. When the third input terminal of the data selector 206 receives the enable clock signal transmitted from the register controller 204 at the first level (e.g., high level "1"), the data selector 206 selects the second input terminal test data (e.g., register input data (reg_scan_in [0101 ])) as the test input data (scan_in [0101 ]) to be input to the SCAN chain test circuit 212. When the third input terminal of the data selector 206 receives the enable clock signal transmitted from the register controller 204 as the second level (e.g., low level "0"), the data selector 206 selects the first input terminal test data (e.g., pin input data (si_0, si_1 … si_n)) as the test input data (scan_in [0101 ]) to be input to the SCAN chain test circuit 212. More specifically, the high level test data "1" of the above test input data is input to the 1 st and 3 rd scan chain test circuits, and the low level test data "0" of the above test input data is input to the 0 th and 2 nd scan chain test circuits. IN this embodiment, when the chip is packaged on the printed circuit board, the original input pins can still use the register input data (reg_scan_in [0101 ]) as the test input data (scan_in [0101 ]) to input to the SCAN chain test circuit 212, so that some adverse factors IN the test process are avoided greatly, and the test efficiency is improved.

When the third input terminal of the data selector 206 receives the enable clock signal transmitted from the register controller 204 as the second level (e.g., low level "0"), the data selector 206 selects the first input terminal test data (e.g., pin input data (si_0, si_1, si_2, and si_3)) as the test data (scan_in [0101 ]) to be input to the SCAN chain test circuit 212. More specifically, the high level test data "1" of the above test input data is input to the 1 st and 3 rd scan chain test circuits, and the low level test data "0" of the above test input data is input to the 0 th and 2 nd scan chain test circuits.

The test data (scan_in [0101 ]) writes the 1 st and 3 rd SCAN chain test circuits to be tested with a high level (e.g., high level "1"), and the 0 th and 2 nd SCAN chain test circuits 212 not to be tested with a low level (e.g., low level "0").

The data selector 206 inputs test data (SCAN_IN [0101 ]) to the SCAN chain test circuit 212; under the action of the shift clock signal (ip_clk), the mode test clock signal (dft_on) and the mode SCAN enable clock Signal (SE), the test data (scan_in [0101 ]) is shifted IN the SCAN chain test circuit to be scanned, and the test data (scan_out [0101 ]) is Output to the register controller 204 via the Output pin (Output Pad), and the register controller 204 records the test data integration (reg_scan_out [0101 ]) and outputs the test data to the external device 202 for analysis.

Fig. 4 is a schematic diagram of a clock controller 208 according to an embodiment of the invention. Next, as shown in fig. 4, the clock controller 208 is coupled to the register controller 204, and receives the enable clock signal (scan_en) and a register Shift clock signal (shift_clk) transmitted by the register clock control module 214, and outputs the Shift clock signal (ip_clk) to a plurality of serially connected D-type flip-flops of the SCAN chain test circuit 212. Under the action of the shift clock signal (ip_clk), all the register test data (scan_in [ n:0 ]) inputted to the SCAN chain test circuit 212 via the data selector 206 are shifted to the next stage register as a whole, and the value of the last stage register is outputted to the register controller 204 and outputted to the external device 202 as an integration (reg_scan_out [ n:0 ]).

The register controller 204 is coupled to the external device 202, the external device 202 generates a Test Clock signal (TCK) and transmits the Test Clock signal to the register controller 204 in a Test state, and the register controller 204 receives the Test Clock signal (TCK) and generates the enable Clock signal (scan_en). For example, when a tester of the external device 202 connects the external device 202 to the register controller 204, the tester causes the external device 202 to generate a continuous standard high-low Test Clock (TCK) signal in a Test state, and transmits the Test Clock signal to the register controller 204; the register controller 204 generates the enable Clock signal (scan_en) after receiving the continuous standard high and low Test Clock signal (TCK) for one and/or more Clock cycles. As shown in fig. 6, the register controller 204 generates the enable Clock signal (scan_en) after receiving the Test Clock signal (TCK) for two Clock cycles, and can be configured by one skilled in the art according to the actual requirements without any limitation.

The register clock control module 214 and the clock controller 208 may also be configured with a plurality of D flip-flops and/or a plurality of gate structures to meet the actual needs. For example: the register clock control module 214 further includes a plurality of D flip-flops 400, D flip-flops 402, and a gating clock circuit (Input Clock Gating, ICG) 404. The clock controller 208 further includes a plurality of D flip-flops 406, D flip-flops 408, a gating clock circuit (Input Clock Gating, ICG) 410, a clock oscillator (Phase Locked Loop, PLL) 412, a first data selector 414, and a second data selector 416. The first data selector 414 and the second data selector 416 may be integrated data selectors formed by combining a plurality of data selectors, and the clock oscillator (Phase Locked Loop, PLL) 412 may be disposed outside the clock controller 208 or separately disposed in a module, which may be configured by a person skilled in the art according to the actual needs, and is not limited in this regard.

As shown in fig. 4, the first input terminal of the first data selector 414 is coupled to the scan chain test circuit pin, and receives the pin shift clock (ext_clk) transmitted from the scan chain test circuit pin; the second and third inputs are coupled to the register clock control module 214 of the register controller 204, and receive the register Shift clock signal (shift_clk) transmitted by the register clock control module 214 and the enable clock signal scan_se transmitted by the register controller 204. Specifically, the first data selector 414 receives the enable clock signal scan_se according to the third input terminal (control terminal), and selects one of the two (shift_clk or ext_clk) to be transmitted to the second data selector 416. When the third input terminal of the first data selector 414 receives the enable clock signal scan_se as a high level, the first data selector 414 selectively outputs the register shift clock signal to the second data selector 416; otherwise, the output pin shifts the clock to the second data selector 416. It should be noted that the enable clock signal scan_se may be directly transmitted from the register control 204 to the clock controller 208. In some embodiments, the clock signal may also be transmitted to the clock controller 208 via the register clock control module 214 in the register control 204, but the present invention is not limited thereto.

A first input terminal of the second data selector 416 receives a continuous functional clock signal (func_clk) generated by a clock oscillator (Phase Locked Loop, PLL), a second input terminal receives a clock signal (shift_clk or ext_clk) transmitted from the first data selector 414, and a third input terminal (signal control terminal) is coupled to the mode controller 210 shown in fig. 2, receives a mode scan clock Signal (SE) transmitted from the mode controller 210, and finally outputs a Shift clock signal (ip_clk) to the scan chain test circuit 212 of fig. 2. Specifically, when the third input terminal of the second data selector 416 receives a mode scan clock Signal (SE) transmitted by the mode controller 210 of fig. 2 to be at a high level, the clock signal (shift_clk or ext_clk) transmitted by the first data selector 414 is selected as the Shift clock (ip_clk) to be output to the scan chain test circuit. When the third input terminal of the second data selector 416 receives a mode scan clock Signal (SE) transmitted from the mode controller of fig. 2, it selects a continuous functional clock signal (func_clk) generated by the clock oscillator (Phase Locked Loop, PLL) received by the first input terminal as a shift clock (ip_clk) to be output to the scan chain test circuit. Here, when the second data selector 416 selects the continuous functional clock signal (func_clk) as the shift clock (ip_clk) to be output to the scan chain test circuit, it indicates that the scan chain test circuit is operated in the functional mode (Function mode) state at this time. When the second data selector 416 selects the register Shift clock signal (shift_clk) to be output to the Scan chain test circuit as the Shift clock (ip_clk), it means that the Scan chain test circuit operates in the Scan mode (Scan mode) state at this time. When the second data selector 416 selects the pin shift clock (ext_clk) to be output to the scan chain test circuit as the shift clock (ip_clk), it indicates that the scan chain test circuit is operated in the original test mode (Original test mode) at this time. in other words, when the mode Scan clock signal SE is high, it indicates that a test mode (e.g., scan mode or original test mode (Original test mode)) is currently enabled, and therefore the test clock (Shift_clk or Ext_clk) output by the first data selector 414 is selected as the Shift clock (IP_CLK) to be output to the Scan chain test circuit. When the mode scan clock Signal (SE) is low, it indicates that the functional mode (Function mode) is currently activated, and thus a continuous functional clock signal func_clk generated by the first data selector 414 (i.e., by the clock oscillator 412) is selected to be output as a shift clock (ip_clk) to the scan chain test circuit. Furthermore, when the mode scan clock signal SE is at a high level, it is determined what kind of test mode is to be started according to the test mode signal (test_mode), and for the detailed description of the mode status portion, please refer to the description of the relevant portion of table 1, which is not repeated here.

Under the action of the shift clock signal (ip_clk), all the register test data (scan_in [ n:0 ]) inputted to the SCAN chain test circuit 212 via the data selector 206 are shifted to the next stage register as a whole, and the value of the last stage register is outputted to the register controller 204 and outputted to the external device 202 as an integration (reg_scan_out [ n:0 ]).

It should be specifically explained that the D-type flip-flop 406 of the clock controller 208 further includes an inverter (not shown) for inverting the TCK to ensure the timing consistency of the clocks, thereby improving the test performance. When the register clock control module 214 transmits an enable clock signal (e.g., an enable clock signal is "1"), the clock controller 208 further includes an inverter (not shown) that inverts (invert) the high-level enable clock signal and transmits the high-level enable clock signal to the D-type flip-flop 406, i.e., the high-level enable clock signal (e.g., an enable clock signal is "1") is converted to a low-level enable clock signal (e.g., an enable clock signal is "0") and transmitted to the gate clock circuit 410 of the clock controller 208 via the D-flip-flops 406 and 408. Locking the continuous functional clock signal (func_clk) when the enable clock signal is high; conversely, a stable continuous functional clock signal (func_clk) is output. It should be specifically noted that, the locking of the continuous functional clock signal (func_clk) may be interpreted as blocking the continuous functional clock signal (func_clk) from going down, or may be interpreted as locking the continuous functional clock signal (func_clk) in a high level or low level state without any change, and those skilled in the art may make corresponding interpretation according to the implemented circuit function, but the invention is not limited thereto.

Fig. 5 is a schematic diagram of a mode controller 210 according to an embodiment of the invention. As shown in fig. 5, the mode controller 210 is coupled to a register mode control module 216. The mode controller 210 receives an enable clock signal scan_se from the register mode control module 216 and outputs a test mode clock signal (dft_on) and a mode SCAN enable clock Signal (SE) to the SCAN chain test circuit 212. The register mode control module 216 may also configure a plurality of D flip-flops to meet the actual needs. For example: the register mode control module 216 also includes a D flip-flop 500 and a D flip-flop 502. a first input terminal of the fourth data selector 506 of the mode controller 210 receives a mode scan enable clock signal (se_i) from the original control scan chain test circuit; a second input coupled to the register mode control module 216 for receiving a Scan enable back-up signal (scan_en_dp); the third input receives a Test mode signal (test_mode) from the original control scan chain Test circuit. A first input terminal of the third data selector 504 of the mode controller 210 receives a mode test clock signal (dft_i) from the original control scan chain test circuit; A second input coupled to the register mode control module 216 for receiving a Scan mode back-up signal (scan_mode_dp); the third input receives a Test mode signal (test_mode) from the original control scan chain Test circuit. Regarding the mode scan enable clock signal (se_i), the Test mode signal (test_mode), and the mode Test clock signal (dft_i) of the original control scan chain Test circuit, it is necessary to explain that: the mode scan enable clock signal (se_i) and the mode test clock signal (dft_i) that originally control the scan chain test circuit are mode control signals of the scan chain test circuit operating in the original test mode (Original test mode) may be provided by the associated modules of the original scan chain test circuit or by a JTAG port (not shown in fig. 5). The mode scan enable clock signal (se_i) and the mode test clock signal (dft_i) of the original control scan chain test circuit are similar to the pull-up principle of the test mode clock signal (dft_on) and the mode scan enable clock Signal (SE). The mode scan enable clock signal (se_i) and the mode test clock signal (dft_i) of the original control scan chain test circuit are pulled up to a high level signal after receiving the TCK signal and the mode test clock signal (dft_i) is pulled up to a high level signal before the mode scan enable clock signal (se_i) of the original control scan chain test circuit. it should be noted here that the mode test clock signal (dft_i) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock signal (se_i) of the original control scan chain test circuit. Those skilled in the art can configure the related mode signal control module of the original scan chain test circuit according to the product requirement, and the invention is not limited thereto. The Test mode signal (test_mode) is a control signal for controlling the scan chain Test circuit to operate in what mode state, and the specific functional details are described in the relevant part of table 1, and are not repeated here. The Test mode signal (test_mode) may be generated by an associated internal module, not shown in the present invention, and a functional module (not shown in fig. 5) for generating or providing the associated Test mode signal (test_mode) may be configured by a person skilled in the art.

The test mode clock signal (DFT_ON) and a mode SCAN enable clock Signal (SE) are signals that control the output data (SCAN_OUT [ n:0] of the test input data (SCAN_IN [ n:0 ]) of FIG. 2 after being tested by the SCAN chain test circuit 212. In some embodiments, as partially shown in fig. 6, the test mode clock signal (dft_on) is pulled up to a high level signal by the mode controller 210 after receiving the TCK signal 3 clock signals, and the mode scan enable clock Signal (SE) is pulled up to a high level signal by the mode controller 210 after receiving the TCK signal 4 clock signals, or the test mode clock signal (dft_on) and the mode scan enable clock Signal (SE) are pulled up to a high level signal by the mode controller 210 after a plurality of clock cycles of the TCK signal and the test mode clock signal (dft_on) is pulled up to a high level signal prior to the mode scan enable clock Signal (SE). It should be noted that, the test mode clock signal (dft_on) is pulled up to a high level signal 1 clock period before the mode scan enable clock Signal (SE), and those skilled in the art can configure the test mode clock signal (dft_on) according to the actual needs, and the invention is not limited thereto.

The test mode clock signal (DFT_ON) and a mode SCAN enable clock Signal (SE) are pulled high to indicate that the output data (SCAN_OUT [ n:0] shown in FIG. 2) after the test by the SCAN chain test circuit is output to the SCAN chain control circuit 200 shown in FIG. 2 and finally to the external device for analysis by the designer.

Specifically, when the Test mode signal (test_mode) is at a low level (e.g., test_mode is "0"), the mode scan enable clock signal (se_i) from the original control scan chain Test circuit is selectively outputted as the mode scan enable clock Signal (SE) through the fourth data selector 506 in the mode controller 210, and the third data selector 504 selectively outputs the mode Test clock signal (dft_i) from the original control scan chain Test circuit as the mode Test clock signal (dft_on). When the Test mode signal (test_mode) is at a high level (e.g., test_mode is "1"), the mode Scan enable backup clock signal (scan_en_dp) from the register mode control module 216 is selectively outputted as the mode Scan enable clock Signal (SE) via the fourth data selector 506 in the mode controller 210, and the third data selector 504 is selectively outputted as the mode Test clock signal (dft_on) from the register mode control module 216.

FIG. 6 is a schematic diagram of a scan chain control circuit clock signal according to an embodiment of the invention. The following will be described in more detail with reference to fig. 2,4, 5, and 6. As shown in a first period T1 of fig. 6, when a tester of the external device 202 in fig. 2 connects the external device 202 to the register controller 204, the tester causes the external device 202 to generate a continuous standard high-low level Test Clock signal (TCK) in a Test state, and transmits the Test Clock signal to the register controller 204; the register controller 204 generates a high enable Clock signal (e.g., SCAN_EN is "1") after receiving the continuous standard high and low Test Clock signal (TCK) for one and/or more Clock cycles. At this time, the data selector 206 IN FIG. 2 inputs the test data (SCAN_IN [ n:0 ]) to the SCAN chain test circuit 212. It should be noted that when the third input terminal (or referred to as the signal control terminal) of the data selector 206 receives the enable clock signal of high level (e.g., scan_en is "1"), it selects the register input data (reg_scan_in [ n:0 ]) as the input data (scan_in [ n:0 ]) to be input to the SCAN chain test circuit 212. As shown IN FIG. 6, it is further noted that the input data (SCAN_IN [ n:0 ]) prior to the T1 period may be pin input data SI_0, SI_n, or data that is otherwise incoming (not of interest as shown IN FIG. 6).

Next, as shown in the second period T2 in fig. 6, when the register clock control module 214 in fig. 4 transmits the high-level enable clock signal scan_en (e.g., the enable clock signal is "1"), an inverter (not shown) further included in the clock controller 208 in fig. 4 inverts (invert) the high-level enable clock signal, and transmits the high-level enable clock signal to the D-type flip-flop 406, i.e., the high-level enable clock signal (e.g., the enable clock signal is "1") is converted to the low-level enable clock signal (e.g., the enable clock signal is "0") and is transmitted to the gate clock circuit 410 of the clock controller 208 through the D flip-flops 406 and 408. When the enable clock signal is high, the continuous functional clock signal (func_clk) is locked. Next, as shown in a third period T3 of fig. 6, when the Test mode signal (test_mode) is at a high level (e.g., test_mode is "1") in fig. 5, the third data selector 504 in the mode controller 210 selects and outputs the mode Test backup clock signal (scan_mode_dp) from the register mode control module 216 as the mode Test clock signal (dft_on) output, i.e., outputs the mode Test clock signal at a high level. Next, as shown in a fourth period T4 of fig. 6, when the Test mode signal (test_mode) is at a high level (e.g., test_mode is "1") in fig. 5, the fourth data selector 506 in the mode controller 210 selects and outputs the mode Scan enable backup clock signal (scan_en_dp) from the register mode control module 216 as the mode Scan enable clock Signal (SE) output, i.e., outputs the mode Scan enable clock signal at a high level. Finally, as shown in a fifth period T5 of fig. 6, when the clock controller 208 of fig. 4 receives the enable clock signal (scan_en) and the mode SCAN enable clock Signal (SE) transmitted from the register clock control module 214 and the mode controller 210, the clock controller 208 outputs a shift clock ip_clk signal having the same frequency as the register shift clock to the SCAN chain test circuit 212 of fig. 2 or the shift clock ip_clk of the clock controller 208 is switched to the register shift clock output by the register controller 204 and transmits the register shift clock to the SCAN chain test circuit 212 of fig. 2. at this time, under the action of the shift clock signal (ip_clk), the test data (scan_in [ n:0 ]) inputted to the SCAN chain test circuit 212 IN the first period T1 is shifted IN the SCAN chain test circuit to be scanned, and the test data (scan_out [ n:0 ]) is outputted to the register controller 204 IN fig. 2 via the Output pin (Output Pad) of the SCAN chain test circuit IN the fifth period T5, and the register controller 204 records the test data and integrates (reg_scan_out [ n:0 ]) to be outputted to the external device 202 for the tester to analyze. it should be noted that fig. 6 also depicts a signal diagram after a number of clock cycles, i.e. after a period of time T6 representing the completion of the test. The clock signal diagram after this partial period will vary due to the specific circuit configuration, and fig. 6 is only shown for simplicity and is not intended to be limiting or illustrative.

It should be noted that the above description with reference to the clock signal schematic diagram of fig. 6 is only the operation state of the scan chain control circuit when the enable clock signal is at the high level, and will be described in detail with reference to table 1 below.

As shown in table 1, the Scan chain control circuit can operate in three modes, namely a Scan mode (Scan mode), a raw test mode (Original test mode), and a Function mode (Function mode). After the scan chain control circuit turns on the external device 202 and receives a number of TCK clock cycles transmitted by the external device 202 (two clock cycles as shown in fig. 6). The register controller 204 in the SCAN chain control circuit 200 shown in FIG. 2 generates a high enable clock signal (SCAN_EN). When the clock controller 208 shown in fig. 4 receives the high-level enable clock signal (scan_en), the data selector 414 in fig. 4 selects the register shift clock (shift_clk) to output to the data selector 416. The register controller 204 as shown in fig. 5 generates the Scan mode dp and Scan en dp signals at high levels accordingly.

Further, when the Test mode signal (test_mode) is at a high level, the data selector 506 in the mode controller 210 shown in fig. 5 selects the scan_en_dp signal output at a high level, and the data selector 504 in the mode controller 210 selects the scan_mode_dp signal output at a high level. Here, the outputs of the data selector 506 and the data selector 504 in table 1 are labeled with only scan_mode_dp and scan_en_dp signals, and are not labeled with high or low signals. It should be specifically explained that when the enable clock signal (scan_en) and the Test mode signal (test_mode) are at high level, the scan_mode_dp and scan_en_dp are necessarily at high level and there is no low level state, but those skilled in the art can design themselves according to their own needs, so the scan_mode_dp and scan_en_dp signal states are not labeled in table 1.

Returning to fig. 4, when the data selector 416 in fig. 4 receives the SE signal of high level (which may be the scan_en_dp signal of high level), the data selector 416 in fig. 4 selects shift_clk to output to the Scan chain test circuit. At this time, the Scan chain control circuit operates in the Scan mode state, and the test data input to the Scan chain test circuit is register input data reg_scan_in [ n:0].

The register controller in the SCAN chain control circuit 200 shown in fig. 2 generates a low enable clock signal (scan_en). When the clock controller 208 shown in fig. 4 receives the enable clock signal (scan_en) of the low level, the data selector 414 in fig. 4 selects the pin shift clock (ext_clk) to output to the data selector 416. It should be noted at this time that the register controller 204 as shown in fig. 5 may consider that the scan_mode_dp and scan_en_dp signals are not generated or that the scan_mode_dp and scan_en_dp signals of low level are generated.

When the Test mode signal (test_mode) is low, the data selector 506 in the mode controller 210 shown in fig. 5 selects the high se_i signal output, and the data selector 504 in the mode controller 210 selects the high dft_i signal output. Here, the outputs of the data selector 506 and the data selector 504 in table 1 are labeled with only the se_i and dft_i signals, and are not labeled with either high or low. It should be specifically explained that se_i and dft_i are pulled up to high level by other circuit blocks (not shown) shown in fig. 5.

Referring back to fig. 4, when the data selector 416 in fig. 4 receives the high SE signal (which may be the high se_i signal), the data selector 414 in fig. 4 selects the pin shift clock (ext_clk) to output to the scan chain test circuit. At this time, the scan chain control circuit operates in Original test mode states, and the test data input to the scan chain test circuit is register input data si_0, si_ … si_n.

Finally, it should be explained that the register controller in the SCAN chain control circuit 200 shown in fig. 2 generates a low-level enable clock signal (scan_en). When the clock controller 208 shown in fig. 4 receives the enable clock signal (scan_en) of the low level, the data selector 414 in fig. 4 selects the pin shift clock (ext_clk) to output to the data selector 416. Further, when the Test mode signal (test_mode) is at a low level, the data selectors 506 and 504 in the mode controller 210 shown in fig. 5 receive the se_i signal and the dft_i signal output at low levels, which are output from other circuit blocks (not shown) shown in fig. 5. It should be specifically explained that at this time, se_i and dft_i of low level indicate that no test is performed, and normal Function verification operation of the chip is performed, that is, indicate that Function mode is entered, so that test data is unknown according to the test Function decision of the chip.

It should be noted in more detail that the above three test mode states can be freely switched, i.e. one test mode state can be switched to one of the other two test mode states after completion. As shown in fig. 6 (which shows that the Scan chain control circuit 200 is now operating in the Scan mode state), after a period of T5 for a few clock cycles, test data (reg_scan_out [ n:0 ]) has been completed and output to the external device 202. The SCAN chain control circuit 200 of the present invention may perform a Reset (Reset) operation, where all clock signals (e.g., scan_en goes low, func_clk is synchronized with the PLL clock (also known as unlocked or blocked), dft_on and SE go low, shift_clk goes low, ip_clk is synchronized with the PLL clock, etc.) are restored to the clock state prior to the T1 period. Next, the scan chain control circuit 200 may restart to operate in the original test mode state or the operation mode state, i.e., the scan chain control circuit 200 is switched from the scan mode state to the original test mode state or the scan mode state to the functional mode state. The above description simply describes the switching between the scan chain control circuit mode states of the present invention, but the present invention is not limited thereto.

TABLE 1

Fig. 7 is a schematic diagram of a scan chain control circuit according to an embodiment of the invention. The method mainly comprises the following steps: in step S702, a continuous stable test clock signal TCK is transmitted to the register controller 204 via the external device 202 shown in fig. 2, and the register controller 204 of the SCAN chain control circuit 200 generates a high-level enable clock signal (scan_en=1) or a low-level enable clock signal (scan_en=0), i.e. enables the SCAN mode or the original test mode.

IN step S704, the SCAN chain control circuit 200 selectively outputs a test data SCAN_IN [ n:0] to the SCAN chain test circuit 212 according to the high level enable clock signal or the low level enable clock signal. As shown in fig. 2, when the enable clock signal is high (e.g., the enable signal is "1"), the data selector 206 selects the test data (reg_scan_in [ n:0 ]) transmitted to the second input terminal by the register controller 204 as the test data to be input to the scan chain test circuit 212. When the enable clock signal is low (e.g., the enable signal is "0"), the data selector 206 selects the test data (si_0, si_1 … si_n) transmitted to the first input terminal by the scan chain test circuit 212 as the test data to be input to the scan chain test circuit 212.

In step S706, the clock controller 210 of the scan chain control circuit 200 triggers the test data to move in the scan chain test circuit 212. As shown in fig. 4, because the clock controller 210 receives a high-level enable signal when the enable signal is high (e.g., the enable signal is "1"). The first data selector 414 of the clock controller 210 selects the register Shift clock signal (shift_clk) transmitted from the register clock control module 214 and received by the second input terminal to transmit to the second data selector 416. The second data selector 416 of the clock controller 210 selects a register Shift clock signal (shift_clk) transmitted by the first data selector 414 received at the second input terminal as a Shift clock signal (ip_clk) to be output to the scan chain test circuit 212. When the enable signal is low (e.g., the enable signal is "0"), the clock controller 210 receives a low enable signal. The first data selector 414 of the clock controller 210 selects the pin shift clock signal (ext_clk) transmitted from the scan chain test circuit 212 and received at the first input terminal to transmit to the second data selector 416. The second data selector 416 of the clock controller 210 selects a pin shift clock signal (ext_clk) transmitted from the first data selector 414 received at the second input terminal as a shift clock signal (ip_clk) to be output to the scan chain test circuit 212.

In step S708, test data of all the scan chain test circuits 212 are output. Because all the register data in the SCAN chain test circuit 212 is shifted down to the next stage of registers as a whole by the register shift clock (shift_clk) or (ext_clk) when the enable clock signal is high and the test mode signal is low or the enable clock signal is low and the test mode signal is high, the SCAN chain test circuit 212 outputs the test data (scan_out [ n:0 ]) via the output pin of the SCAN chain test circuit 212 and outputs the test data (reg_scan_out [ n:0 ]) to the test access port via the register controller 204 to output the test data to the chip external test device 202.

In step S710, steps S706, S708 are repeated until all data is shifted out to the external device 202.

The test principle of the scan chain control circuit is described with reference to fig. 1 to 7, and how the scan chain control circuit realizes the test flexibility when the chip is packaged on the PCB board will be explained in detail below. Fig. 8 is a schematic diagram of a scan chain test circuit packaged on a PCB according to an embodiment of the invention. As shown in fig. 8, only the integrated design circuits IC1, IC2 to be tested and their corresponding scan chain test circuits 212-1, 212-2, 212-3, 212-4 (as shown in the dashed boxes, the rectangular pattern is illustrated as a D-flip-flop or other test basic cell circuit configuration, the invention is not limited thereto), PAD pins and scan chain control circuit 200. It should be noted here that the integrated design circuits IC1, IC2 to be tested as shown in the figures only show two scan chain test circuits 212-3, 212-4 and 212-1, 212-2, respectively. However, the number of the integrated design circuits to be tested and the scan chain test circuits can be determined according to the actual test requirements or according to the corresponding test requirements such as the product functions of the integrated design circuits to be tested, and the skilled person can design the integrated design circuits according to the actual situations. In addition, when the test circuit (also referred to as including the scan chain control circuit and the scan chain test circuit) is packaged on the PCB, PAD pins (i.e., input/output pins as shown in fig. 2) of the scan chain test are packaged on the PCB. As shown in fig. 8, the pins that are packaged on the PCB board are represented as PAD pins as hatched rectangles in the figure, but the two pins should not be confused by those skilled in the art. Alternatively, in order to distinguish the PAD pin shown in fig. 2 from the PAD pin shown in fig. 8, and facilitate understanding, the PAD pin on the PCB may also be referred to as a lead interface or a lead terminal, and the description of the lead terminal will be used hereinafter when describing the pin on the PCB. In addition, for convenience of illustration, fig. 8 only shows the scan chain control circuit 200, and the specific circuit structures of the scan chain test circuits 212-1, 212-2, 212-3, and 212-4 and the internal circuit structures of the scan chain control circuit 200 are shown in fig. 8, and the specific details of the scan chain test circuits 212-1, 212-2, 212-3, and 212-4 are not described in detail herein with reference to the description of fig. 2 to 5. it should be noted that the Input pins (i.e., input_0, input_1, …, input_n pins shown in fig. 2, and not shown in fig. 8) of the scan chain test circuits 212-1, 212-2, 212-3, and 212-4 shown in fig. 8 are all directly connected to the respective scan chain test circuits 212-1, 212-2, 212-3, and 212-4, but the Input pins (i.e., input_0, input_1, …, and input_n) of the scan chain test circuit 212 are not directly connected to the scan chain test circuits in fig. 2. It should be explained here that a person skilled in the art can design a circuit connection either in the connection shown in fig. 2 or in the connection shown in fig. 8. For convenience in explaining the circuit principle of the present invention and illustrating the schematic drawing, fig. 2 is a schematic diagram mainly illustrating the circuit design manner of the scan chain control circuit for controlling the scan chain test circuit, so the Input pins (input_0, input_1, …, input_n) of the scan chain test circuit 212 are not directly connected to the scan chain test circuit, and the present invention is not limited thereto.

As shown in fig. 8, when the test circuit (also referred to as including the scan chain control circuit and the scan chain test circuit) is packaged on the PCB board, the two scan chain test circuits 212-3, 212-4 and 212-1, 212-2 of the integrated design circuits IC1, IC2 to be tested are respectively connected to the terminals of the PCB board, as shown by the hatched rectangle.

In this case, if the integrated circuit IC1 and/or the integrated circuit IC2 are to be tested, only the lead terminals of 212-3 and 212-4 and/or the lead terminals of 212-1 and 212-2 need to be respectively imported and exported with test data (input and output are not distinguished in the drawings, but the invention is not limited thereto) for the designer to analyze the chip design. However, with the development of integrated design circuits, chip testing is faced with a number of problems as chips are packaged onto a PCB from individual dies (or die) on a wafer. On the one hand, each scan chain test circuit has two pins for input and output respectively, when the scan chain test circuits are too many (for example, when the scan chain test circuits are 50, there will be 100 pins), the test is performed from the lead end leads of each scan chain test circuit, so that the difficulty of the test is greatly increased, and the development and test cost is increased. The other side, when packaged on the PCB board, may also cause connection failure of the lead terminal, and may also cause poor contact failure such as short circuit and/or open circuit during testing, which results in reduced accuracy of the test result and is not beneficial to analysis.

Based on the analysis, as shown in fig. 8, the input/output pins of all scan chain test circuits are uniformly coupled to the scan chain control circuit (the input/output pins of the scan chain test circuits 212-1, 212-2, 212-3, 212-4 in the dashed boxes shown in fig. 8 are uniformly coupled to the scan chain control circuit), and the input/output pins of the scan chain test circuits are controlled to import or export test data to or from the test data via the scan chain control circuit (the input and the output are not distinguished in the drawing, but the invention is not limited thereto). The scan chain control circuit is connected to an external device through a test Interface (Interface as shown in fig. 8).

In some embodiments, the scan chain control circuit package may be applied to ball grid array (ball GRID ARRAY, BGA), flip-chip (flip-chip), or contact array package (LAND GRID ARRAY, LGA), which is not limited in the present invention.

Specifically, after the bare chip is packaged on the PCB, if the chip design is relatively simple, the number of the lead terminals is relatively small, and the packaging quality is good, the test can be directly performed by externally connecting the lead terminals with the leads. If the chip design is complex, the number of the lead terminals is large or if the package quality is not good (short circuit and/or open circuit and other bad contact faults are caused during test), the test can be controlled by the scan chain control circuit without passing the lead terminal test. In other words, the scan chain control circuit directly performs chip testing through the interface on the test circuit board without performing testing through externally connecting the lead end with the lead. The SCAN chain control circuit can use the pin input data (SCAN_IN [ n:0 ]) to input the test data into the SCAN chain test circuit and output the test data (Scan_out [ n:0 ]) after the test is performed under the action of the pin shift clock (ext_clk) to the external equipment for analysis by the designer. At this point, the so-called scan chain control circuit operates in the original test mode (Original test mode). More specifically, the scan chain control circuit may also use register input data (reg_scan_in [ n:0 ]) and input test data to the scan chain test circuit for testing under the action of the register Shift clock signal (shift_clk), and then output test completed test data (reg_scan_out [ n:0 ]) to the external device for analysis by the designer. At this time, it is called a Scan chain control circuit operating in a Scan mode (Scan mode). Furthermore, the scan chain control circuit may be turned off after the chip verification test is completed. At this time, the so-called scan chain control circuit operates in a Function mode (Function mode). The description of this part is referred to the descriptions of the parts shown in fig. 2 to 7, and will not be repeated here.

The SCAN chain control circuit may input test data to the SCAN chain test circuit using the pin input data (scan_in [ n:0 ]), and output test data (scan_out [ n:0 ]) after performing a test under the pin shift clock (ext_clk ]) to an external device. It should be noted that, the pin input data (scan_in [ n:0 ]) is the test data transmitted from the input pin of the SCAN chain test circuit (this pin should be understood as the input pin of the SCAN chain test circuit shown IN fig. 2, but should not be understood as the lead terminal on the PAB board) to the SCAN chain control circuit, and is transmitted to the SCAN chain test circuit via the SCAN chain control circuit to complete the test (for this part, please refer to the description of fig. 3, and the description is omitted here). Finally, the tested test data (Scan_out [ n:0 ]) can be directly output to the external device through the lead terminal on the test circuit board, or can be transmitted to the Scan chain control circuit through the scan_out [ n:0 ]) and output to the external device through the Interface. Specifically, there are two options for outputting the test data (Scan_out [ n:0 ]). First, can directly export to external equipment through the lead terminal lead wire on the PCB board. Second, the test data (scan_out [ n:0 ]) after the test is completed may be output to the Scan chain control circuit and output to the external device via the Interface. Regarding the case of outputting test data, since the principle is similar to that of inputting test data, those skilled in the art can correspondingly modify the manner of outputting data based on the principle of inputting test data according to the present invention, and the manner of outputting data is not limited in any way.

The scan chain control circuit may use register input data (reg_scan_in [ n:0 ]) and input test data to the scan chain test circuit for testing under the action of a register Shift clock signal (shift_clk), and then output test completed test data (reg_scan_out [ n:0 ]) to an external device. It should be noted that the register input data is test data generated by a series of registers in the scan chain control circuit (e.g. register input data (reg_scan_in n: 0) in fig. 2, but specific registers are not shown) and is transmitted to the scan chain test circuit via the scan chain control circuit to complete the test (for this part, please refer to the description of fig. 2 and 6, and details thereof are not repeated here). Finally, the tested test data (Reg_scan_out [ n:0 ]) can be directly output to the external device through the lead terminal on the test circuit board, or can be transmitted to the scan chain control circuit through the test data (Reg_scan_out [ n:0 ]) and output to the external device through the Interface. The output principle after the completion of the test of the register input data (reg_scan_in [ n:0 ]) is similar to the explanation of the output principle of the test data (scan_out [ n:0 ]) after the completion of the test described above, and will not be repeated here.

In view of the above, the scan chain control circuit of the present invention can directly perform chip testing through wiring (also referred to as an interface) on a test circuit board when the chip is packaged on a PCB board, without performing testing through externally connecting leads to the lead terminals. Meanwhile, the SCAN chain control circuit can select pin input data (SCAN_IN [ n ] 0 ]) for testing and can also select register input data (Reg_scan_in [ n ] 0 ]) for testing. The accuracy of the test is improved, the flexibility of test selection is improved, and the test accuracy and efficiency can be greatly improved.

The present invention has been described in terms of the preferred embodiments only, so that those skilled in the art can better understand the present invention from various aspects, but various modifications and alterations can be made to the present invention by those skilled in the art without departing from the spirit and scope of the present invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A scan chain control circuit, comprising:

A register controller including a register clock control module outputting a register shift clock signal and a register mode control module outputting an enable clock signal;

A mode controller coupled to the register controller, receiving the enable clock signal, and outputting a mode scan enable clock signal;

A clock controller coupled to the register controller and the mode controller, receiving the register shift clock signal, the enable clock signal, and the mode scan enable clock signal, and outputting a shift clock signal; and

A data selector coupled to the scan chain test circuit and the register controller, wherein input pins of the scan chain test circuit are respectively coupled to a plurality of input terminals of the data selector, and test data is transmitted to the scan chain test circuit via the data selector,

Wherein, the input pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit, and the output pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit;

The chip test is performed through the interface on the test circuit board without the need of externally connecting leads through the lead end of the scan chain test circuit,

When the scan chain control circuit is under the action of the pin shift clock, the scan chain control circuit inputs pin input data to the scan chain test circuit, and after testing, the scan chain control circuit uniformly transmits the tested test data to the scan chain control circuit and outputs the test data through an interface on the test circuit board;

When the scan chain control circuit is under the action of the register shift clock signal, the scan chain control circuit inputs the register input data to the scan chain test circuit, and after the test is performed, the test data after the test is uniformly transmitted to the scan chain control circuit and is output through an interface on the test circuit board.

2. The scan chain control circuit of claim 1, wherein the scan chain control circuit is applicable to a joint test workgroup debug interface and/or a serial line debug interface.

3. The scan chain control circuit of claim 1, wherein said pin input data is uniformly transferred from said scan chain test circuit pin to said scan chain control circuit and then to said scan chain test circuit.

4. The scan chain control circuit of claim 1, wherein the scan chain control circuit is capable of generating the register input data by the scan chain control circuit and transmitting the register input data to the scan chain test circuit.

5. The scan chain control circuit of claim 3, wherein the test data after the pin input data test transmitted from the scan chain test circuit pins is uniformly transmitted to the scan chain control circuit and output via an interface on the test circuit board.

6. The scan chain control circuit according to claim 4, wherein test data generated by said scan chain control circuit after said register input data test is transmitted to said scan chain control circuit and output via an interface on said test circuit board.

7. The scan chain control circuit according to claim 1, wherein said scan chain control circuit outputs test data after testing said pin input data transmitted from said scan chain test circuit pins by a pin shift clock.

8. The scan chain control circuit according to claim 7, wherein in a case where the scan chain control circuit is operated in an original test mode, the scan chain control circuit outputs test data after testing the pin input data transferred from the scan chain test circuit pins by a pin shift clock.

9. The scan chain control circuit according to claim 8, wherein the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under the action of a register shift clock.

10. The scan chain control circuit of claim 9, wherein in a case where the scan chain control circuit is operated in a scan mode, the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under a register shift clock.

11. The scan chain control circuit of claim 10, wherein when said scan chain control circuit is operating in the original test mode, it is possible to switch to the scan mode by resetting the scan chain control circuit.

12. The scan chain control circuit of claim 10, wherein when the scan chain control circuit is operating in the scan mode, the scan chain control circuit can be switched to the original test mode by a reset operation and restarting.