CN112306140B - Back gate voltage bias circuit of fully depleted silicon-on-insulator - Google Patents
Back gate voltage bias circuit of fully depleted silicon-on-insulator Download PDFInfo
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- CN112306140B CN112306140B CN201910672410.3A CN201910672410A CN112306140B CN 112306140 B CN112306140 B CN 112306140B CN 201910672410 A CN201910672410 A CN 201910672410A CN 112306140 B CN112306140 B CN 112306140B
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
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Abstract
The invention provides a back gate voltage bias circuit of fully depleted silicon on insulator, comprising: a current source or sink providing a source current or sink current; the current mirror is used for mirroring the source current or the sink current; and the source of the load transistor is connected with the power supply voltage or the ground, the drain of the load transistor is connected with the output end of the current mirror, and the gate and the back gate of the load transistor are connected with the drain of the load transistor to generate a back gate bias voltage. The invention utilizes the characteristic of full-medium isolation of fully depleted silicon-on-insulator (FDSOI) to introduce a back gate into a circuit working loop, so that the circuit can work in a saturation region in a self-adaptive manner under the action of a mirror power supply and generate corresponding back gate working voltage; due to the complete symmetry and the back gate insulation characteristics of the circuit, the device can have the capability of working at a specified width-to-length ratio; the invention can enable a circuit designer to have a method for changing the working characteristics of the generated device, and simultaneously, the problems of complex setting and high cost of SOI body bias voltage are greatly solved.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a back gate voltage bias circuit of fully depleted silicon on insulator.
Background
Fully Depleted Silicon On Insulator (FDSOI) differs from conventional bulk Silicon processes in that there is no well structure in contact with the active region, but there is a back gate terminal under the Insulator. The back gate has similar electrical properties with the body region in the bulk silicon process, but the bulk silicon process needs to reverse bias the body region voltage to avoid forward conduction of the well, thereby limiting the application of the body region in the bulk silicon process.
Due to the particularities of the fully depleted silicon-on-insulator (FDSOI) structure itself, the neutral body region is no longer present and the body potential is not tapped off, but instead is the back gate potential with no latch-up risk. With the recent upgrade of semiconductor process, fully depleted silicon-on-insulator (soi) is considered to be a competitive product in the currently mainstream FinFET (Fin-Field-Effect Transistor) process due to its excellent performance. In addition to various excellent properties that are recognized, fully depleted silicon-on-insulator (FDSOI) offers the capability of back-gate modulation, i.e., faster device operation when forward back-gate biased and reduced device leakage when reverse back-gate biased. However, in practical engineering applications, since the requirements of the back gate voltage of the transistor are different at various places of the circuit, the generation of the multi-bias voltage is very complicated and requires a great area cost, and therefore, it is often difficult to provide the required back gate voltage in the circuit design. Therefore, at present, most of the circuits that successfully apply backgate control are based on small-scale control or large-scale overall backgate control.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a fully depleted silicon-on-insulator back gate voltage bias circuit, which is used to solve the problems of the prior art that a back gate control circuit is complicated and difficult to realize in a large scale.
To achieve the above and other related objects, the present invention provides a fully depleted silicon-on-insulator back gate voltage bias circuit, comprising at least:
a current source for providing a source current;
the input end of the current mirror is connected with the current source and is used for mirroring the source current;
the source of the load transistor is connected with a power supply voltage, the drain of the load transistor is connected with the output end of the current mirror, and the gate and the back gate of the load transistor are connected with the drain of the load transistor and generate a back gate bias voltage;
wherein the load transistor is a P-type fully depleted silicon-on-insulator transistor.
Optionally, the fully depleted silicon-on-insulator back gate voltage bias circuit further comprises a logic operation module connected between the drain and the back gate of the load transistor, wherein an input end of the logic operation module is connected to the drain of the load transistor, and an output end of the logic operation module is connected to the back gate of the load transistor.
More optionally, the logic operation module includes at least one of an operational amplifier module, a voltage offset module, and an inverting logic module.
More optionally, the current source includes a first P-type transistor, a source of the first P-type transistor is connected to a power supply voltage, a gate of the first P-type transistor is connected to a first preset voltage, and a drain of the first P-type transistor outputs the source current.
More optionally, the first P-type transistor is a fully depleted silicon-on-insulator transistor, and a back gate of the first P-type transistor is connected to a power supply voltage or ground.
More optionally, the current mirror includes a first N-type transistor and a second N-type transistor; the drain electrode of the first N-type transistor is connected with the output end of the current source, the grid electrode of the first N-type transistor is connected with the drain electrode of the first N-type transistor, and the source electrode of the first N-type transistor is grounded; and the drain electrode of the second N-type transistor is connected with the drain electrode of the load transistor, the grid electrode of the second N-type transistor is connected with the grid electrode of the first N-type transistor, and the source electrode of the second N-type transistor is grounded.
More optionally, the first N-type transistor and the second N-type transistor are fully depleted silicon-on-insulator transistors, and back gates of the first N-type transistor and the second N-type transistor are connected to a power supply voltage or ground.
To achieve the above and other related objects, the present invention provides a fully depleted silicon-on-insulator back gate voltage bias circuit, comprising at least:
a current sink for providing a sink current;
the input end of the current mirror is connected with the current sink and is used for mirroring the sink current;
the source of the load transistor is grounded, the drain of the load transistor is connected with the output end of the current mirror, and the gate and the back gate of the load transistor are connected with the drain of the load transistor and generate a back gate bias voltage;
wherein the load transistor is an N-type fully depleted silicon-on-insulator transistor.
Optionally, the fully depleted silicon-on-insulator back gate voltage bias circuit further comprises a logic operation module connected between the drain and the back gate of the load transistor, wherein an input end of the logic operation module is connected to the drain of the load transistor, and an output end of the logic operation module is connected to the back gate of the load transistor.
More optionally, the logic operation module includes at least one of an operational amplifier module, a voltage offset module, and an inverting logic module.
More optionally, the current sink includes a third N-type transistor, a source of the third N-type transistor is grounded, a gate of the third N-type transistor is connected to a second preset voltage, and a drain of the third N-type transistor outputs the sink current.
More optionally, the third N-type transistor is a fully depleted silicon-on-insulator transistor, and a back gate of the third N-type transistor is connected to a power supply voltage or ground.
More optionally, the current mirror includes a second P-type transistor and a third P-type transistor; the drain electrode of the second P-type transistor is connected with the output end of the current sink, the grid electrode of the second P-type transistor is connected with the drain electrode of the second P-type transistor, and the source electrode of the second P-type transistor is connected with power supply voltage; and the drain electrode of the third P-type transistor is connected with the drain electrode of the load transistor, the grid electrode of the third P-type transistor is connected with the grid electrode of the second P-type transistor, and the source electrode of the third P-type transistor is connected with a power supply voltage.
More optionally, the second P-type transistor and the third P-type transistor are fully depleted silicon-on-insulator transistors, and back gates of the second P-type transistor and the third P-type transistor are connected to a power supply voltage or ground.
As described above, the fully depleted silicon-on-insulator back gate voltage bias circuit of the present invention has the following beneficial effects:
the back gate voltage bias circuit of the fully depleted silicon-on-insulator (FDSOI) of the invention utilizes the characteristic of full medium isolation of the fully depleted silicon-on-insulator (FDSOI) to introduce the back gate into a circuit working loop, and the circuit can work in a saturation region in a self-adaptive manner under the action of a mirror power supply and generate corresponding back gate working voltage; due to the complete symmetry and the back gate insulation characteristics of the circuit, the device can have the capability of working at a specified width-to-length ratio; the invention can enable a circuit designer to have a method for changing the working characteristics of the generated device, and simultaneously, the problems of complex setting and high cost of SOI body bias voltage are greatly solved.
Drawings
Fig. 1 shows one implementation of the fully depleted silicon-on-insulator back gate voltage bias circuit of the present invention.
Fig. 2 shows another implementation of the fully depleted silicon-on-insulator back gate voltage bias circuit of the present invention.
Fig. 3 shows yet another implementation of the fully depleted silicon-on-insulator back gate voltage bias circuit of the present invention.
Description of the element reference numerals
Back gate voltage bias circuit of 1 fully depleted silicon on insulator
11a current source
12a current mirror
13a load transistor
11b Current sink
12b current mirror
13b load transistor
14 logic operation module
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 1, the present embodiment provides a fully depleted silicon-on-insulator back gate voltage bias circuit 1, where the fully depleted silicon-on-insulator back gate voltage bias circuit 1 includes:
a current source 11a, a current mirror 12a and a load transistor 13 a.
As shown in fig. 1, the current source 11a (current source) is used to provide a source current (or called a source current).
Specifically, in the present embodiment, the current source 11a includes a first P-type transistor PM1, and the first P-type transistor PM1 is a fully depleted silicon-on-insulator transistor. The source of the first P-type transistor PM1 is connected to a power supply voltage Vdd, the gate is connected to a first preset voltage Vs1, the drain outputs the source current, and the back gate is connected to the power supply voltage Vdd or the ground Gnd.
It should be noted that the current source 11a may adopt any circuit structure capable of generating a source current, including but not limited to a single-transistor silicon-on-insulator transistor, and the connection relationship may be adaptively adjusted based on an actual device structure, which is not described herein again.
As shown in fig. 1, the input terminal of the current mirror 12a is connected to the current source 11a, and the output terminal is connected to the load transistor 13a, for mirroring (equal or set proportion) the source current.
Specifically, in the present embodiment, the current mirror 12a includes a first N-type transistor NM1 and a second N-type transistor NM2, and the first N-type transistor NM1 and the second N-type transistor NM2 are fully depleted silicon-on-insulator transistors. A drain of the first N-type transistor NM1 is connected to the output terminal of the current source 11a, a gate thereof is connected to the drain of the first N-type transistor NM1, a source thereof is grounded Gnd, and a back gate thereof is grounded Gnd; the second N-type transistor NM2 has a drain connected to the drain of the load transistor 13a, a gate connected to the gate of the first N-type transistor NM1, a source grounded Gnd, and a back gate grounded Gnd.
Note that, the back gates of the first N-type transistor NM1 and the second N-type transistor NM2 may be connected to the power supply voltage Vdd, and may be set based on actual needs, which is not limited to this embodiment.
It should be noted that the current mirror 12a may adopt any circuit structure capable of mirroring current, including but not limited to a silicon-on-insulator transistor, and may adaptively adjust a connection relationship based on an actual device structure, which is not described herein again.
As shown in fig. 1, the load transistor 13a is connected to the output terminal of the current mirror 12a for generating the back-gate bias voltage Vbias.
Specifically, the load transistor 13a is a P-type fully depleted silicon-on-insulator transistor. In this embodiment, the source of the load transistor 13a is connected to a power supply voltage Vdd, the drain is connected to the output terminal of the current mirror 12a, and the gate and back gate are connected to the drain of the load transistor 13a to output the back gate bias voltage Vbias.
Specifically, the back-gate bias voltage Vbias at a set current is generated at the drain of the load transistor 13a based on the current output from the current mirror 12 a.
Meanwhile, the back gate bias voltage Vbias acts on the back gate of the load transistor 13a, the width-to-length ratio of the load transistor 13a is adjusted based on the back gate bias voltage Vbias, and further the working characteristics of the load transistor 13a are changed, so that different back gate bias voltages Vbias and circuit performance are obtained without replacing devices. As an implementation of the present invention, the width-to-length ratio (size) of the load transistor 13a is changed by the adjustment of the back-gate bias voltage Vbias to further adjust the back-gate bias voltage Vbias; as another implementation of the present invention, when the width-to-length ratio of the first P-type transistor PM1 does not match the width-to-length ratio of the load transistor 13a (assuming that the width-to-length ratio of the first P-type transistor PM1 is large, the width-to-length ratio of the load transistor 13a is small), the width-to-length ratio of the load transistor 13a is adjusted based on the back-gate bias voltage Vbias (the back-gate bias voltage Vbias is increased to increase the width-to-length ratio of the load transistor 13 a), so that the width-to-length ratios of the two devices match, and the circuit performance is improved. For the voltage requirement of multiple bias points, a complex circuit structure is not needed, a large number of layout areas are not occupied, and the cost is greatly reduced.
Example two
As shown in fig. 2, the present embodiment provides a fully depleted silicon-on-insulator back gate voltage bias circuit 1, which is different from the first embodiment in that the fully depleted silicon-on-insulator back gate voltage bias circuit employs a device of the type opposite to that of the first embodiment.
The fully depleted silicon-on-insulator back gate voltage bias circuit 1 includes a current sink 11b, a current mirror 12b and a load transistor 13 b.
As shown in fig. 2, the current sink 11b (current sink) is used to provide a sink current (or referred to as a sink current).
Specifically, in the present embodiment, the current sink 11b includes a third N-type transistor NM3, and the third N-type transistor NM3 is a fully depleted silicon-on-insulator transistor. The source of the third N-type transistor NM3 is grounded Gnd, the gate is connected to a second preset voltage Vs2, the drain outputs the sink current, and the back gate is connected to a power supply voltage Vdd or grounded Gnd.
As shown in fig. 2, the input terminal of the current mirror 12b is connected to the current sink 11b, and the output terminal thereof is connected to the load transistor 13b, for mirroring (equal proportion or set proportion) the sink current.
Specifically, in the present embodiment, the current mirror 12b includes a second P-type transistor PM2 and a third P-type transistor PM3, and the second P-type transistor PM2 and the third P-type transistor PM3 are fully depleted silicon-on-insulator transistors. The drain of the second P-type transistor PM2 is connected to the output end of the current sink 11b, the gate is connected to the drain of the second P-type transistor PM2, the source is connected to the power supply voltage Vdd, and the back gate is connected to the power supply voltage Vdd; the third P-type transistor PM3 has a drain connected to the drain of the load transistor 13b, a gate connected to the gate of the second P-type transistor PM2, a source connected to the power supply voltage Vdd, and a back gate connected to the power supply voltage Vdd.
The back gates of the second P-type transistor PM2 and the third P-type transistor PM3 may be grounded Gnd, which may be set based on actual needs, but are not limited to this embodiment.
As shown in fig. 2, the load transistor 13b is connected to the output terminal of the current mirror 12b for generating the back-gate bias voltage Vbias.
Specifically, the load transistor 13b is an N-type fully depleted silicon-on-insulator transistor. In this embodiment, the source of the load transistor 13b is grounded Gnd, the drain is connected to the output terminal of the current mirror 12b, and the gate and the back gate are connected to the drain of the load transistor 13b to output the back gate bias voltage Vbias.
The principle of the back gate voltage bias circuit of fully depleted soi of this embodiment is the same as that of the first embodiment, and therefore, the details are not repeated here.
EXAMPLE III
As shown in fig. 3, the present embodiment provides a fully depleted silicon-on-insulator back gate voltage bias circuit 1, which is different from the first embodiment in that the fully depleted silicon-on-insulator back gate voltage bias circuit 1 further includes a logic operation module 14 connected between the drain and the back gate of the load transistor 13 a.
Specifically, the input end of the logic operation module 14 is connected to the drain of the load transistor 13a, and the output end is connected to the back gate of the load transistor 13a, so as to output the drain voltage of the load transistor 13a to the back gate of the load transistor 13a after logic operation, thereby adjusting the back gate of the load transistor 13a and obtaining the corresponding back gate bias voltage Vbias.
It should be noted that the logic operation module 14 includes any one or a combination of several logics, including but not limited to amplification, inversion, and offset (a set amount is increased or decreased on the drain voltage of the load transistor 13a to realize offset). Any circuit structure capable of implementing corresponding logic is suitable for the logic operation module 14 of the present invention, including but not limited to an operational amplifier module, a voltage offset module and an inverting logic module, which are not described herein in detail.
It should be noted that the logic operation module 14 is also applicable to the second embodiment, and is not described herein again.
In summary, the present invention provides a back gate voltage bias circuit for fully depleted silicon on insulator, including: a current source for providing a source current; the input end of the current mirror is connected with the current source and is used for mirroring the source current; the source of the load transistor is connected with a power supply voltage, the drain of the load transistor is connected with the output end of the current mirror, and the gate and the back gate of the load transistor are connected with the drain of the load transistor and generate a back gate bias voltage; wherein the load transistor is a P-type fully depleted silicon-on-insulator transistor. Or comprises the following steps: a current sink for providing a sink current; the input end of the current mirror is connected with the current sink and is used for mirroring the sink current; the source of the load transistor is grounded, the drain of the load transistor is connected with the output end of the current mirror, and the gate and the back gate of the load transistor are connected with the drain of the load transistor and generate a back gate bias voltage; wherein the load transistor is an N-type fully depleted silicon-on-insulator transistor. The back gate voltage bias circuit of the fully depleted silicon-on-insulator (FDSOI) of the invention utilizes the characteristic of full medium isolation of the fully depleted silicon-on-insulator (FDSOI) to introduce the back gate into a circuit working loop, and the circuit can work in a saturation region in a self-adaptive manner under the action of a mirror power supply and generate corresponding back gate working voltage; due to the complete symmetry and the back gate insulation characteristics of the circuit, the device can have the capability of working at a specified width-to-length ratio; the invention can enable a circuit designer to have a method for changing the working characteristics of the generated device, and simultaneously, the problems of complex setting and high cost of SOI body bias voltage are greatly solved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. A fully depleted silicon-on-insulator back gate voltage bias circuit, comprising at least:
a current source for providing a source current;
the input end of the current mirror is connected with the current source and is used for mirroring the source current;
the source electrode of the load transistor is connected with power supply voltage, the drain electrode of the load transistor is connected with the output end of the current mirror, and the grid electrode of the load transistor is connected with the drain electrode of the load transistor;
the input end of the logic operation module is connected with the drain electrode of the load transistor, and the output end of the logic operation module is connected with the back gate of the load transistor and generates a back gate bias voltage;
wherein the load transistor is a P-type fully depleted silicon-on-insulator transistor.
2. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 1, wherein: the logic operation module comprises at least one of an operation amplification module, a voltage offset module and an inversion logic module.
3. The fully depleted silicon-on-insulator back gate voltage bias circuit of any of claims 1-2, wherein: the current source comprises a first P-type transistor, the source electrode of the first P-type transistor is connected with a power supply voltage, the grid electrode of the first P-type transistor is connected with a first preset voltage, and the drain electrode of the first P-type transistor outputs the source current.
4. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 3, wherein: the first P type transistor is a fully depleted silicon-on-insulator transistor, and the back gate of the first P type transistor is connected with a power supply voltage or ground.
5. The fully depleted silicon-on-insulator back gate voltage bias circuit of any of claims 1-2, wherein: the current mirror comprises a first N-type transistor and a second N-type transistor; the drain electrode of the first N-type transistor is connected with the output end of the current source, the grid electrode of the first N-type transistor is connected with the drain electrode of the first N-type transistor, and the source electrode of the first N-type transistor is grounded; and the drain electrode of the second N-type transistor is connected with the drain electrode of the load transistor, the grid electrode of the second N-type transistor is connected with the grid electrode of the first N-type transistor, and the source electrode of the second N-type transistor is grounded.
6. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 5, wherein: the first N-type transistor and the second N-type transistor are fully depleted silicon-on-insulator transistors, and back gates of the first N-type transistor and the second N-type transistor are connected with a power supply voltage or ground.
7. A fully depleted silicon-on-insulator back gate voltage bias circuit, comprising at least:
a current sink for providing a sink current;
the input end of the current mirror is connected with the current sink and is used for mirroring the sink current;
the source electrode of the load transistor is grounded, the drain electrode of the load transistor is connected with the output end of the current mirror, and the grid electrode of the load transistor is connected with the drain electrode of the load transistor;
the input end of the logic operation module is connected with the drain electrode of the load transistor, and the output end of the logic operation module is connected with the back gate of the load transistor and generates a back gate bias voltage;
wherein the load transistor is an N-type fully depleted silicon-on-insulator transistor.
8. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 7, wherein: the logic operation module comprises at least one of an operation amplification module, a voltage offset module and an inversion logic module.
9. The fully depleted silicon-on-insulator back gate voltage bias circuit of any of claims 7 to 8, wherein: the current sink comprises a third N-type transistor, the source electrode of the third N-type transistor is grounded, the grid electrode of the third N-type transistor is connected with a second preset voltage, and the drain electrode of the third N-type transistor outputs the sink current.
10. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 9, wherein: the third N-type transistor is a fully depleted silicon-on-insulator transistor, and the back gate of the third N-type transistor is connected with a power supply voltage or ground.
11. The fully depleted silicon-on-insulator back gate voltage bias circuit of any of claims 7 to 8, wherein: the current mirror comprises a second P-type transistor and a third P-type transistor; the drain electrode of the second P-type transistor is connected with the output end of the current sink, the grid electrode of the second P-type transistor is connected with the drain electrode of the second P-type transistor, and the source electrode of the second P-type transistor is connected with power supply voltage; and the drain electrode of the third P-type transistor is connected with the drain electrode of the load transistor, the grid electrode of the third P-type transistor is connected with the grid electrode of the second P-type transistor, and the source electrode of the third P-type transistor is connected with a power supply voltage.
12. The fully depleted silicon-on-insulator back gate voltage bias circuit of claim 11, wherein: the second P-type transistor and the third P-type transistor are fully depleted silicon-on-insulator transistors, and back gates of the second P-type transistor and the third P-type transistor are connected with a power supply voltage or ground.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103955250A (en) * | 2014-03-18 | 2014-07-30 | 尚睿微电子（上海）有限公司 | Bandgap reference circuit with high power supply rejection ratio |
| US20150301540A1 (en) * | 2013-06-27 | 2015-10-22 | Stmicroelectronics Pvt Ltd | Capless on chip voltage regulator using adaptive bulk bias |
| US20170288531A1 (en) * | 2016-03-31 | 2017-10-05 | Nxp B.V. | Charge pump circuit and method for operating a charge pump circuit |
| US10054974B1 (en) * | 2017-04-06 | 2018-08-21 | Globalfoundries Inc. | Current mirror devices using cascode with back-gate bias |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1709741B1 (en) * | 2004-01-19 | 2008-08-20 | Nxp B.V. | Mos switching circuit |
| US9306550B2 (en) * | 2014-03-17 | 2016-04-05 | Stmicroelectronics International N.V. | Schmitt trigger in FDSOI technology |
-
2019
- 2019-07-24 CN CN201910672410.3A patent/CN112306140B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150301540A1 (en) * | 2013-06-27 | 2015-10-22 | Stmicroelectronics Pvt Ltd | Capless on chip voltage regulator using adaptive bulk bias |
| CN103955250A (en) * | 2014-03-18 | 2014-07-30 | 尚睿微电子（上海）有限公司 | Bandgap reference circuit with high power supply rejection ratio |
| US20170288531A1 (en) * | 2016-03-31 | 2017-10-05 | Nxp B.V. | Charge pump circuit and method for operating a charge pump circuit |
| US10054974B1 (en) * | 2017-04-06 | 2018-08-21 | Globalfoundries Inc. | Current mirror devices using cascode with back-gate bias |
Non-Patent Citations (2)
| Title |
|---|
| 8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing;Sylvain Clerc et al.;《2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers》;20151231;全文 * |
| 全耗尽SOIMOSFET及CMOS／SOI电路的研究;张正璠等;《微电子学》;19960630;第26卷(第3期);全文 * |
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| CN112306140A (en) | 2021-02-02 |
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