CN112290909A - High-performance crystal driving circuit - Google Patents
High-performance crystal driving circuit Download PDFInfo
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- CN112290909A CN112290909A CN201910658618.XA CN201910658618A CN112290909A CN 112290909 A CN112290909 A CN 112290909A CN 201910658618 A CN201910658618 A CN 201910658618A CN 112290909 A CN112290909 A CN 112290909A
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- 239000003990 capacitor Substances 0.000 claims description 33
- 238000001514 detection method Methods 0.000 claims description 19
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- 230000010355 oscillation Effects 0.000 description 4
- 230000008878 coupling Effects 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
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Abstract
The invention discloses a high-performance crystal driving circuit, and relates to the technical field of integrated circuits. The circuit comprises a sub-circuit of a starting sub-circuit, a sub-circuit of an amplitude regulator, a sub-circuit of an oscillator, an operational amplifier sub-circuit, a sub-circuit of a trigger and an output sub-circuit; the amplitude regulator sub-circuit is connected with the oscillator sub-circuit and is used for adjusting to reduce the amplitude of an output signal of the oscillator sub-circuit, the operational amplifier sub-circuit is connected with the oscillator sub-circuit and the output sub-circuit, and the operational amplifier sub-circuit amplifies the output signal of the oscillator sub-circuit and is output by the output sub-circuit; the flip-flop sub-circuit is connected to the oscillator sub-circuit and the output sub-circuit. The high-performance crystal driving circuit can select two modes of active input and passive crystal input through the trigger subcircuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-performance crystal driving circuit.
Background
Since the 20 th generation of the last century, the theoretical research and manufacturing level of the crystal driver are rapidly developed, and all performance indexes are remarkably improved. As one of clock frequency sources, crystal oscillators are widely used in military and consumer electronics fields because of their superior Q values, frequency accuracies, stabilities, and the like, as compared with other types of oscillators. In the field of integrated circuits, the role of an IO interface integrated circuit is crucial in order to effectively and reasonably transmit a crystal frequency signal to a chip core. With the increasing requirements on the crystal driving circuit, the low power supply becomes a trend, and especially the low power supply to a single dry battery is a bottleneck in designing the existing structure.
Disclosure of Invention
The invention mainly aims to provide a high-performance crystal driving circuit, aiming at solving the problems in the prior art.
In order to achieve the above object, the present invention provides a high performance crystal driving circuit, which comprises a sub-circuit of a start amplifier, a sub-circuit of an amplitude regulator, a sub-circuit of an oscillator, an operational amplifier, a sub-circuit of a trigger, and an output sub-circuit; the amplitude regulator sub-circuit is connected with the oscillator sub-circuit and is used for adjusting to reduce the amplitude of an output signal of the oscillator sub-circuit, the operational amplifier sub-circuit is connected with the oscillator sub-circuit and the output sub-circuit, and the operational amplifier sub-circuit amplifies the output signal of the oscillator sub-circuit and is output by the output sub-circuit; the trigger sub-circuit is connected to the oscillator sub-circuit and the output sub-circuit, and when the oscillator sub-circuit receives an active clock signal, the trigger sub-circuit is switched on, shapes the active clock signal and then sends the active clock signal to the output sub-circuit.
Preferably, the high performance driving circuit further includes a vibration-down detection sub-circuit, and the vibration-down detection sub-circuit is connected to the output sub-circuit, receives an output signal of the output sub-circuit, and outputs a detection result.
Preferably, the flip-flop sub-circuit comprises a first signal input, a second signal input, a third signal input and a first output;
the first signal input end is connected to the first enable signal end to receive a first enable signal; the second signal input end is connected to the first enable signal end through a first inverter and used for receiving an inverted signal of the first enable signal; the third signal input terminal is connected to the oscillator sub-circuit, and the first output terminal is connected to the output sub-circuit.
Preferably, the trigger sub-circuit is a schmitt trigger.
Preferably, the starting circuit is connected to the first enable signal terminal, and the starting circuit receives the first enable signal input by the first enable signal terminal to provide the starting voltage for the subsequent circuit.
Preferably, the oscillator sub-circuit includes a crystal, one end of the crystal is connected with a first capacitor, the other end of the crystal is connected with a second capacitor and a first NMOS transistor, a drain of the first NMOS transistor is connected to the regulator sub-circuit, a source of the first NMOS transistor is connected to the first capacitor and the second capacitor, and a gate of the first NMOS transistor is connected to the regulator sub-circuit.
The high-performance crystal driving circuit comprises a starting sub-circuit, an amplitude regulator sub-circuit, an oscillator sub-circuit, an operational amplifier sub-circuit, a trigger sub-circuit and an output sub-circuit, wherein the trigger sub-circuit enables the circuit to select two modes of active input and passive crystal input, and when an active clock signal is input into the oscillator sub-circuit, the trigger sub-circuit processes the active clock signal and then sends the active clock signal to the output sub-circuit.
Drawings
FIG. 1 is a schematic diagram of a high performance crystal driver circuit according to the present invention;
FIG. 2 is a schematic diagram of an oscillator sub-circuit in the high performance crystal driver circuit of the present invention;
FIG. 3 is a schematic diagram of an amplitude regulator sub-circuit in the high performance transistor driver circuit according to the present invention;
FIG. 4 is a schematic diagram of a stop-oscillation detection sub-circuit of the high performance transistor driving circuit according to the present invention;
FIG. 5 is a schematic diagram of a promoter circuit in the high performance crystal driver circuit of the present invention;
FIG. 6 is a schematic diagram of a flip-flop sub-circuit in the high performance crystal driver circuit of the present invention;
FIG. 7 is a schematic diagram of a passive input mode of operation according to an embodiment of the present invention;
fig. 8 is a schematic diagram of the active input operation mode in the embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention is further described below with reference to the accompanying drawings.
A high-performance crystal driving circuit is disclosed, as shown in figure 1, and comprises a starting sub-circuit, an amplitude regulator sub-circuit, an oscillator sub-circuit, an operational amplifier sub-circuit, a trigger sub-circuit and an output sub-circuit; the amplitude regulator sub-circuit is connected with the oscillator sub-circuit and is used for adjusting to reduce the amplitude of an output signal of the oscillator sub-circuit, the operational amplifier sub-circuit is connected with the oscillator sub-circuit and the output sub-circuit, and the operational amplifier sub-circuit amplifies the output signal of the oscillator sub-circuit and is output by the output sub-circuit; the trigger sub-circuit is connected to the oscillator sub-circuit and the output sub-circuit, and when the oscillator sub-circuit receives an active clock signal, the trigger sub-circuit is switched on, shapes the active clock signal and then sends the active clock signal to the output sub-circuit.
As shown in fig. 2, the oscillator sub-circuit includes a crystal, one end of the crystal is connected with a first capacitor, the other end of the crystal is connected with a second capacitor and a first NMOS transistor, a drain of the first NMOS transistor is connected to the regulator sub-circuit, a source of the first NMOS transistor is connected to the first capacitor and the second capacitor, and a gate of the first NMOS transistor is connected to the regulator sub-circuit.
Preferably, the crystals are 32.768K crystals.
The embodiment of the invention comprises a sub-circuit of the amplitude regulator of the starting sub-circuit, a sub-circuit of the oscillator, an operational amplifier sub-circuit, a sub-circuit of the trigger and an output sub-circuit, which are used for driving the 32.768K crystal, and in some embodiments, two modes of active input or passive crystal input can be selected. In a passive input mode, the power consumption of the power supply is extremely low, the power supply consumes only 150nA of current under normal temperature and pressure TT corner and a load capacitor 18p, the establishing time is 100ms, the stabilizing time is 300ms, the duty ratio of the clock frequency is 50 percent, and the power supply has positive and negative 2 percent and extremely good performance.
As shown in fig. 3, the amplitude regulator sub-circuit includes a first PMOS transistor Mp1, a second PMOS transistor Mp2, a third PMOS transistor Mp3, a fourth PMOS transistor Mp4, a fifth PMOS transistor Mp5, a sixth PMOS transistor Mp6, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, the first PMOS transistor Mp1 is connected to the power supply and the second PMOS transistor Mp2, the third PMOS transistor Mp3 is connected to the first NMOS transistor Mn1 in the oscillator sub-circuit through the third capacitor C3, the fourth PMOS transistor Mp4 is connected to the power supply through the fourth capacitor C4, the fifth PMOS transistor Mp5 is connected to the fourth PMOS transistor Mp4 and to the power supply through the fifth capacitor C5, and the sixth PMOS transistor Mp6 is connected to the fifth PMOS transistor Mp5 and the sixth PMOS transistor Mp1 and connected to the power supply through the first capacitor C6 and the sixth capacitor C1.
In the working state of the amplitude regulator sub-circuit, when the amplitude regulator sub-circuit is not excited, the gate voltage of the sixth PMOS transistor Mp6 is quite low, and a large current flows through the first NMOS transistor Mn 1. When the oscillator sub-circuit starts to operate, more and more current flows through the third PMOS transistor Mp3, thereby increasing the gate voltage of the sixth PMOS transistor Mp 6. After a while, the current on the third PMOS transistor Mp3 and the first NMOS transistor Mn1 starts to decrease. To achieve equalization, the regulator subcircuit maintains the minimum current required for the oscillator to operate.
The source electrode of the first PMOS tube Mp1 is connected with a power supply, and the grid electrode and the drain electrode are connected with the source electrode of the second PMOS tube Mp 2; the drain electrode of the second PMOS tube Mp2 is connected with a second NMOS tube Mn2, and the gate electrode of the second PMOS tube Mp2 is connected with the gate electrodes of a fourth PMOS tube Mp4 and a fifth PMOS tube Mp 5; the gate of the third PMOS transistor Mp3 is connected to one end of the third capacitor C3, the source is connected to the power supply, the drain is connected to a third NMOS transistor Mn3, and the other end of the third capacitor C3 is connected to the gate of the first NMOS transistor Mn 1; the source electrode of the fourth PMOS tube Mp4 is connected to the drain electrode of the fifth PMOS tube Mp5, and the drain electrode is connected to the fourth capacitor C4; the source electrode of the fifth PMOS tube Mp5 is connected to the fifth capacitor C5, and the drain electrode is connected to the sixth capacitor C6 and the gate electrode of the sixth PMOS tube Mp 6; the source of the sixth PMOS transistor Mp6 is connected to the first resistor R1, and the drain is connected to a fourth NMOS transistor Mn 4.
The drain of the second NMOS transistor Mn2 is connected to the drain and gate of the second PMOS transistor Mp2, the source is grounded, the gate is connected to the gates of the third NMOS transistor Mn3 and the fourth NMOS transistor Mn4 and is also connected to the drain of the sixth PMOS transistor Mp6, the drain of the third NMOS transistor Mn3 is connected to the drain of the third PMOS transistor Mp3, the source is grounded, and the drain of the fourth NMOS transistor Mn4 is connected to the drain of the sixth PMOS transistor Mp6, and the source is grounded.
Preferably, the high performance driving circuit further includes a vibration-down detection sub-circuit, and the vibration-down detection sub-circuit is connected to the output sub-circuit, receives an output signal of the output sub-circuit, and outputs a detection result. The working state of the high-performance driving circuit can be conveniently judged by a user.
Specifically, as shown IN fig. 4, the oscillation-stop detection sub-circuit is connected to the output sub-circuit through the CLK _ IN terminal thereof and receives the clock signal, and the oscillation-stop detection sub-circuit outputs the detection result through the TOUT terminal thereof. When the CLK _ IN end of the oscillation stop detection sub-circuit receives the clock signal output by the output sub-circuit, the oscillation stop detection sub-circuit detects the clock and outputs an indication signal '1' at the TOUT end; when the crystal of the oscillator sub-circuit stops oscillating and the CLK _ IN terminal does not receive the clock signal, the TOUT terminal outputs an indication signal '0'; namely, whether the high-performance driving circuit stops vibrating can be judged by judging the indication signal '1' or the indication signal '0' output by the vibration stopping detection sub-circuit.
Preferably, the promoter circuit is connected to the first enable signal terminal XTAL _ EN, and receives the first enable signal input from the first enable signal terminal XTAL _ EN to provide the start voltage for the subsequent circuits.
As shown in fig. 5, the promoter circuit includes a seventh PMOS transistor Mp7, an eighth PMOS transistor Mp8 connected to the first enable signal terminal XTAL _ EN, a ninth PMOS transistor Mp9 connected to the eighth PMOS transistor Mp8, and a tenth PMOS transistor Mp10 connected to the ninth PMOS transistor Mp 9; the promoter circuit further comprises a second resistor R2 connected with the first PMOS tube Mp1, a fifth NMOS tube Mn5 and a seventh capacitor C7 connected with the second resistor R2, and a sixth NMOS tube Mn6 connected with the tenth PMOS tube Mp 10; the output end of the starting up circuit is connected with the tenth PMOS tube Mp10 and the sixth NMOS tube Mn6 to provide starting voltage for the amplitude regulator sub circuit.
When the first enable signal is switched from high to low, the seventh PMOS transistor Mp7 and the eighth PMOS transistor Mp8 start to be turned on, and the level of the output terminal XO gradually changes from high to low by charging and discharging the seventh capacitor C7, so that the starting purpose is achieved.
The gates of the seventh and eighth PMOS transistors Mp7 and Mp8 are connected to the first enable signal terminal XTAL _ EN, which receives an enable signal to turn on the seventh and eighth PMOS transistors Mp7 and Mp 8; the source of the seventh PMOS transistor Mp7 is connected to the power supply, the drain of the seventh PMOS transistor Mp7 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the gate of the ninth PMOS transistor Mp9, the gate of the tenth PMOS transistor Mp10, the drain of the fifth NMOS transistor Mn5, and one end of a seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded; the source electrode of the eighth PMOS tube Mp8 is connected to the power supply, and the drain electrode is connected to the source electrode of the ninth PMOS tube Mp 9; the drain of the ninth PMOS transistor Mp9 is connected to the source of the tenth PMOS transistor Mp10, and the drain of the tenth PMOS transistor Mp10 is connected to the drain of the sixth NMOS transistor Mn 6; the sources of the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6 are grounded, and the gates of the fifth NMOS transistor Mn5 and the sixth NMOS transistor Mn6 are connected to each other and to the first enable signal terminal XTAL _ EN.
Preferably, the flip-flop sub-circuit comprises a first signal input, a second signal input, a third signal input and a first output; the first signal input end is connected to a first enable signal end XTAL _ EN to receive a first enable signal; the second signal input end is connected to the first enable signal end XTAL _ EN through a first inverter and is configured to receive an inverted signal of the first enable signal; the third signal input terminal is connected to the oscillator sub-circuit, and the first output terminal is connected to the output sub-circuit.
Preferably, the trigger sub-circuit is a schmitt trigger.
As shown in fig. 6, the flip-flop sub-circuit includes a first fet M1, a second fet M2, a third fet M3, a fourth fet M4, a fifth fet M5 and a sixth fet M6 connected in sequence, a seventh fet M7 connected to the second fet M2 and the third fet M3, and an eighth fet M8 connected to the fourth fet M4, the fifth fet M5 and the seventh fet M7.
Specifically, the gate of the first fet M1 is connected to the first enable signal terminal through an inverter, and is configured to receive the inverted signal XTAL _ ENN of the first enable signal. The gate of the sixth fet M6 is connected to the first enable signal terminal XTAL _ EN to receive the first enable signal. The third fet M3, the fourth fet M4, the seventh fet M7 and the eighth fet M8 are connected to the input terminal Sout of the output sub-circuit.
Preferably, the output sub-circuit receives signals sent by the operational amplifier sub-circuit and the trigger sub-circuit for selective output.
In a specific embodiment, the output sub-circuit is an output sub-circuit of a MUX selector structure. When the signals of the operational amplifier sub-circuit and the flip-flop sub-circuit are transmitted to the output sub-circuit, the output is selected by setting the second enable signal MUX _ SEL.
In a specific embodiment, the high-performance driving circuit comprises two working modes of active input and passive input.
As shown in fig. 7, in the passive input operation mode, the 32.728K crystal of the present embodiment is connected between the terminal X0 and the terminal X1, and is hung on the load capacitors C0 and C1, where C0= C1=10p, the first enable signal XTAL _ EN changes from high to low 1ns after the power is turned on, and the second enable signal MUX _ SEL is low. The working principle is as follows: when the first enable signal XTAL _ EN is powered on, the amplitude-stabilizing sub-circuit is turned on and makes the transistor Mn obtain an initial current, at this time, the transistor Mn resonates with the crystal, and sine wave signals with large amplitude, i.e., output signals of the oscillator sub-circuit, can be detected at the X0 terminal and the X1 terminal; the sine wave signal at the X0 end is fed back and sent to the amplitude voltage-stabilizing sub-circuit, and the drain current flowing through the transistor Mn is reduced through the voltage-stabilizing regulation effect of the amplitude voltage-stabilizing sub-circuit, so that the amplitude at the X0 end is reduced; in addition, the sine wave signal at the end X0 is sent to an operational amplifier sub-circuit through a coupling capacitor Cc, so that the amplitude of the signal is amplified and the driving capability is increased; the amplified signal is sent to the output sub-circuit, and the output sub-circuit selectively outputs 32.768K clocks, at this time, the oscillation stop detection sub-circuit detects that a clock signal exists, and outputs a detection signal '1'.
As shown in fig. 8, in the active input operation mode, an active 32.768K clock is input to the X0 terminal, the first enable signal XTAL _ EN is high, and the second enable signal MUX _ SEL is high. The working principle is as follows: when an active 32.768K clock is input into the XO end, the trigger sub-circuit is switched on, a clock signal is sent to the output sub-circuit, the 32.768K clock is selected and output through the output sub-circuit, and the oscillation stop detection circuit detects the clock signal and outputs a detection signal '1' as in a passive input working mode.
It should be understood that the above is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent structures or equivalent flow transformations made by the present specification and drawings, or applied directly or indirectly to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. A high-performance crystal driving circuit is characterized in that the high-performance crystal driving circuit comprises a starting sub-circuit, an amplitude regulator sub-circuit, an oscillator sub-circuit, an operational amplifier sub-circuit, a trigger sub-circuit and an output sub-circuit; the amplitude regulator sub-circuit is connected with the oscillator sub-circuit and is used for adjusting to reduce the amplitude of an output signal of the oscillator sub-circuit, the operational amplifier sub-circuit is connected with the oscillator sub-circuit and the output sub-circuit, and the operational amplifier sub-circuit amplifies the output signal of the oscillator sub-circuit and is output by the output sub-circuit; the trigger sub-circuit is connected to the oscillator sub-circuit and the output sub-circuit, and when the oscillator sub-circuit receives an active clock signal, the trigger sub-circuit is switched on, shapes the active clock signal and then sends the active clock signal to the output sub-circuit.
2. The high-performance crystal driving circuit according to claim 1, further comprising a vibration-down detection sub-circuit connected to the output sub-circuit, receiving an output signal of the output sub-circuit, and outputting a detection result.
3. The high-performance crystal driving circuit according to claim 2, wherein the flip-flop sub-circuit comprises a first signal input terminal, a second signal input terminal, a third signal input terminal, and a first output terminal;
the first signal input end is connected to the first enable signal end to receive a first enable signal; the second signal input end is connected to the first enable signal end through a first inverter and used for receiving an inverted signal of the first enable signal; the third signal input terminal is connected to the oscillator sub-circuit, and the first output terminal is connected to the output sub-circuit.
4. The high performance crystal driver circuit of claim 3, wherein the flip-flop sub-circuit is a Schmitt trigger.
5. The high-performance crystal driving circuit as claimed in claim 3, wherein the start-up circuit is connected to the first enable signal terminal, and the start-up circuit receives the first enable signal inputted from the first enable signal terminal to provide a start-up voltage for a subsequent circuit.
6. The high-performance crystal driving circuit according to claim 2, wherein the oscillator sub-circuit comprises a crystal, one end of the crystal is connected with a first capacitor, the other end of the crystal is connected with a second capacitor and a first NMOS transistor, a drain of the first NMOS transistor is connected to the regulator sub-circuit, a source of the first NMOS transistor is connected to the first capacitor and the second capacitor, and a gate of the first NMOS transistor is connected to the regulator sub-circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910658618.XA CN112290909A (en) | 2019-07-22 | 2019-07-22 | High-performance crystal driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910658618.XA CN112290909A (en) | 2019-07-22 | 2019-07-22 | High-performance crystal driving circuit |
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| CN112290909A true CN112290909A (en) | 2021-01-29 |
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| CN201910658618.XA Pending CN112290909A (en) | 2019-07-22 | 2019-07-22 | High-performance crystal driving circuit |
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