CN112289694A - Wafer bonding method - Google Patents
Wafer bonding method Download PDFInfo
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- CN112289694A CN112289694A CN202011193800.1A CN202011193800A CN112289694A CN 112289694 A CN112289694 A CN 112289694A CN 202011193800 A CN202011193800 A CN 202011193800A CN 112289694 A CN112289694 A CN 112289694A
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- wafer
- bonding layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/8388—Hardening the adhesive by cooling, e.g. for thermoplastics or hot-melt adhesives
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83909—Post-treatment of the layer connector or bonding area
- H01L2224/8393—Reshaping
- H01L2224/83947—Reshaping by mechanical means, e.g. "pull-and-cut", pressing, stamping
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A wafer bonding method, comprising: providing a first wafer and a second wafer, wherein the first wafer and the second wafer are respectively provided with a first bonding layer and a second bonding layer which are used for bonding; stacking the second wafer on the first wafer upside down, and bonding the first wafer and the second wafer together through the first bonding layer and the second bonding layer; thinning the thickness of one side of the first wafer, which is far away from the first bonding layer; and performing notch trimming on the first wafer and the second wafer together. By only executing one trimming process, the technical effects of reducing the preparation cost and the trimming distance of the notch are achieved, and the number of effective chips is increased.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer bonding method.
Background
In a semiconductor manufacturing process, as the process technology develops, the requirement for integration degree per unit area is higher, and the wafer bonding method can be used to bond different wafers to improve the integration degree. However, at least two notch trimming processes are usually required in the conventional wafer bonding method, which not only causes the cost burden of wafer fabrication, but also reduces the number of effective chips due to the multiple notch trimming processes. Therefore, it is necessary to provide a wafer bonding method to solve the above technical problems.
Disclosure of Invention
The invention aims to provide a wafer bonding method.
In order to achieve the above object, an aspect of the present invention provides a wafer bonding method, including:
providing a first wafer and a second wafer, wherein the first wafer and the second wafer are respectively provided with a first bonding layer and a second bonding layer which are used for bonding;
stacking the second wafer on the first wafer upside down, and bonding the first wafer and the second wafer together through the first bonding layer and the second bonding layer;
thinning the thickness of one side of the first wafer, which is far away from the first bonding layer; and
and carrying out gap trimming on the first wafer and the second wafer together.
Further, the first bonding layer is butted with the second bonding layer through fusion bonding.
Further, the step of trimming the notch of the first wafer and the second wafer together further includes:
carrying out plane finishing grinding on the thinned surface of the first wafer; and
and carrying out plane finishing grinding on the surface of the second wafer, which is far away from the side of the second bonding layer.
Further, polishing is performed by chemical mechanical polishing.
Further, the first wafer is an array device.
Further, the second wafer is a complementary metal oxide semiconductor device.
Further, the notch trimming is a trimmed wafer edge with a first edge width and a first trimming thickness according to the setting of the edge washing treatment of the photoresist.
Further, the setting of the edge-washing treatment is set according to the covering state of the photoresist in the process of forming the metal interconnection layer.
Further, the setting of the edge washing treatment is set according to a photoresist covering state in the process of forming the first bonding layer and the second bonding layer.
Further, the first edge width is between 1 and 2 millimeters.
Compared with the prior art, the invention only executes one trimming process, achieves the effects of reducing the preparation cost and the trimming distance of the gap, and improves the number of effective chips. It can be seen that the present invention is a significant advance.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
FIGS. 1A-1D are diagrams illustrating steps of a wafer bonding method.
Fig. 2A-2D are process diagrams of a wafer bonding method according to an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the particular embodiments described herein are illustrative only, and that the word "embodiment" as used in the description of the invention is intended to serve as an example, instance, or illustration, and is not intended to limit the invention.
Referring to fig. 1A-1D, steps of a wafer bonding method are shown. The method comprises the following steps: step S11: providing a first wafer 11 and a second wafer 12 after the first notch trimming, where the first wafer 11 and the second wafer 12 each have a first bonding layer 111 and a second bonding layer 121 for bonding (see fig. 1A).
In this step, the first notch trimming includes trimming the first wafer 11 by thickness and edge width, and a first cut surface 13 is provided at an intersection of the first notch trimming and the first notch trimming, where the first cut surface 13 is located at a distance D1 (e.g., 1 mm) from the edge of the first wafer 11.
Step S12: the second wafer 12 is stacked on the first wafer 11 upside down, and the first wafer 11 and the second wafer 12 are bonded together through the first bonding layer 111 and the second bonding layer 121 (see fig. 1B).
Step S13: and thinning the thickness of the side of the first wafer 11 away from the first bonding layer 111 (see fig. 1C). In this step, since the first cross section 13 itself is an unstable structure, when the first wafer 11 is thinned by using a grinder (grind), stress is accumulated at the first cross section 13 to form a weak point. When the first wafer 11 is stressed, peeling or chipping may easily occur at the first fracture surface 13, and a crack with a crack length of a1 is generated at the first fracture surface 13 toward the center of the first wafer 11.
Step S14: the first wafer 11 and the second wafer 12 are subjected to a second notch trimming (see fig. 1D).
In this step, the second notch trimming includes trimming the thickness and the edge width of the first wafer 11 and the second wafer 12, and forming a second cross section 14 at the intersection of the first wafer 11 and the second wafer 12, where the second notch trimming is performed and the second notch trimming is not performed, where the distance between the second cross section 14 and the edge of the second wafer 12 is D2 (the first wafer 11 and the second wafer 12 are aligned with each other). The second gap trimming can be performed to remove the fracture generated in the first fracture surface 13, i.e. D2 is not less than the sum of D1 and the fracture length a 1.
However, as the semiconductor process has higher requirements for integration in a unit area, the stacked layers in the wafer become thicker, and if the stacked layers in the wafer are thicker than those in the first wafer 11, the wafer will form a section deeper than the first section 13, which causes more severe peeling or chipping phenomena when the wafer is thinned, so that a distance greater than D2 is required to trim the second notch trimming to remove the crack, but this sacrifices more effective number of chips and increases the cost of wafer manufacturing. Therefore, in order to solve the above technical problems, the present invention provides a wafer bonding method.
Fig. 2A-2D are schematic diagrams illustrating steps of a wafer bonding method according to an embodiment of the invention. The method comprises the following steps:
step S21: a first wafer 21 and a second wafer 22 are provided, and the first wafer 21 and the second wafer 22 each have a first bonding layer 211 and a second bonding layer 221 for bonding (see fig. 2A).
In the present invention, the first wafer 21 may be an array (array) device, such as an integrated circuit device including a thin-film transistor (TFT); the second wafer 22 may be a complementary metal-oxide-semiconductor (CMOS) device, such as an integrated circuit device including a MOSFET or an image sensor.
Step S22: the second wafer 22 is stacked upside down on the first wafer 21, and the first wafer 21 and the second wafer 22 are bonded together through the first bonding layer 211 and the second bonding layer 221 (see fig. 2B).
In this step, the first bonding layer 211 includes a first film layer 2111 and a first bonding via 2112 disposed therein, and the second bonding layer 221 includes a second film layer 2211 and a second bonding via 2212 disposed therein, and the first bonding via 2112 and the second bonding via 2212 may be butted by, for example, fusion bonding. It is understood that electrostatic bonding, direct bonding, and solder bonding may also be used to bond the first wafer 21 and the second wafer 22, and the bonding method is not limited by the invention.
Step S23: and thinning the thickness of the side of the first wafer 21 away from the first bonding layer 211 (see fig. 2C). In this step, the edge of the thinned first wafer 21 is a continuous smooth curved surface, and is not a cross section having an unstable structure, and when the first wafer 21 is thinned by using a grinder (grind), stress is not easily accumulated on the smooth curved surface, so that the peeling or chipping phenomenon can be effectively suppressed.
Step S24: the first wafer 21 and the second wafer 22 are subjected to notch trimming (see fig. 2D). In this step, since the first wafer 21 and the second wafer 22 are subjected to Edge Bead Removal (EBR) or Wafer Edge Exposure (WEE) edge cleaning during the preparation process, the edge cleaning region is usually removed at the same time when the edge cleaning process is performed, so that the edge cleaning process is set and the crack length caused when the first wafer 21 is thinned is considered at the same time when the distance of the edge cleaning process is set, that is, the edge cleaning process can be used to trim the wafer edge with the first edge width W and the first cleaning thickness T according to the edge cleaning process of the photoresist (as shown in fig. 2D). However, since the peeling or chipping phenomenon is effectively suppressed, the distance of the edge-washing region is set within a proper or minimum range, which can be set according to, for example, the photoresist coverage state in the process of forming a metal interconnection layer (e.g., the copper process stage in the semiconductor process), or the photoresist coverage state in the process of forming the first bonding layer 211 and the second bonding layer 221, thereby reducing the gap trimming distance and the number of invalid chips.
In this embodiment, the first edge width W is between 1 and 2 millimeters.
In this step, the etching gas used for the first bonding via 2112 and the second bonding via 2212 generated in the step S23 is fluorocarbon gas, and if the flow rate of the fluorocarbon gas is not well controlled, carbon-based residual can be easily formed on the wafer surface, especially in the loose structure (such as the first fracture surface 13), if the carbon residual is not removed, when the first wafer 21 and the second wafer 22 are bonded, the surface of the first wafer 21 and the second wafer 22 having the carbon residual may generate defects such as bubble defects (bubbdeffects), thereby reducing the wafer yield. According to the invention, the gap trimming is carried out on the first wafer 21 and the second wafer 22 after bonding, so that the existence of an unstable structure is reduced, the carbon residue is not easy to remain, the defect is reduced, and the wafer yield is improved.
The method further comprises the following steps after the step of S24:
carrying out plane finishing grinding on the thinned surface of the first wafer 21; and
and performing plane finishing grinding on the surface of the second wafer 22 on the side far away from the second bonding layer 221. In this step, the polishing process may be performed by chemical-mechanical polishing (CMP). The purpose of this step is to bond other wafers subsequently on the first wafer or a step performed for subsequent packaging.
Compared with the prior art, the invention only executes one trimming process, achieves the technical effects of reducing the preparation cost and the gap trimming distance, and improves the number of effective chips. Moreover, the trimming is performed after bonding, so that the residue of the carbon residue can be effectively reduced, and the wafer yield is improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (10)
1. A wafer bonding method is characterized by comprising the following steps:
providing a first wafer and a second wafer, wherein the first wafer and the second wafer are respectively provided with a first bonding layer and a second bonding layer which are used for bonding;
stacking the second wafer on the first wafer upside down, and bonding the first wafer and the second wafer together through the first bonding layer and the second bonding layer;
thinning the thickness of one side of the first wafer, which is far away from the first bonding layer; and
and carrying out gap trimming on the first wafer and the second wafer together.
2. The method of claim 1, wherein: and butting the first bonding layer and the second bonding layer by means of fusion bonding.
3. The method of claim 1, wherein the step of trimming the notch of the first wafer together with the second wafer further comprises:
carrying out plane finishing grinding on the thinned surface of the first wafer; and
and carrying out plane finishing grinding on the surface of the second wafer, which is far away from the side of the second bonding layer.
4. The method of claim 3, wherein: the polishing is performed by chemical mechanical polishing.
5. The method of claim 1, wherein: the first wafer is an array device.
6. The method of claim 1, wherein: the second wafer is a complementary metal oxide semiconductor device.
7. The method of claim 1, wherein: the notch trimming is a trimmed wafer edge having a first edge width and a first trimmed thickness according to a setting for edge washing processing of the photoresist.
8. The method of claim 7, wherein: the setting of the edge washing treatment is set according to the covering state of the photoresist in the process of forming the metal interconnection layer.
9. The method of claim 7, wherein: the setting of the edge washing treatment is set according to the covering state of photoresist in the process of forming the first bonding layer and the second bonding layer.
10. The method of claim 7, wherein: the first edge width is between 1 and 2 millimeters.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011193800.1A CN112289694A (en) | 2020-10-30 | 2020-10-30 | Wafer bonding method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011193800.1A CN112289694A (en) | 2020-10-30 | 2020-10-30 | Wafer bonding method |
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| CN112289694A true CN112289694A (en) | 2021-01-29 |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136448A (en) * | 2010-01-25 | 2011-07-27 | S.O.I.Tec绝缘体上硅技术公司 | Process for annealing a structure |
| JP2011523779A (en) * | 2008-09-02 | 2011-08-18 | エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ | Mixed trimming method |
| CN102194667A (en) * | 2010-03-02 | 2011-09-21 | S.O.I.Tec绝缘体上硅技术公司 | Method for manufacturing a multilayer structure with trimming by thermomechanical effects |
| CN103035580A (en) * | 2012-07-24 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding and dissociating process method applied to thin silicon slices |
| US20140113452A1 (en) * | 2012-10-18 | 2014-04-24 | United Microelectronics Corp. | Wafer edge trimming method |
| TW201417163A (en) * | 2012-10-18 | 2014-05-01 | United Microelectronics Corp | Wafer edge trimming method |
| CN108074797A (en) * | 2016-11-14 | 2018-05-25 | 三星电子株式会社 | The method for making substrat structure |
| CN109545672A (en) * | 2018-11-21 | 2019-03-29 | 德淮半导体有限公司 | Wafer bonding method and bonded wafer |
| JP2020096132A (en) * | 2018-12-14 | 2020-06-18 | 株式会社東京精密 | Edge trimming method for bonded wafer |
-
2020
- 2020-10-30 CN CN202011193800.1A patent/CN112289694A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011523779A (en) * | 2008-09-02 | 2011-08-18 | エス． オー． アイ． テック シリコン オン インシュレーター テクノロジーズ | Mixed trimming method |
| CN102136448A (en) * | 2010-01-25 | 2011-07-27 | S.O.I.Tec绝缘体上硅技术公司 | Process for annealing a structure |
| CN102194667A (en) * | 2010-03-02 | 2011-09-21 | S.O.I.Tec绝缘体上硅技术公司 | Method for manufacturing a multilayer structure with trimming by thermomechanical effects |
| CN103035580A (en) * | 2012-07-24 | 2013-04-10 | 上海华虹Nec电子有限公司 | Temporary bonding and dissociating process method applied to thin silicon slices |
| US20140113452A1 (en) * | 2012-10-18 | 2014-04-24 | United Microelectronics Corp. | Wafer edge trimming method |
| TW201417163A (en) * | 2012-10-18 | 2014-05-01 | United Microelectronics Corp | Wafer edge trimming method |
| CN108074797A (en) * | 2016-11-14 | 2018-05-25 | 三星电子株式会社 | The method for making substrat structure |
| CN109545672A (en) * | 2018-11-21 | 2019-03-29 | 德淮半导体有限公司 | Wafer bonding method and bonded wafer |
| JP2020096132A (en) * | 2018-12-14 | 2020-06-18 | 株式会社東京精密 | Edge trimming method for bonded wafer |
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Application publication date: 20210129 |