CN112242467A - Manufacturing method of LED chip - Google Patents
Manufacturing method of LED chip Download PDFInfo
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- CN112242467A CN112242467A CN202011125565.4A CN202011125565A CN112242467A CN 112242467 A CN112242467 A CN 112242467A CN 202011125565 A CN202011125565 A CN 202011125565A CN 112242467 A CN112242467 A CN 112242467A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229910052751 metal Inorganic materials 0.000 claims abstract description 357
- 239000002184 metal Substances 0.000 claims abstract description 357
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 240
- 230000004888 barrier function Effects 0.000 claims abstract description 140
- 238000000034 method Methods 0.000 claims abstract description 61
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 230000008569 process Effects 0.000 claims abstract description 39
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- 239000004065 semiconductor Substances 0.000 claims description 51
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- 238000000576 coating method Methods 0.000 abstract description 9
- 239000011248 coating agent Substances 0.000 abstract description 6
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- 238000005530 etching Methods 0.000 description 7
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- 239000010931 gold Substances 0.000 description 6
- 229910002601 GaN Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000004134 energy conservation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- -1 gold-aluminum Chemical compound 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/405—Reflective materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Led Devices (AREA)
Abstract
The embodiment of the application provides a manufacturing method of an LED chip, which comprises the following steps: forming an epitaxial structure on the surface of the substrate; forming a photoresist mask layer on one side of the epitaxial structure, which is far away from the substrate, wherein the photoresist mask layer is provided with at least one through hole, and the projection area of the through hole on the substrate is gradually reduced along a first direction; forming a metal reflecting layer, a metal barrier layer covering the metal reflecting layer and a metal conducting layer covering the metal barrier layer in the through hole in sequence by taking the photoresist mask layer as a mask so as to form an electrode structure of the LED chip; wherein the first direction is directed from the substrate to the epitaxial structure; the process temperature when the metal barrier layer is formed is higher than that when the metal reflecting layer is formed, so that the coating property of the metal barrier layer on the metal reflecting layer is improved on the basis of improving the luminous efficiency of the LED chip and reducing the resistivity of the electrode structure of the LED chip.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of an LED chip.
Background
A semiconductor Light Emitting Diode (LED) is a solid-state light source, is a light emitting device made of a semiconductor P-N junction, has the obvious advantages of energy conservation, environmental protection, green health and the like, and is widely applied to the fields of indication, display, backlight and the like. Therefore, how to improve the light emitting efficiency and reliability of the semiconductor light emitting diode is a main problem to be solved in the field of light emitting diodes.
Disclosure of Invention
In view of this, the present disclosure provides a method for manufacturing an LED chip to improve the light emitting efficiency and reliability of a light emitting diode.
In order to achieve the above purpose, the embodiments of the present application provide the following technical solutions:
a manufacturing method of an LED chip comprises the following steps:
forming an epitaxial structure on the surface of a substrate, wherein the epitaxial structure comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are stacked;
forming a photoresist mask layer on one side, away from the substrate, of the epitaxial structure, wherein the photoresist mask layer is provided with at least one through hole, and the projection area of the through hole on the substrate is gradually reduced along a first direction;
forming a metal reflecting layer, a metal barrier layer covering the metal reflecting layer and a metal conducting layer covering the metal barrier layer in the through hole in sequence by taking the photoresist mask layer as a mask so as to form an electrode structure of the LED chip;
wherein the first direction is directed from the substrate to the epitaxial structure; the process temperature when the metal barrier layer is formed is higher than the process temperature when the metal reflecting layer is formed.
Optionally, with the photoresist mask layer as a mask, sequentially forming a metal reflection layer in the through hole and a metal barrier layer covering the metal reflection layer includes:
evaporating a metal reflecting layer on the surface of the part of the epitaxial structure, which is positioned in the through hole, by taking the photoresist mask layer as a mask;
preheating the photoresist mask layer at a preset temperature, and forming a metal barrier layer covering the metal reflecting layer in the through hole at the preset temperature.
Optionally, the metal blocking layer includes at least two stacked metal blocking units, and along the first direction, preset process parameters of each metal blocking unit in the at least two stacked metal blocking units are gradually increased;
wherein the preset process parameter includes at least one of a formation rate and a process temperature.
Optionally, the process temperature of each of the at least two stacked metal barrier units is gradually increased.
Optionally, preheating the photoresist mask layer at a preset temperature, and forming a metal barrier layer covering the metal reflective layer in the through hole at the preset temperature includes:
preheating the photoresist mask layer at a first preset temperature, and forming a first metal blocking unit covering the metal reflecting layer in the through hole at the first preset temperature;
preheating the photoresist mask layer at a second preset temperature, and forming a second metal blocking unit covering the first metal blocking unit in the through hole at the second preset temperature;
preheating the photoresist mask layer at a third preset temperature, and forming a third metal blocking unit covering the second metal blocking unit in the through hole at the third preset temperature;
the first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature.
Optionally, along the first direction, a value of a difference between process temperatures of adjacent ones of the at least two stacked metal blocking units ranges from 15 ℃ to 30 ℃, inclusive.
Optionally, with the photoresist mask layer as a mask, forming a metal conductive layer covering the metal blocking layer in the through hole includes:
and maintaining the third preset temperature, and continuously taking the photoresist mask layer as a mask to form a metal conducting layer covering the metal barrier layer in the through hole.
Optionally, a photoresist mask layer is formed on a side of the epitaxial structure away from the substrate, the photoresist mask layer has at least one through hole, and a projection area of the through hole on the substrate gradually decreases along a first direction, including:
forming a first photoresist layer on one side of the epitaxial structure, which is far away from the substrate;
exposing and developing the first photoresist layer by utilizing light with a first wavelength to form a first through hole in the first photoresist layer;
forming a second photoresist layer on one side of the first photoresist layer, which is far away from the epitaxial structure;
exposing and developing the second photoresist layer by using light with a second wavelength to form a second through hole in the second photoresist layer, wherein the second through hole corresponds to the first through hole to form a through hole in the photoresist mask layer;
wherein the second wavelength is greater than the first wavelength; the first photoresist layer and the second photoresist layer are negative photoresist layers.
Optionally, the first photoresist layer is a deep ultraviolet photoresist layer; the second photoresist layer is a heat-sensitive photoresist layer.
Optionally, the method further includes:
and forming an ohmic contact layer in the through hole by taking the photoresist mask layer as a mask, wherein the metal reflection layer is positioned on one side of the ohmic contact layer, which is far away from the epitaxial structure, and covers the ohmic contact layer.
In the method for manufacturing the LED chip provided by the embodiment of the application, the electrode structure of the LED chip comprises a metal reflecting layer, a metal barrier layer and a metal conducting layer, wherein the metal reflecting layer, the metal barrier layer and the metal conducting layer are sequentially formed in the through hole, the metal reflecting layer is used for reflecting light transmitted to the electrode structure of the LED chip to the inside of the LED chip, the light is finally emitted from the light emitting surface of the chip through refraction, the light emitting efficiency and the reliability of the light emitting diode are improved, the resistivity of the electrode structure is reduced by the metal conducting layer, the electrode structure of the LED chip has a good conductive effect, the metal barrier layer is used for blocking diffusion between the metal reflecting layer and the metal conducting layer, the resistivity of the electrode structure caused by mutual solubility between the metal reflecting layer and the metal conducting layer is relieved, and the resistivity of the electrode structure is increased, further reducing the resistivity of the electrode structure.
Furthermore, in the method for manufacturing an LED chip provided in the embodiments of the present application, when the photoresist mask layer is used as a mask, and a metal reflective layer, a metal barrier layer covering the metal reflective layer, and a metal conductive layer covering the metal barrier layer are sequentially formed in the through hole, a process temperature when the metal barrier layer is formed is higher than a process temperature when the metal reflective layer is formed, so that a minimum size of the through hole in the photoresist mask layer when the metal barrier layer is formed is larger than a minimum size of the through hole in the photoresist mask layer when the metal reflective layer is formed, and further, when the photoresist mask layer is used as a mask, the metal reflective layer is sequentially formed in the through hole, and the metal barrier layer covers the metal reflective layer, the metal barrier layer can completely cover the metal reflective layer, and the drapability of the metal barrier layer to the metal reflective layer is improved, and reducing the resistivity of the electrode structure of the LED chip.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing an LED chip according to an embodiment of the present application;
fig. 2 to 19 are schematic structural diagrams after completion of each process step in a method for manufacturing an LED chip according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application, but the present application may be practiced in other ways than those described herein, and it will be apparent to those of ordinary skill in the art that the present application is not limited to the specific embodiments disclosed below.
As mentioned in the background section, how to improve the light emitting efficiency and reliability of semiconductor light emitting diodes is a major problem to be solved in the field of light emitting diodes.
The inventor researches and discovers that if an aluminum-containing reflective electrode structure is adopted as an electrode in an LED, the aluminum layer in the electrode structure can be used as reflective metal to reflect light transmitted to a P electrode and an N electrode of an LED chip back to the inside of the LED chip, so that the reflected light is reflected for multiple times in the LED chip and finally exits from a light-emitting surface of the chip through refraction, and the light-emitting efficiency and the reliability of the light-emitting diode are improved.
In addition, the Au layer is plated in the electrode structure in the LED chip to serve as the conducting layer, so that the resistivity of the electrode structure in the LED chip can be reduced, and a good conducting effect is obtained.
However, since the Au layer and the Al layer are easily diffused to form an Au-Al mutual solubility, the resistivity of the electrode structure of the LED chip increases, and therefore, a titanium layer and a platinum layer are further disposed between the aluminum layer serving as the reflective metal layer and the gold layer serving as the conductive metal layer in the LED chip as metal barrier layers.
The inventor further researches and discovers that in the electrode structure of the LED chip, although a metal barrier layer is added between an Au layer and an Al layer, the coverage of different metal layers is general, so that a gold-aluminum mutual solubility phenomenon is still easily generated between the aluminum layer serving as a reflecting metal layer and the gold layer serving as a conducting metal layer, and the resistivity of the electrode structure of the LED chip is still high.
The undercut angle of the yellow light process is fixed in the manufacturing process of the electrode structure of the LED chip, so that the coating property among different metal layers is general when the electron beam evaporation coating process is adopted to form each metal layer in the electrode structure of the LED chip.
In view of this, embodiments of the present application provide a method for manufacturing an LED chip to improve light emitting efficiency and reliability of a light emitting diode, and the following describes the method for manufacturing an LED chip provided in the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 1, a method for manufacturing an LED chip provided in the embodiment of the present application includes:
s10: as shown in fig. 2, an epitaxial structure 20 is formed on a surface of a substrate 10, and the epitaxial structure 20 includes an N-type semiconductor layer 21, an active layer 22, and a P-type semiconductor layer 23, which are stacked.
On the basis of the above embodiments, in an embodiment of the present application, the substrate is a sapphire substrate, but the present application does not limit this, and in other embodiments of the present application, the substrate may also be a substrate of another material, as the case may be.
On the basis of the foregoing embodiments, in an embodiment of the present application, the N-type semiconductor layer is an N-type gallium nitride layer, and the P-type semiconductor layer is a P-type gallium nitride layer, which is not limited in this application, and is determined as the case may be.
Specifically, in one embodiment of the present application, forming an epitaxial structure on a surface of a substrate includes:
as shown in fig. 3, an N-type semiconductor layer 21 is formed on the surface of the substrate 10, an active layer 22 is formed on the side of the N-type semiconductor layer 21 away from the substrate 10, and a P-type semiconductor layer 23 is formed on the side of the active layer 22 away from the N-type semiconductor layer 21;
with continued reference to fig. 2, a first region of the P-type semiconductor layer 23 and the active layer 22 is etched to expose the N-type semiconductor layer 21, wherein the first region is used for forming an N-type electrode later.
It should be noted that, in the embodiment of the present application, the etching depth of the first region may be a sum of thicknesses of the P-type semiconductor layer and the active layer, or may be greater than the sum of thicknesses of the P-type semiconductor layer and the active layer, and less than the sum of thicknesses of the P-type semiconductor layer, the active layer, and the N-type semiconductor layer.
Specifically, in an embodiment of the present application, etching the P-type semiconductor layer 23 and the first region of the active layer 22 to expose the N-type semiconductor layer 21 includes:
coating a layer of photoresist on the surface of one side, away from the active layer, of the P-type semiconductor layer, and baking, exposing and developing the photoresist to form a first photoresist pattern layer;
etching the first region of the epitaxial structure by using the first photoresist pattern layer as a mask and utilizing a dry etching process to enable the epitaxial structure to expose the N-type semiconductor layer;
and removing the first photoresist pattern layer.
Specifically, in an embodiment of the present application, the etching the P-type semiconductor layer and the first region of the active layer includes: the P-type semiconductor layer and the first region of the active layer are etched by using an Inductively Coupled Plasma (ICP) etching process, and in other embodiments of the present application, other processes may also be used to etch the P-type semiconductor layer and the first region of the active layer, which is not limited in this application and is specifically determined according to the circumstances.
On the basis of any one of the above embodiments, in an embodiment of the present application, the method for manufacturing an LED chip further includes:
as shown in fig. 4, a current blocking layer 30 is formed on a side of the P-type semiconductor layer 23 away from the substrate 10, wherein the current blocking layer 30 is located on a partial surface of the P-type semiconductor layer 23 and exposes at least a surface of a second region of the P-type semiconductor layer, which is used for forming a P-type electrode later.
Specifically, in an embodiment of the present application, the forming of the current blocking layer 30 on the side of the P-type semiconductor layer 23 facing away from the substrate 10 includes:
forming a barrier layer on one side, away from the substrate, of the P-type semiconductor layer, wherein the barrier layer covers the surface of the epitaxial structure;
coating a layer of photoresist on one side of the barrier layer, which is far away from the P-type semiconductor layer, and baking, exposing and developing the photoresist to form a second photoresist pattern layer;
taking the second photoresist pattern layer as a mask, and etching the barrier layer to form a current barrier layer in a partial area of one side of the P-type semiconductor layer, which is far away from the substrate, wherein the current barrier layer at least exposes the surface of a second area of the P-type semiconductor layer;
and removing the second photoresist pattern layer.
Optionally, in an embodiment of the present application, a PECVD deposition process is used to deposit a barrier layer on a side of the P-type semiconductor layer 23 away from the active layer 22, which is not limited in this application, and in other embodiments of the present application, another formation process may also be used to form the barrier layer on the side of the P-type semiconductor layer away from the active layer, as the case may be.
On the basis of any one of the above embodiments, in an embodiment of the present application, the method for manufacturing an LED chip further includes:
as shown in fig. 5, a transparent conductive layer 40 is formed on a side of the current blocking layer 30 away from the P-type semiconductor layer 23, and the transparent conductive layer 40 covers the current blocking layer 30 and a region of the surface of the P-type semiconductor layer 23 excluding the second region surface.
Specifically, in an embodiment of the present application, the forming of the transparent conductive layer 40 on the side of the current blocking layer 30 away from the P-type semiconductor layer 23 includes:
forming a conducting layer on one side, away from the P-type semiconductor layer, of the current blocking layer, wherein the conducting layer covers the surface of the epitaxial structure and the current blocking layer;
coating a layer of photoresist on one side of the conducting layer, which is far away from the P-type semiconductor layer, baking, exposing and developing the photoresist to form a third photoresist pattern layer;
taking the third photoresist pattern layer as a mask, etching the conducting layer to form a transparent conducting layer on one side of the current blocking layer, which is far away from the P-type semiconductor layer, wherein the transparent conducting layer covers the current blocking layer and the area of the surface of the P-type semiconductor layer 23 except the surface of the second area;
and removing the third photoresist pattern layer.
S20: forming a photoresist mask layer 50 on a side of the epitaxial structure 20 away from the substrate 10, where the photoresist mask layer 50 has at least one through hole, and a projection area of the through hole on the substrate 10 gradually decreases along a first direction, where the first direction is directed from the substrate 10 to the epitaxial structure 20.
Optionally, on the basis of the above embodiment, in an embodiment of the present application, the shape of the through hole is an inverted trapezoid, but the present application does not limit this shape, as the case may be.
On the basis of the foregoing embodiment, in an embodiment of the present application, the photoresist mask layer 50 includes a first photoresist mask layer 51 and a second photoresist mask layer 52, specifically, the photoresist mask layer 50 is formed on a side of the epitaxial structure 20 away from the substrate 10, the photoresist mask layer has at least one through hole, and the step of gradually reducing a projection area of the through hole on the substrate along a first direction includes:
forming a first photoresist layer on the side of the epitaxial structure 20 away from the substrate 10;
as shown in fig. 6, exposing and developing the first photoresist layer by using light with a first wavelength, forming a first through hole in the first photoresist layer, and forming a first photoresist mask layer 51;
forming a second photoresist layer on the side of the first photoresist mask layer 51 departing from the epitaxial structure 20;
as shown in fig. 7, exposing and developing the second photoresist layer by using light with a second wavelength, forming a second through hole in the second photoresist layer, and forming a second photoresist mask layer, where the second through hole corresponds to the first through hole, and the second through hole and the first through hole constitute a through hole in the photoresist mask layer;
wherein the second wavelength is greater than the first wavelength; the first photoresist layer and the second photoresist layer are negative photoresist layers.
It should be noted that, in the manufacturing method of the LED chip provided in this embodiment of the present application, an N-type electrode and a P-type electrode are to be formed in the first region and the second region, respectively, and therefore, in an embodiment of the present application, two through holes are provided in the photoresist mask layer, and are located in the first region and the second region, respectively, that is, the first region and the second region each have one through hole, specifically, with reference to fig. 7, in an embodiment of the present application, exposing and developing the first photoresist layer by using light with a first wavelength, and forming the first through hole in the first photoresist layer includes: exposing and developing the first photoresist layer by using light with a first wavelength to form a first through hole in the first photoresist layer at positions corresponding to the first region and the second region respectively; exposing and developing the second photoresist layer by using light with a second wavelength, wherein the step of forming a second through hole in the second photoresist layer comprises the following steps: the second photoresist layer is exposed and developed by using light with a second wavelength, so that a second through hole is formed in the second photoresist layer at a position corresponding to the first region and the second region, respectively.
It should be further noted that, on the basis of the foregoing embodiments, in an embodiment of the present application, because the first photoresist layer and the second photoresist layer are negative photoresist layers, when the first photoresist layer is exposed and developed by using the light with the first wavelength and the second photoresist layer is exposed and developed by using the light with the second wavelength, a projection area of a first through hole formed in the first photoresist layer and a projection area of a second through hole formed in the second photoresist layer on the substrate are gradually reduced along a first direction, so that a projection area of a through hole formed by the first through hole and the second through hole on the substrate is gradually reduced along the first direction.
On the basis of the above embodiments, in one embodiment of the present application, the first wavelength is 248nm, and the second wavelength is 365nm or 405nm, but the present application does not limit this, and in other embodiments of the present application, the first wavelength and the second wavelength may also have other values, as the case may be.
On the basis of the foregoing embodiments, in an embodiment of the present application, the first photoresist layer is a deep ultraviolet photoresist layer, and the second photoresist layer is a thermal sensitive photoresist layer, but the present application is not limited thereto.
It should be noted that the second photoresist layer is a thermal sensitive photoresist layer, and therefore, when a higher temperature is applied to the second photoresist layer, the aperture of the second through hole is larger than that when a lower temperature is applied to the second photoresist layer, so that the process temperature formed during the subsequent process of disposing the metal blocking layer is higher than that formed during disposing the metal reflective layer, and the drapability of the metal blocking layer to the metal reflective layer is improved.
On the basis of any of the above embodiments, in an embodiment of the present application, the photoresist mask layer 50 includes a first photoresist mask layer 51 and a second photoresist mask layer 52, specifically, as shown in fig. 8, in a first through hole formed in the first photoresist layer, an opening width L on a side far from the epitaxial structure is formed4(i.e., the width of the upper bottom of the first via hole) is greater than the width L of the opening in the second via hole formed in the second photoresist layer, on the side close to the epitaxial structure5(namely, the width of the bottom of the second via hole), because the amount of deformation of the first photoresist layer is smaller when a higher temperature is applied, in the embodiment of the present application, when an electrode structure is formed subsequently, if the width of the top bottom of the first via hole is greater than the width of the bottom of the second via hole, when a higher temperature is applied to the photoresist mask layer, even if the amount of deformation of the first photoresist layer is smaller, the size of the first via hole in the first photoresist layer does not limit the formation area of the electrode structure, and the coverage of the metal barrier layer on the metal reflective layer is further improved.
In another embodiment of the present application, the photoresist mask layer 50 only includes a first photoresist mask layer 51, specifically, as shown in fig. 9, a photoresist mask layer is formed on a side of the epitaxial structure away from the substrate, the photoresist mask layer has at least one through hole, and a projection area of the through hole on the substrate gradually decreases along a first direction, including:
forming a first photoresist layer on one side of the epitaxial structure, which is far away from the substrate;
and exposing and developing the first photoresist layer by using light with a first wavelength, and forming a first through hole in the first photoresist layer to form a first photoresist mask layer 51, wherein the first through hole is a through hole in the photoresist mask layer.
It should be noted that, when the photoresist mask layer only includes the first photoresist mask layer, even if the first photoresist layer is a deep ultraviolet photoresist layer rather than a thermal sensitive photoresist layer, the deformation degree of the first photoresist layer at a higher temperature is still greater than the deformation degree of the first photoresist layer at a lower temperature, so that the metal barrier layer and the metal reflective layer are formed by using the photoresist mask layer as a mask, the drapability of the metal barrier layer to the metal reflective layer is improved, and the deformation degree of the non-thermal sensitive photoresist layer is smaller than that of the thermal sensitive photoresist layer.
S30: the photoresist mask layer 50 is used as a mask, a metal reflecting layer 61, a metal barrier layer 62 covering the metal reflecting layer 61 and a metal conducting layer 63 covering the metal barrier layer 62 are sequentially formed in the through hole to form an electrode structure 60 of the LED chip, so that light transmitted to the electrode structure of the LED chip is reflected back to the interior of the LED chip by the metal reflecting layer, and finally the light is emitted from a light emitting surface of the chip through refraction, so that the light emitting efficiency and the reliability of the LED are improved, the resistivity of the electrode structure is reduced by the metal conducting layer, the electrode structure of the LED chip has a good conducting effect, the metal barrier layer is used for blocking diffusion between the metal reflecting layer and the metal conducting layer, and the increase of the resistivity of the electrode structure caused by the mutual solubility between the metal reflecting layer and the metal conducting layer is relieved, further reducing the resistivity of the electrode structure.
Moreover, when the photoresist mask layer is used as a mask, a metal reflecting layer, a metal barrier layer covering the metal reflecting layer and a metal conducting layer covering the metal barrier layer are sequentially formed in the through hole, the process temperature when the metal barrier layer is formed is higher than the process temperature when the metal reflective layer is formed, so that the minimum size of the through hole in the photoresist mask layer when the metal barrier layer is formed is larger than the minimum size of the through hole in the photoresist mask layer when the metal reflective layer is formed, and then when the photoresist mask layer is used as a mask to sequentially form a metal reflecting layer and a metal barrier layer covering the metal reflecting layer in the through hole, the metal barrier layer can completely cover the metal reflecting layer, so that the covering performance of the metal barrier layer on the metal reflecting layer is improved, and the resistivity of the electrode structure of the LED chip is reduced.
Specifically, in one embodiment of the present application, forming the electrode structure includes:
forming a metal reflecting layer 61 in the through hole and on the side of the epitaxial structure 20 departing from the substrate 10 by taking the photoresist mask layer 50 as a mask; forming a metal barrier layer 62 covering the metal reflective layer 61 on the side of the metal reflective layer 61 away from the epitaxial structure 20; a metal conductive layer 63 covering the metal barrier layer 62 is formed on the side of the metal barrier layer 62 facing away from the metal reflective layer 61.
Optionally, on the basis of any of the above embodiments, in an embodiment of the present application, the electrode structure is prepared by using a sectional heating coating method, but the present application does not limit this, and in other embodiments of the present application, the electrode structure may also be prepared by using other methods, as the case may be.
It should be noted that, when the electrode structure is prepared by a sectional heating coating method, the shape of the photoresist mask layer may also change with the sectional heating, that is, when the photoresist mask layer is continuously heated, the photoresist mask layer may shrink, an opening (i.e., the width of the upper bottom of the through hole) on one side of the through hole away from the epitaxial structure may widen, and a portion (i.e., the side surface of the through hole) on one side of the photoresist mask layer close to the through hole may warp, so that the minimum size of the through hole increases.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 10 and 11, fig. 10 and 11 are partially enlarged views of a dashed line frame in fig. 7, and with the photoresist mask layer 50 as a mask, sequentially forming a metal reflective layer 61 in the via hole and a metal barrier layer 62 covering the metal reflective layer 61 includes:
continuing to refer to fig. 10, evaporating a metal reflective layer 61 on the surface of the portion of the epitaxial structure 20 located in the through hole by using the photoresist mask layer as a mask;
with reference to fig. 11, the photoresist mask layer 50 is preheated at a preset temperature, and a metal barrier layer 62 covering the metal reflective layer 61 is formed in the through hole at the preset temperature.
On the basis of the above embodiment, in an embodiment of the present application, the metal reflective layer is an Al layer, so as to reflect light transmitted to the electrode structure of the LED chip back to the inside of the LED chip by using a higher reflectivity of the Al layer, and finally emit light from the light emitting surface of the chip through refraction, thereby improving the light emitting efficiency and reliability of the light emitting diode.
It should be noted that, in the above embodiment, as can be seen from fig. 10 and 11, when a metal barrier layer covering the metal reflective layer is formed in the through hole, the photoresist mask layer is preheated at a preset temperature, so that the photoresist mask layer shrinks, an opening (i.e., a width of an upper bottom of the through hole) on a side of the through hole away from the epitaxial structure widens, that is, the width L of the through hole opening in fig. 11 is increased7Is larger than the width L of the through hole opening in figure 106And the part of the photoresist mask layer close to one side of the through hole (namely, the side surface of the through hole) is warped, namely, the upward warping angle of the part of the photoresist mask layer close to one side of the through hole in fig. 11 is theta, so that the minimum size of the through hole in the photoresist mask layer is increased, a metal reflecting layer is formed by using a smaller through hole, a metal blocking layer is formed by using a larger through hole, and the drapability of the metal blocking layer on the metal reflecting layer is improved.
On the basis of the above embodiments, in an embodiment of the present application, a thickness of the metal reflective layer ranges from 200A to 2000A, inclusive, and this application does not limit this, as the case may be.
On the basis of the above embodiment, in an embodiment of the present application, the evaporation rate of the metal reflective layer ranges from 5A/S to 10A/S, inclusive, so that the metal reflective layer has a larger coverage area and a higher deposition rate.
On the basis of the above embodiments, in one embodiment of the present application, the metal barrier layer includes at least two stacked metal barrier units, and optionally, in an embodiment of the present application, the metal barrier layer includes 2 to 5 stacked metal barrier units, so as to improve the effect of the metal barrier layer for blocking the diffusion between the metal reflecting layer and the metal conducting layer, relieve the resistivity rise of the electrode structure caused by the mutual solubility between the metal reflecting layer and the metal conducting layer, reduce the resistivity of the electrode structure, meanwhile, the phenomenon that the voltage of the electrode structure is too high due to too many metal blocking units is avoided, the blocking capability of the metal blocking layer is influenced due to too few metal blocking units, and the diffusion between the metal reflecting layer and the metal conducting layer cannot be completely blocked is avoided.
On the basis of the foregoing embodiments, in an embodiment of the present application, along the first direction, the preset process parameter of each metal blocking unit in the at least two stacked metal blocking units is gradually increased, so as to improve the drapability of a metal blocking unit formed later to a metal blocking unit formed earlier in two adjacent metal blocking units in the at least two stacked metal blocking units.
Optionally, in an embodiment of the present application, the preset process parameter includes a forming rate, so that a coverage of a later-formed metal blocking unit to a previously-formed metal blocking unit is improved by increasing a forming rate of the later-formed metal blocking unit in two adjacent metal blocking units; in another embodiment of the present application, the predetermined process parameter includes a process temperature, so as to increase a process temperature of a later-formed metal barrier unit in two adjacent metal barrier units, and improve a coverage of the later-formed metal barrier unit on a previously-formed metal barrier unit.
It should be noted that, when the process temperature of each metal blocking unit in the at least two stacked metal blocking units is gradually increased along the first direction, the process temperature also continuously heats the photoresist mask layer, so that the photoresist mask layer gradually shrinks, an opening (i.e., the width of the upper bottom of the through hole) on one side, away from the epitaxial structure, in the through hole in the photoresist mask layer is gradually increased, and a portion (i.e., the side surface of the through hole) on one side, close to the through hole, in the photoresist mask layer is gradually warped, so that the minimum size of the through hole in the photoresist mask layer is gradually increased, and the metal blocking layer can completely cover the metal reflective layer when the photoresist mask layer is used as a mask to form the metal blocking layer covering the metal reflective layer in the through hole, the coating property of the metal barrier layer on the metal reflecting layer is improved, and the resistivity of the electrode structure of the LED chip is reduced.
On the basis of the foregoing embodiment, in an embodiment of the present application, when the metal barrier layer includes 3 stacked metal barrier units, preheating the photoresist mask layer 50 at a preset temperature, and forming the metal barrier layer 62 covering the metal reflective layer 61 in the via hole at the preset temperature includes:
as shown in fig. 12, preheating the photoresist mask layer 50 at a first preset temperature, and forming a first metal blocking unit 6201 covering the metal reflective layer 61 in the through hole at the first preset temperature;
as shown in fig. 13, preheating the photoresist mask layer 50 at a second preset temperature, and forming a second metal blocking unit 6202 in the via hole to cover the first metal blocking unit 6201 at the second preset temperature;
as shown in fig. 14, the photoresist mask layer 50 is preheated at a third preset temperature, and a third metal barrier unit 6203 covering the second metal barrier unit 6202 is formed in the through hole at the third preset temperature;
the first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature, so that the drapability of the second metal blocking unit to the first metal blocking unit and the drapability of the third metal blocking unit to the second metal blocking unit are improved.
On the basis of the foregoing embodiment, in an embodiment of the present application, along the first direction, a value of a difference between process temperatures of adjacent metal barrier units in the at least two stacked metal barrier units ranges from 15 ℃ to 30 ℃, inclusive, and optionally, in an embodiment of the present application, the first preset temperature is 50 ℃, the second preset temperature is 70 ℃, and the third preset temperature is 100 ℃, but the present application does not limit this, depending on circumstances.
As can be seen from fig. 12 and 13, a width L1 of an opening of the via hole on a side away from the epitaxial structure (i.e., a width of the upper bottom of the via hole) when the first metal barrier unit is formed is smaller than a width L2 of an opening of the via hole on a side away from the epitaxial structure (i.e., a width of the upper bottom of the via hole) when the second metal barrier unit is formed, and an angle θ at which a portion of the photoresist mask layer on a side close to the via hole (i.e., a side surface of the via hole) warps upward when the first metal barrier unit is formed1Is smaller than the upward warping angle theta of the part (namely the side surface of the through hole) close to one side of the through hole in the photoresist mask layer when the second metal blocking unit is formed2Therefore, the minimum size of the through hole is smaller than that of the through hole when the first metal blocking unit is formed, the coverage of the first metal blocking unit by the second metal blocking unit is improved when the metal blocking layer is formed in the through hole by taking the photoresist mask layer as a mask.
As can be seen from fig. 13 and 14, the width L2 of the opening of the via hole on the side far from the epitaxial structure (i.e., the width of the upper bottom of the via hole) when the second metal barrier unit is formed is smaller than the width L3 of the opening of the via hole on the side far from the epitaxial structure (i.e., the width of the upper bottom of the via hole) when the third metal barrier unit is formed, and the angle θ at which the portion of the photoresist mask layer on the side near the via hole (i.e., the side of the via hole) warps upward when the second metal barrier unit is formed2Is smaller than the third metal barrier unitWhen the photoresist mask layer is formed, the part of the photoresist mask layer close to one side of the through hole (namely the side surface of the through hole) is warped upwards by an angle theta3Therefore, the minimum size of the through hole is smaller than that of the through hole when the second metal blocking unit is formed, the photoresist mask layer is used as a mask, and the drapability of the third metal blocking unit on the second metal blocking unit is improved when the metal blocking layer is formed in the through hole.
On the basis of the foregoing embodiment, in an embodiment of the present application, as shown in fig. 15, the metal blocking layer includes 3 stacked metal blocking units, each metal blocking unit includes a first metal blocking layer and a second metal blocking layer, specifically, preheating the photoresist mask layer at a preset temperature, and forming the metal blocking layer covering the metal reflective layer in the via hole at the preset temperature includes:
preheating the photoresist mask layer at a first preset temperature, and forming a first metal barrier layer 621 covering a first metal barrier unit of the metal reflection layer 61 and a second metal barrier layer 622 in the first metal barrier unit in the through hole at the first preset temperature, wherein the first metal barrier layer 621 of the first metal barrier unit covers the metal reflection layer 61, and the second metal barrier layer 622 of the first metal barrier unit covers the first metal barrier layer 621 of the first metal barrier unit;
preheating the photoresist mask layer at a second preset temperature, and forming a first metal blocking layer 623 covering a second metal blocking unit of the first metal blocking unit and a second metal blocking layer 624 covering the second metal blocking unit in the through hole at the second preset temperature, wherein the first metal blocking layer 623 covering the second metal blocking layer 622 in the first metal blocking unit and the second metal blocking layer 624 covering the first metal blocking unit in the second metal blocking unit;
preheating the photoresist mask layer at a third preset temperature, and forming a first metal barrier layer 625 in the third metal barrier unit and a second metal barrier layer 626 in the third metal barrier unit in the through hole at the third preset temperature, wherein the first metal barrier layer 625 in the third metal barrier unit covers the second metal barrier layer 624 in the second metal barrier unit, and the second metal barrier layer 626 in the third metal barrier unit covers the first metal barrier layer 625 in the third metal barrier unit.
On the basis of the foregoing embodiment, in an embodiment of the present application, the first metal barrier layer is a Ti layer, and the second metal barrier layer is a Pt layer, which is not limited in this application, in other embodiments of the present application, the first metal barrier layer and the second metal barrier layer may also be other metal layers, and it is only necessary to ensure that the first metal barrier layer and the second metal barrier layer play a role in blocking diffusion between the metal reflective layer and the metal conductive layer, as the case may be.
On the basis of the above embodiment, in an embodiment of the present application, the evaporation rate of the first metal barrier layer is 1A/S-2A/S, inclusive, and the evaporation rate of the second metal barrier layer is 0.5A/S-2A/S, inclusive, which is not limited herein, and it is only necessary to ensure that the first metal barrier layer and the second metal barrier layer have lower evaporation rates, so that the first metal barrier layer and the second metal barrier layer have higher compactness, and the blocking effect of the metal barrier layer is improved.
On the basis of the foregoing embodiment, in an embodiment of the present application, a thickness of the first metal barrier layer ranges from 200A to 1000A inclusive, and a thickness of the second metal barrier layer ranges from 500A to 2000A inclusive, which is not limited in this application, as the case may be.
On the basis of the foregoing embodiments, in an embodiment of the present application, as shown in fig. 16, forming a metal conductive layer 63 covering the metal barrier layer 62 in the through hole by using the photoresist mask layer 50 as a mask includes:
and maintaining the third preset temperature, continuously taking the photoresist mask layer as a mask, and forming a metal conducting layer 63 covering the metal barrier layer 62 in the through hole, so that the resistivity of the electrode structure is reduced by using the metal conducting layer, and the electrode structure of the LED chip has a good conducting effect.
On the basis of the foregoing embodiment, in an embodiment of the present application, the metal conductive layer is an Au layer, which is not limited in this application, and in other embodiments of the present application, the metal conductive layer may also be another metal layer, and it is only necessary to ensure that the metal conductive layer can reduce the resistivity of the electrode structure, so that the electrode structure of the LED chip has a good conductive effect, which is specifically determined according to the situation.
On the basis of the above embodiment, in an embodiment of the present application, a thickness of the metal conductive layer ranges from 0.5um to 2um, inclusive, and the present application does not limit this, as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, the evaporation rate of the metal conductive layer is 10A/S to 15A/S, inclusive, which is not limited in the present application, as the case may be.
It should be noted that, since it is difficult to form a good ohmic contact and the adhesion is poor when the Al layer is in direct contact with the GaN layer, in an embodiment of the present application, as shown in fig. 17, the forming of the electrode structure further includes:
and forming an ohmic contact layer 64 in the through hole by taking the photoresist mask layer 50 as a mask, wherein the metal reflecting layer 61 is positioned on one side of the ohmic contact layer 64, which is far away from the epitaxial structure 20, and covers the ohmic contact layer 64, so that the ohmic contact layer is utilized to form good ohmic contact between the epitaxial structure and the metal reflecting layer and has better adhesion.
Optionally, the ohmic contact layer is a Cr layer or a Ni layer, that is, a Cr layer or a Ni layer is disposed between the GaN layer and the Al layer in the LED chip, so that the Al layer forms good ohmic contact and has strong adhesion with the GaN layer through the Cr layer or the Ni layer.
On the basis of the above embodiments, in an embodiment of the present application, the thickness of the ohmic contact layer ranges from 10A to 50A, inclusive, and this is not limited in this application, as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, the evaporation rate of the ohmic contact layer is 0.5A/S, inclusive, which is not limited in the present application, as the case may be.
On the basis of any of the above embodiments, in an embodiment of the present application, after forming an ohmic contact layer, a metal reflective layer, a metal barrier layer covering the metal reflective layer, and a metal conductive layer covering the metal barrier layer in the through hole in sequence by using the photoresist mask layer as a mask, the method further includes: removing the photoresist mask layer, optionally, in an embodiment of the present application, removing the photoresist mask layer includes: and removing the photoresist mask layer by adopting a stripping process, but the photoresist mask layer is not limited in the application and is determined according to the situation.
On the basis of any of the above embodiments, in an embodiment of the present application, as shown in fig. 18, the electrode structure 60 includes an N-type electrode 70 and a P-type electrode 80, which is not limited in this application, as the case may be.
On the basis of the above embodiments, in an embodiment of the present application, as shown in fig. 19, the method for manufacturing an LED further includes:
an insulating layer 90 is formed on one side of the transparent conducting layer 40, which deviates from the epitaxial wafer 20, the insulating layer 90 completely covers the epitaxial structure 20 and the transparent conducting layer 40, the insulating layer 90 is provided with a third through hole and a fourth through hole, the third through hole exposes a part of the surface of the N-type electrode 70, and the fourth through hole exposes a part of the surface of the P-type electrode 80.
The following describes a manufacturing process of the method for manufacturing an LED chip provided in the embodiments of the present application with reference to specific embodiments.
Specifically, in an embodiment of the present application, a process method for manufacturing an LED chip includes:
forming an epitaxial structure on the surface of a substrate, wherein the epitaxial structure comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are stacked;
forming a current blocking layer on one side of the P-type semiconductor layer, which is far away from the substrate, by adopting a PECVD (plasma enhanced chemical vapor deposition) deposition process;
forming a transparent conducting layer on one side, away from the P-type semiconductor layer, of the current blocking layer;
forming a photoresist mask layer on one side of the transparent conducting layer, which is far away from the substrate, wherein the photoresist mask layer is provided with at least one through hole;
sequentially forming an ohmic contact layer and a metal reflecting layer on the surface of the part of the epitaxial structure, which is positioned in the through hole, at normal temperature by taking the photoresist mask layer as a mask;
preheating the photoresist mask layer at the temperature of 50 ℃ and keeping the temperature for 15-30 mins, so that the shrinkage range of the photoresist mask layer is 0-0.5 um and comprises a right endpoint value, wherein the value range of the width of an opening (namely the upper bottom of the through hole) on one side, far away from the epitaxial structure, of the through hole in the photoresist mask layer is 0-1 um and comprises the right endpoint value, the value range of an upward warping angle of a part (namely the side surface of the through hole) on one side, close to the through hole, of the photoresist mask layer is 0-3 DEG and comprises the right endpoint value, and a first metal blocking unit covering the metal reflecting layer is formed in the through hole by taking the current photoresist mask layer as a mask;
preheating the photoresist mask layer at the temperature of 70 ℃, and keeping the temperature for 15-30 mins, so that the shrinkage range of the photoresist mask layer is 0.5-1 um and comprises end point values, wherein the value range of the width of an opening (namely the upper bottom of the through hole) on one side, far away from the epitaxial structure, of the through hole in the photoresist mask layer is 1-2 um and comprises the end point values, the value range of the upward warping angle of a part (namely the side surface of the through hole) on one side, close to the through hole, of the photoresist mask layer is 3-10 degrees and comprises the end point values, and a second metal blocking unit covering the first metal blocking unit is formed in the through hole by taking the current photoresist mask layer as a mask;
preheating the photoresist mask layer at the temperature of 100 ℃, and keeping the temperature for 15-30 mins, so that the shrinkage range of the photoresist mask layer is 1-3 um and comprises end point values, wherein the value range of the width of an opening (namely the upper bottom of the through hole) on one side, far away from the epitaxial structure, of the through hole in the photoresist mask layer is 2-6 um and comprises the end point values, the value range of the upward warping angle of a part (namely the side surface of the through hole) on one side, close to the through hole, of the photoresist mask layer is 10-60 degrees and comprises the end point values, and a third metal blocking unit covering the second metal blocking unit is formed in the through hole by taking the current photoresist mask layer as a mask;
continuously preheating the photoresist mask layer at the temperature of 100 ℃, keeping the shape of a through hole in the current photoresist mask layer unchanged, and forming a metal conducting layer covering the third metal blocking unit in the through hole;
removing the photoresist mask layer by adopting a stripping process;
and forming an insulating layer on one side of the transparent conducting layer, which is far away from the epitaxial wafer.
It should be noted that, in the above embodiment, the shrinkage range of the photoresist mask layer refers to the entire shrinkage value range of the photoresist mask layer, and for example, when the photoresist mask layer is preheated at a temperature of 70 ℃, the shrinkage range of the photoresist mask layer is 0.5um to 1um, which includes: when the photoresist mask layer is preheated at the temperature of 50 ℃, the shrinkage range of the photoresist mask layer is within the total shrinkage range after the photoresist mask layer is further shrunk on the basis that the photoresist mask layer is shrunk when the photoresist mask layer is preheated at the temperature of 50 ℃ and the photoresist mask layer is preheated at the temperature of 70 ℃. Similarly, when the photoresist mask layer is preheated at the temperature of 100 ℃, the shrinkage range of the photoresist mask layer is 1 um-3 um, and the total shrinkage range of the photoresist mask layer is obtained after the photoresist mask layer is preheated at the temperatures of 50 ℃, 70 ℃ and 100 ℃.
To sum up, in the LED chip's that this application embodiment provided manufacturing method, the electrode structure of LED chip is including forming in proper order metal reflecting layer in the through-hole, cover the metal barrier layer of metal reflecting layer and cover the metal conducting layer of metal barrier layer, thereby can utilize the metal reflecting layer will transmit the light reflection of the electrode structure of LED chip and get back to inside the LED chip, finally through refraction from the chip play plain noodles light-emitting, improve emitting diode's luminous efficacy and reliability, and utilize the metal conducting layer reduces the resistivity of electrode structure, make the electrode structure of LED chip has good electrically conductive effect, utilize simultaneously the metal barrier layer blocks the metal reflecting layer with diffusion between the metal conducting layer alleviates the metal reflecting layer with the electrode structure resistivity that mutual solution phenomenon between the metal conducting layer leads to rises, further reducing the resistivity of the electrode structure.
Furthermore, in the method for manufacturing an LED chip provided in the embodiments of the present application, when the photoresist mask layer is used as a mask, and a metal reflective layer, a metal barrier layer covering the metal reflective layer, and a metal conductive layer covering the metal barrier layer are sequentially formed in the through hole, a process temperature when the metal barrier layer is formed is higher than a process temperature when the metal reflective layer is formed, so that a minimum size of the through hole in the photoresist mask layer when the metal barrier layer is formed is larger than a minimum size of the through hole in the photoresist mask layer when the metal reflective layer is formed, and further, when the photoresist mask layer is used as a mask, the metal reflective layer is sequentially formed in the through hole, and the metal barrier layer covers the metal reflective layer, the metal barrier layer can completely cover the metal reflective layer, and the drapability of the metal barrier layer to the metal reflective layer is improved, and reducing the resistivity of the electrode structure of the LED chip.
All parts in the specification are described in a mode of combining parallel and progressive, each part is mainly described to be different from other parts, and the same and similar parts among all parts can be referred to each other.
In the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other to enable those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A manufacturing method of an LED chip is characterized by comprising the following steps:
forming an epitaxial structure on the surface of a substrate, wherein the epitaxial structure comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are stacked;
forming a photoresist mask layer on one side, away from the substrate, of the epitaxial structure, wherein the photoresist mask layer is provided with at least one through hole, and the projection area of the through hole on the substrate is gradually reduced along a first direction;
forming a metal reflecting layer, a metal barrier layer covering the metal reflecting layer and a metal conducting layer covering the metal barrier layer in the through hole in sequence by taking the photoresist mask layer as a mask so as to form an electrode structure of the LED chip;
wherein the first direction is directed from the substrate to the epitaxial structure; the process temperature when the metal barrier layer is formed is higher than the process temperature when the metal reflecting layer is formed.
2. The manufacturing method of claim 1, wherein the forming of the metal reflective layer and the metal barrier layer covering the metal reflective layer in the through hole in sequence by using the photoresist mask layer as a mask comprises:
evaporating a metal reflecting layer on the surface of the part of the epitaxial structure, which is positioned in the through hole, by taking the photoresist mask layer as a mask;
preheating the photoresist mask layer at a preset temperature, and forming a metal barrier layer covering the metal reflecting layer in the through hole at the preset temperature.
3. The manufacturing method according to claim 2, wherein the metal barrier layer comprises at least two stacked metal barrier units, and the preset process parameters of each metal barrier unit in the at least two stacked metal barrier units are gradually increased along the first direction;
wherein the preset process parameter includes at least one of a formation rate and a process temperature.
4. The method of manufacturing according to claim 3, wherein the process temperature of each of the at least two stacked metal barrier units is gradually increased.
5. The method of claim 4, wherein preheating the photoresist mask layer at a predetermined temperature and forming a metal barrier layer covering the metal reflective layer in the via hole at the predetermined temperature comprises:
preheating the photoresist mask layer at a first preset temperature, and forming a first metal blocking unit covering the metal reflecting layer in the through hole at the first preset temperature;
preheating the photoresist mask layer at a second preset temperature, and forming a second metal blocking unit covering the first metal blocking unit in the through hole at the second preset temperature;
preheating the photoresist mask layer at a third preset temperature, and forming a third metal blocking unit covering the second metal blocking unit in the through hole at the third preset temperature;
the first preset temperature is lower than the second preset temperature, and the second preset temperature is lower than the third preset temperature.
6. The method of manufacturing according to claim 4, wherein, in the first direction, a difference between process temperatures of adjacent ones of the at least two stacked metal barrier units ranges from 15 ℃ to 30 ℃, inclusive.
7. The method of claim 5, wherein forming a metal conductive layer covering the metal barrier layer in the via hole with the photoresist mask layer as a mask comprises:
and maintaining the third preset temperature, and continuously taking the photoresist mask layer as a mask to form a metal conducting layer covering the metal barrier layer in the through hole.
8. The manufacturing method of any one of claims 1 to 7, wherein a photoresist mask layer is formed on a side of the epitaxial structure facing away from the substrate, the photoresist mask layer having at least one through hole, and a projection area of the through hole on the substrate gradually decreases along a first direction, and the method comprises:
forming a first photoresist layer on one side of the epitaxial structure, which is far away from the substrate;
exposing and developing the first photoresist layer by utilizing light with a first wavelength to form a first through hole in the first photoresist layer;
forming a second photoresist layer on one side of the first photoresist layer, which is far away from the epitaxial structure;
exposing and developing the second photoresist layer by using light with a second wavelength to form a second through hole in the second photoresist layer, wherein the second through hole corresponds to the first through hole to form a through hole in the photoresist mask layer;
wherein the second wavelength is greater than the first wavelength; the first photoresist layer and the second photoresist layer are negative photoresist layers.
9. The method of claim 8, wherein the first photoresist layer is a deep ultraviolet photoresist layer; the second photoresist layer is a heat-sensitive photoresist layer.
10. The method of manufacturing according to claim 1, further comprising:
and forming an ohmic contact layer in the through hole by taking the photoresist mask layer as a mask, wherein the metal reflection layer is positioned on one side of the ohmic contact layer, which is far away from the epitaxial structure, and covers the ohmic contact layer.
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| CN114388667A (en) * | 2021-12-23 | 2022-04-22 | 江西兆驰半导体有限公司 | Flip light-emitting diode chip electrode and preparation method thereof |
| CN114551340A (en) * | 2022-01-14 | 2022-05-27 | 深圳镓芯半导体科技有限公司 | Third generation semiconductor contact window structure and manufacturing method thereof |
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Application publication date: 20210119 |