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CN112233981A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN112233981A
CN112233981A CN202011089159.7A CN202011089159A CN112233981A CN 112233981 A CN112233981 A CN 112233981A CN 202011089159 A CN202011089159 A CN 202011089159A CN 112233981 A CN112233981 A CN 112233981A
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region
regions
doped
barrier
type transistor
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田武
孙超
王欣
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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    • H10B—ELECTRONIC MEMORY DEVICES
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    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The invention provides a semiconductor device and a preparation method thereof, comprising the following steps: providing a substrate layer, wherein a grid electrode is arranged on the substrate layer, a source electrode region, a drain electrode region and a channel region are arranged in the substrate layer, the grid electrode corresponds to the channel region, and the source electrode region and the drain electrode region are arranged on two sides of the grid electrode; forming a graphical barrier layer on a region to be doped between a source electrode region and a grid electrode and a region to be doped between a drain electrode region and the grid electrode on the substrate layer, wherein the barrier layer shields part of the region to be doped at intervals; and doping the region to be doped to form a lightly doped region. The invention forms the barrier layer in the area (wide tube area) which needs to reduce the doping amount of the light doping area, and reduces the doping amount of the area through the shielding effect of the barrier layer, thereby avoiding the area (narrow tube sub-area) which does not need to reduce the doping amount of the light doping area from reducing the doping amount, not only avoiding the generation of the leakage current of the wide tube, but also avoiding the breakdown voltage of the narrow tube from being influenced, and the method is simple and feasible.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a preparation method thereof.
Background
In current 3D-NAND circuit designs, a large number of ultra high voltage N-type metal oxide semiconductor (UHV NMOS) devices are used to generate and pass voltages to the core array, and to program and erase them. In order to obtain large current driving capability, a number of wide ultra-high voltage nmos devices are often used. However, since the substrate bias characteristics need to be balanced, the threshold Voltage (VT) and the ion Implantation (IMP) of the well of these ultra-high voltage nmos devices are generally relatively small. Therefore, a large leakage current is likely to occur due to penetration in the high-voltage off state.
How to avoid the generation of leakage current of semiconductor devices is a technical problem which needs to be solved urgently at present.
Disclosure of Invention
The invention aims to solve the technical problem of how to avoid the generation of leakage current of a semiconductor device.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of: providing a substrate layer, wherein a grid electrode is arranged on the substrate layer, a source electrode region, a drain electrode region and a channel region are arranged in the substrate layer, the grid electrode corresponds to the channel region, and the source electrode region and the drain electrode region are arranged on two sides of the grid electrode; forming a graphical blocking layer on the substrate layer, the region to be doped between the source region and the grid electrode and the region to be doped between the drain region and the grid electrode, wherein the blocking layer shields part of the region to be doped at intervals; and doping the region to be doped to form a lightly doped region.
Optionally, the blocking layer includes blocking areas and hollow-out areas, the blocking areas and the hollow-out areas are alternately arranged, and the hollow-out areas expose the substrate layer.
Optionally, the blocking layer includes a plurality of blocking bars arranged at intervals, the blocking bars serve as the blocking areas, and gaps between adjacent blocking bars serve as the hollowed-out areas.
Optionally, the blocking layer includes a plurality of concentric blocking rings arranged at intervals, the blocking rings serve as the blocking areas, and gaps between adjacent blocking rings serve as the hollowed-out areas.
Optionally, the blocking layer includes a plurality of blocking blocks arranged in a matrix, the blocking blocks serve as the blocking regions, and gaps between adjacent blocking blocks serve as the hollow regions.
Optionally, the width of the barrier rib or the barrier ring or the barrier rib is 60nm to 0.5 μm.
Optionally, doping is performed on the source region and the drain region before forming the barrier layer, so as to form a source region and a drain region.
Optionally, doping the source region and the drain region after or before forming the lightly doped region to form a source region and a drain region.
Optionally, the semiconductor device includes a first type transistor and a second type transistor, a width of a channel region of the first type transistor is greater than a width of a channel region of the second type transistor, and the blocking layer is formed only on a region to be doped of the first type transistor.
The invention also provides a semiconductor device prepared by the preparation method, which comprises the following steps: a base layer; a gate disposed on the base layer; the source electrode and the drain electrode are arranged in the substrate layer and are positioned at two sides of the grid electrode, and the channel region is arranged in the substrate layer and corresponds to the grid electrode; the lightly doped region is arranged in the substrate layer and is positioned between the source electrode and the grid electrode and between the drain electrode and the grid electrode; and the patterned barrier layer is arranged on the substrate layer and shields part of the lightly doped region at intervals.
Optionally, the semiconductor device includes a first type transistor and a second type transistor, a width of a channel region of the first type transistor is greater than a width of a channel region of the second type transistor, the blocking layer is formed only on a region to be doped of the first type transistor, and a doping concentration of a lightly doped region of the first type transistor is less than a doping concentration of a lightly doped region of the second type transistor.
The invention has the advantages that the barrier layer is formed in the region (wide tube region) needing to reduce the doping dose of the light doping region, the doping dose of the region is reduced through the shielding effect of the barrier layer, and the doping dose of the region is not reduced by adjusting the ion implantation dose of the ion implantation equipment, so that the doping dose of the region (narrow tube region) not needing to reduce the doping dose of the light doping region is also prevented from being reduced.
Drawings
Fig. 1 is a schematic step view of a manufacturing method of a semiconductor device according to a first embodiment of the present invention;
fig. 2A to 2D are schematic cross-sectional views of a semiconductor structure in respective steps of a manufacturing method of a semiconductor device according to a first embodiment of the present invention;
FIG. 3 is a schematic top view of the structure shown in FIG. 2C;
FIG. 4 is a schematic top view of a semiconductor structure according to a second embodiment of the method of manufacturing the present invention;
FIG. 5 is a schematic top view of a semiconductor structure according to a third embodiment of the method of manufacturing the present invention;
FIG. 6 is a schematic top view of a semiconductor structure according to a fourth embodiment of the method of manufacturing the present invention;
FIG. 7 is a schematic top view of a semiconductor structure according to a fifth embodiment of the method of manufacturing the present invention;
FIG. 8 is a schematic top view of a semiconductor structure according to a sixth embodiment of the method of manufacturing the present invention;
fig. 9 is a schematic top view of a semiconductor structure according to a seventh embodiment of the method of manufacturing the present invention.
Detailed Description
Embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail below with reference to the accompanying drawings.
As described in the background, in order to obtain large current driving capability, a number of wide ultra-high voltage nmos devices are often used to generate and deliver voltages to the core array, and program and erase them. However, since good substrate bias characteristics are required, the threshold Voltage (VT) and the ion Implantation (IMP) of the well of these ultra-high voltage nmos devices are generally small, and thus a large leakage current is likely to occur due to penetration in the high-voltage off state.
In the prior art, methods for improving leakage current include: firstly, the length (channel length) of a channel region is increased, but the chip size is increased, and the unit cost is increased; secondly, the ion implantation concentration of the trap is increased, but the bulk effect is changed, so that the voltage transmission efficiency is reduced; 3) the lightly doped region (LDD) is reduced in dopant amount or ion implantation depth, but results in the Breakdown Voltage (BVDS) of the otherwise narrow transistor being affected. Therefore, the methods for improving the leakage current in the prior art have defects.
Accordingly, the present invention provides a semiconductor device and a method for manufacturing the same, which can improve leakage current and avoid the above-mentioned drawbacks.
Fig. 1 is a schematic view of steps of a manufacturing method of a semiconductor device according to a first embodiment of the present invention, and fig. 2A to 2D are schematic cross-sectional views of a semiconductor structure in respective steps of the manufacturing method of the semiconductor device according to the first embodiment of the present invention.
Referring to step S10 and fig. 2A, a substrate layer 100 is provided, a gate 110 is disposed on the substrate layer 100, a source region 101, a drain region 102 and a channel region 120 are disposed in the substrate layer 100, the gate 110 corresponds to the channel region 120, and the source region 101 and the drain region 102 are disposed on two sides of the gate 110.
The constituent material of the substrate layer 100 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and also includes multilayer structures of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and germanium-on-insulator (GeOI). As an example, in the present embodiment, the base layer 100 is made of monocrystalline silicon.
In the base layer 100, the region below the gate 110 is the channel region 120, that is, the region of the base layer 100 shielded by the gate 110 is the channel region 120. Although the source region 101 and the drain region 102 are disposed on both sides of the gate electrode 110, the source region 101 and the drain region 102 are not disposed in contact with the gate electrode 100, but have a certain distance therebetween. A region to be doped 103 is between the source region 101 and the gate 110, and a region to be doped 104 is between the drain region 102 and the gate 110. The regions to be doped 103 and 104 are doped in the subsequent step to form lightly doped regions.
The source region 101 and the drain region 102 may be doped to form a source and a drain. In the present embodiment, after this step, the source region 101 and the drain region 102 are doped before the step of forming the barrier layer 150 (see fig. 2C).
Specifically, in step S11 and fig. 2B, the source region 101 and the drain region 102 are doped to form the source 130 and the drain 140. The doping method may be ion Implantation (IMP), and the implanted ions may be selected according to the type of the subsequently formed transistor. For example, if NMOS is to be formed subsequently, in this step, As, P or Sb ion implantation may be performed on the source region 101 and the drain region 102 to form a source 130 and a drain 140; if a PMOS is to be formed subsequently, B ion implantation may be performed on the source region 101 and the drain region 102 to form the source 130 and the drain 140.
In other embodiments of the present invention, the source region 101 and the drain region 102 may be doped to form a source and a drain after forming the blocking layer, before forming the lightly doped layer, or after forming the lightly doped layer.
Referring to step S12 and fig. 2C, a patterned blocking layer 150 is formed on the substrate layer 100, on the region to be doped 103 between the source region 101 and the gate 110 and on the region to be doped 104 between the drain region 102 and the gate 110, wherein the blocking layer 150 blocks portions of the regions to be doped 103 and 104 at intervals.
The blocking layer 150 is formed to block a portion of the regions to be doped 103 and 104 at intervals, which means that the blocking layer 150 has a pattern that can block a portion of the regions to be doped 103 and 104 and expose a portion of the regions to be doped 103 and 104. Specifically, referring to fig. 3, which is a schematic top view of the structure shown in fig. 2C, the blocking layer 150 includes blocking regions 151 and hollow-out regions 152, the blocking regions 151 and the hollow-out regions 152 are alternately arranged, the blocking regions 151 block the regions 103 and 104 to be doped of the substrate layer 100, and the hollow-out regions 152 expose the regions 103 and 104 to be doped of the substrate layer 100, so that a part of the regions 103 and 104 to be doped are blocked and a part of the regions are not blocked.
Further, in this step, a barrier material layer may be formed on the substrate layer 100, and then the barrier material layer may be patterned by using photolithography and etching processes to form the patterned barrier layer 150. In this embodiment, the material of the blocking layer 150 is polysilicon, and in other embodiments of the present invention, the blocking layer 150 may also be other materials as long as the blocking effect can be achieved for the subsequent ion implantation.
Referring to step S13 and fig. 2D, the regions to be doped 103 and 104 are doped to form lightly doped regions 160 and 170. The regions to be doped 103 and 104 may be doped by an ion implantation process, the type of the implanted ions is the same as the type of the ions forming the source and the drain, but the concentrations of the implanted ions and the ions are different, and the doping concentrations of the lightly doped regions 160 and 170 are less than the doping concentrations of the source and the drain.
In this step, in the region not shielded by the blocking layer 150 (i.e., the hollow-out region 152), ions can be implanted into the regions to be doped 103 and 104 and diffused in the regions to be doped 103 and 104 to form lightly doped regions 163 and 170, while in the region shielded by the blocking layer 150 (i.e., the blocking region 151), the ion implantation is blocked and the regions to be doped 103 and 104 are not implanted, so that the ion dose implanted into the regions to be doped 103 and 104 is reduced under the same ion implantation dose provided by the implantation equipment, so that the doping concentration of the lightly doped regions 160 and 170 is reduced, and under the same voltage, the depletion rate of the drain region becomes slow, and the depletion layers of the source region and the drain region are not easily connected, so that the penetration phenomenon is not easily generated, the leakage current is improved, and the electrical performance of the semiconductor device is improved.
Further, as shown in fig. 3, in the first embodiment, the blocking layer 150 includes a plurality of blocking bars arranged at intervals, the blocking bars serve as the blocking regions 151, and gaps between adjacent blocking bars serve as the hollow-out regions 152. The spacing between the barrier ribs (i.e., the width of the hollow-out area 150) can be determined according to the doping concentration required by the regions to be doped 103 and 104. If the doping concentration required by the regions to be doped 103 and 104 is high, the interval between the barrier ribs is increased, and if the doping concentration required by the regions to be doped 103 and 104 is low, the interval between the barrier ribs is decreased. The width of the barrier rib, i.e. the barrier region 151, may also be determined according to the required doping concentration of the regions to be doped 103 and 104. Further, the width of the barrier rib is 60 nm-0.5 μm.
Further, in the first embodiment, the barrier ribs are disposed along the width direction of the channel region 120, and in other embodiments of the present invention, for example, referring to fig. 4, in the second embodiment, the barrier ribs are disposed along the length direction of the channel region 120, referring to fig. 5, and in the third embodiment, the barrier ribs are disposed obliquely; referring to fig. 6, in the fourth embodiment, the barrier ribs are arranged in different directions. The above description is only used to illustrate the arrangement of the barrier ribs, and it is understood that other arrangements of the barrier ribs may be used.
In the above embodiment, the blocking region 151 is formed by a blocking strip, and in the fifth embodiment of the present invention, the blocking region is formed by a plurality of concentric blocking rings arranged at intervals. Specifically, referring to fig. 7, a plurality of blocking rings 153 are concentrically disposed, the blocking rings 153 serve as the blocking regions for blocking the regions to be doped 103 and 104, and a gap 154 between adjacent blocking regions 153 serves as the hollow region to expose the regions to be doped 103 and 104.
In the sixth embodiment of the present invention, the blocking region may also be formed by a plurality of blocking blocks arranged in a matrix. Specifically, referring to fig. 8, a plurality of blocking blocks 155 are arranged in an array, the blocking blocks 155 serve as the blocking regions for blocking the regions to be doped 103 and 104, and gaps 156 between adjacent blocking blocks 155 serve as the hollow regions to expose the regions to be doped 103 and 104.
Compared with the prior art that the doping amount of a lightly doped region (LDD) is reduced by directly adjusting the ion implantation amount of ion implantation equipment, the preparation method of the invention forms the barrier layer in the region (wide tube region) needing to reduce the doping amount of the lightly doped region, reduces the doping amount of the region through the shielding effect of the barrier layer, and does not reduce the doping amount of the region through adjusting the ion implantation amount of the ion implantation equipment, thereby avoiding that the doping amount of the region (narrow tube region) not needing to reduce the doping amount of the lightly doped region is also reduced.
Further, the present invention provides a seventh embodiment. Referring to fig. 9, which is a schematic top view of a semiconductor structure according to a seventh embodiment of the present invention, the semiconductor device includes a first-type transistor 100A and a second-type transistor 100B. The first-type transistor 100A includes a first gate 110A, a first source 130A, a first drain 140A, and a first channel region 120A, and the second-type transistor 100B includes a second gate 110B, a second source 130B, a second drain 140B, and a second channel region 120B. Wherein a width W1 of the first channel region 120A of the first-type transistor 100A is greater than a width W2 of the second channel region 120B of the second-type transistor 100B. The barrier layer 150 is formed only in the corresponding regions of the lightly doped regions 160A and 170A of the first-type transistor 100A, and is not formed in the corresponding regions of the lightly doped regions 160B and 170B of the second-type transistor 100B, so that the doping concentrations of the lightly doped regions 160A and 170A of the first-type transistor 100A are less than those of the lightly doped regions 160B and 170B of the second-type transistor 100B.
The invention also provides a semiconductor device prepared by the preparation method. Referring to fig. 2D, the semiconductor device includes a substrate layer 100, a gate 110, a source 130, a drain 140, a channel region 120, lightly doped regions 160 and 170, and a patterned barrier layer 150.
The gate 110 is disposed on the substrate layer 100; the source 130 and the drain 140 are disposed in the substrate layer 100 and located at two sides of the gate 110; the channel region 120 is disposed in the base layer 110, and corresponds to the gate 110; the lightly doped regions 160 and 170 are disposed in the substrate layer 100 and located between the source 130 and the gate 110 and between the drain 140 and the gate 110; a patterned barrier layer 150 is disposed on the substrate layer 100 and blocks portions of the lightly doped regions 160 and 170. The arrangement of the blocking layer 150 is shown in fig. 3 to 8, and is not described again.
Further, the semiconductor device includes a first type transistor and a second type transistor. Specifically, referring to fig. 9, the semiconductor device includes a first-type transistor 100A and a second-type transistor 100B. The first-type transistor 100A includes a first gate 110A, a first source 130A, a first drain 140A, and a first channel region 120A, and the second-type transistor 100B includes a second gate 110B, a second source 130B, a second drain 140B, and a second channel region 120B.
Wherein a width W1 of the first channel region 120A of the first-type transistor 100A is greater than a width W2 of the second channel region 120B of the second-type transistor 100B. The barrier layer 150 is formed only in the corresponding regions of the lightly doped regions 160A and 170A of the first-type transistor 100A, and is not formed in the corresponding regions of the lightly doped regions 160B and 170B of the second-type transistor 100B, so that the doping concentrations of the lightly doped regions 160A and 170A of the first-type transistor 100A are less than the doping concentrations of the lightly doped regions 160B and 170B of the second-type transistor 100B.
The semiconductor device can avoid the generation of leakage current of the first type transistor 100A (wide tube) and the influence on the breakdown voltage of the second type transistor 100B (narrow tube), and the size and the process of the semiconductor device cannot be increased additionally, so that the method is simple and feasible.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims (11)

1. A method for manufacturing a semiconductor device, comprising the steps of:
providing a substrate layer, wherein a grid electrode is arranged on the substrate layer, a source electrode region, a drain electrode region and a channel region are arranged in the substrate layer, the grid electrode corresponds to the channel region, and the source electrode region and the drain electrode region are arranged on two sides of the grid electrode;
forming a graphical blocking layer on the substrate layer, the region to be doped between the source region and the grid electrode and the region to be doped between the drain region and the grid electrode, wherein the blocking layer shields part of the region to be doped at intervals;
and doping the region to be doped to form a lightly doped region.
2. The method of claim 1, wherein the barrier layer comprises blocking regions and hollow-out regions, the blocking regions and the hollow-out regions are alternately arranged, and the hollow-out regions expose the substrate layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the barrier layer comprises a plurality of barrier ribs arranged at intervals, the barrier ribs serve as the barrier regions, and gaps between adjacent barrier ribs serve as the hollow regions.
4. The method for manufacturing a semiconductor device according to claim 2, wherein the barrier layer comprises a plurality of concentric barrier rings arranged at intervals, the barrier rings serve as the barrier regions, and gaps between adjacent barrier rings serve as the hollow regions.
5. The method of manufacturing a semiconductor device according to claim 2, wherein the barrier layer includes a plurality of barrier blocks arranged in a matrix, the barrier blocks serve as the barrier regions, and gaps between adjacent barrier blocks serve as the hollow regions.
6. The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein the width of the barrier region is 60nm to 0.5 μm.
7. The method of claim 1, wherein the source and drain regions are doped to form source and drain regions prior to forming the barrier layer.
8. The method of claim 1, wherein the source and drain regions are doped after or before the lightly doped region is formed to form a source region and a drain region.
9. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device comprises a first type transistor and a second type transistor, a channel region width of the first type transistor is larger than a channel region width of the second type transistor, and the blocking layer is formed only on a region to be doped of the first type transistor.
10. A semiconductor device manufactured by the manufacturing method of any one of claims 1 to 8, comprising:
a base layer;
a gate disposed on the base layer;
a source and a drain disposed in the substrate layer and on both sides of the gate,
the channel region is arranged in the substrate layer and corresponds to the grid electrode;
the lightly doped region is arranged in the substrate layer and is positioned between the source electrode and the grid electrode and between the drain electrode and the grid electrode;
and the patterned barrier layer is arranged on the substrate layer and shields part of the lightly doped region at intervals.
11. The semiconductor device according to claim 10, wherein the semiconductor device comprises a first type transistor and a second type transistor, a channel region width of the first type transistor is larger than a channel region width of the second type transistor, the barrier layer is formed only on a region to be doped of the first type transistor, and a doping concentration of a lightly doped region of the first type transistor is smaller than a doping concentration of a lightly doped region of the second type transistor.
CN202011089159.7A 2020-10-13 2020-10-13 Semiconductor device and method for manufacturing the same Pending CN112233981A (en)

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