CN112201690B - MOSFET transistor - Google Patents

Abstract

The invention discloses a MOSFET transistor, which comprises: a substrate; a buffer layer; a drift region; doping the base region; a cap layer; a plurality of grooves; the trenches extend from one side of the cap layer to one side of the substrate and extend into the drift region; the heavy doping regions are positioned in the drift region and at the bottom of the groove, and the first metal layer covers part of the table surface, part of the bottom of the groove and the side wall connected with part of the bottom; a gate dielectric layer and a gate electrode; a first electrode and a second electrode; the MOSFET transistor has a first cell region and a second cell region. Therefore, by arranging the groove, the first primitive cell region and the second primitive cell region, the electric field shielding of the heavily doped region to the groove gate is realized, the electric connection between the doped base region and the second electrode is realized, and meanwhile, the Schottky diode is also reversely connected in parallel, so that the preparation difficulty of the MOSFET transistor can be reduced, the production cost of the MOSFET transistor can be reduced, and the on-resistance of the MOSFET transistor can be reduced on the basis that the primitive cell size is not influenced.

Description

MOSFET Transistor

Technical Field

The invention relates to the field of semiconductors, and in particular to a MOSFET transistor.

Background Art

Compared with Si, the wide bandgap semiconductor material SiC has about 3 times the bandgap width, 10 times the critical breakdown electric field strength, and 3 times the thermal conductivity. Therefore, SiC MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has higher voltage resistance, higher operating frequency, and higher temperature resistance than Si-based IGBT (Insulated Gate Bipolar Transistor). Both in theory and in practice, it has been confirmed that SiC MOSFET has a switching frequency of more than 10 and better switching efficiency than Si-based IGBT. However, due to the high cost of SiC materials, immature technology, and difficult preparation process, the cost of SiC MOSFET is high.

On the other hand, in many applications, such as full-bridge applications, transistors need to work in parallel with a freewheeling diode. For example, the commonly used Si-based IGBT modules currently use Si fast recovery diodes in parallel as freewheeling diodes. Because the internal parasitic pn diode of SiC MOSFET has a high turn-on voltage and large losses, it often requires an anti-parallel SiC Schottky diode as a freewheeling diode. If a freewheeling diode is integrated in a device (MOSFET transistor), it can not only improve the integration and reliability of the chip, but also effectively reduce the chip cost. However, in the prior art, when a Schottky diode is integrated in a MOSFET chip, the size of the original cell will increase, which will lead to an increase in the on-resistance.

Summary of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present invention is to provide a MOSFET transistor, which, by setting a trench, a first primitive cell region and a second primitive cell region, realizes electric field shielding of the heavily doped region on the trench gate, realizes electrical connection between the doped base region and the second electrode, and also connects a Schottky diode in reverse parallel, which can reduce the difficulty of preparing the MOSFET transistor without affecting the primitive cell size, and can also reduce the production cost of the MOSFET transistor, and can also reduce the on-resistance of the MOSFET transistor.

The MOSFET transistor according to the present invention comprises: a substrate; a buffer layer, the buffer layer is located on one side of the substrate; a drift region, the drift region is located on a side of the buffer layer away from the substrate; a doped base region, the doped base region is located on a side of the drift region away from the buffer layer; a cap layer, the cap layer is located on a side of the doped base region away from the drift region; a plurality of grooves, the plurality of grooves extend from one side of the cap layer to one side of the substrate and extend into the drift region; a plurality of heavily doped regions, the heavily doped regions are at least located in the drift region and at the bottom of the grooves; a first metal layer, the first metal layer covers The groove comprises a portion of the table top, a portion of the bottom and a side wall connected to the portion of the bottom; a gate dielectric layer and a gate, wherein the gate dielectric layer and the gate are located in the groove and an isolation dielectric is spaced between the gate and the first metal layer; a first electrode and a second electrode, wherein the first electrode is located on a side of the substrate away from the buffer layer, and the second electrode is filled in the groove and in contact with the first metal layer; the MOSFET transistor comprises a first cell region and a second cell region, and a portion of the heavily doped region located in the second cell region further extends to the side wall of the groove having the first metal layer.

According to the MOSFET transistor of the present invention, by providing the trench, the first primitive cell region and the second primitive cell region, compared with the prior art, the electric field shielding of the heavily doped region to the trench gate is achieved, and the reliability of the device gate is improved. The electrical connection between the doped base region and the second electrode is achieved, and the Schottky diode is also connected in reverse parallel. On the basis of not affecting the primitive cell size, the difficulty of preparing the MOSFET transistor can be reduced, the production cost of the MOSFET transistor can be reduced, and the on-resistance of the MOSFET transistor can also be reduced.

In some examples of the present invention, an ohmic contact is formed between the first metal layer in the second cell region and the heavily doped region at the sidewall of the groove and at the bottom of the groove, and an ohmic contact is formed between the first metal layer in the second cell region and the cap layer on the portion of the table surface; a Schottky contact is formed between the first metal layer in the first cell region and the drift region, and an ohmic contact is formed between the first metal layer in the first cell region and the cap layer on the portion of the table surface.

In some examples of the present invention, the substrate, the buffer layer, the drift region, and the cap layer have a first doping type, and the doped base region and the heavily doped region have a second doping type.

In some examples of the present invention, the substrate and the cap layer are both heavily doped, and the drift region is lightly doped.

In some examples of the present invention, a distance D between an orthographic projection of the heavily doped region on the substrate and an orthographic projection of the gate sidewall of the trench on the substrate satisfies: 0≤D≤Th, where Th is the sum of the widths of the gate and the isolation medium.

In some examples of the present invention, the thickness of the doped base region is not less than 0.2 microns.

In some examples of the present invention, the depth of the trench is greater than the thickness of the doped base region.

In some examples of the present invention, the depth of the portion of the trench extending into the drift region is not less than 0.2 microns.

In some examples of the present invention, the MOSFET transistor further includes: a lightly doped conductive layer, the lightly doped conductive layer is located in the drift region and between two adjacent heavily doped regions, the doping type of the lightly doped conductive layer is the same as the doping type of the drift region, and the doping concentration is greater than the doping concentration of the drift region.

Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

FIG1 is a schematic structural diagram of a first primitive cell region of a MOSFET transistor according to an embodiment of the present invention;

2 is a schematic structural diagram of a second primitive cell region of a MOSFET transistor according to an embodiment of the present invention;

3 is a schematic structural diagram of a first primitive cell region and a second primitive cell region of a MOSFET transistor according to an embodiment of the present invention;

4 is a perspective view of a first primitive cell region and a second primitive cell region of a MOSFET transistor according to an embodiment of the present invention;

FIG. 5 is a circuit structure diagram of a MOSFET transistor chip according to an embodiment of the present invention.

Reference numerals:

MOSFET transistor 100;

Gate 1; first electrode 2; second electrode 3;

substrate 10; buffer layer 20; drift region 30; doped base region 40; cap layer 50; trench 60; heavily doped region 70; first metal layer 80; gate dielectric layer 90; isolation dielectric 11;

A first primitive cell region 110; a second primitive cell region 120; an ohmic contact 130; and a Schottky contact 140;

Schottky diode 200; lightly doped conductive layer 300.

DETAILED DESCRIPTION

Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

The following describes a MOSFET transistor 100 according to an embodiment of the present invention with reference to FIGS. 1 to 5 .

As shown in FIGS. 1 to 5 , a MOSFET transistor 100 according to an embodiment of the present invention includes: a substrate 10, a buffer layer 20, a drift region 30, a doped base region 40, a cap layer 50, a plurality of trenches 60, a plurality of heavily doped regions 70, a first metal layer 80, a gate dielectric layer 90, a gate 1, a first electrode 2, and a second electrode 3. The doping type of the substrate 10 may be n-type heavily doped low resistivity, and the buffer layer 20 is located on one side of the substrate 10. It should be noted that in the up-down direction shown in FIG. 1 , the buffer layer 20 may be located above the substrate 10. The drift region 30 is located on the side of the buffer layer 20 away from the substrate 10. It should be noted that in the up-down direction shown in FIG. 1 , the drift region 30 may be located above the buffer layer 20, the buffer layer 20 may be located between the drift region 30 and the substrate 10, and one side of the drift region 30 may be in contact with the buffer layer 20. The doped base region 40 is located on the side of the drift region 30 away from the buffer layer 20. It should be noted that in the up-down direction shown in FIG1 , the doped base region 40 can be located above the drift region 30. The cap layer 50 is located on the side of the doped base region 40 away from the drift region 30. It should be explained that in the up-down direction shown in FIG1 , the cap layer 50 can be located above the doped base region 40, and one side of the doped base region 40 can be in contact with the cap layer 50. The doping type of the cap layer 50 can be n-type heavy doping. A plurality of grooves 60 extend from one side of the cap layer 50 to one side of the substrate 10 and extend into the drift region 30. It should be noted that in the up-down, down-left, and right directions shown in FIG1 , the groove 60 can extend downward from the left side of the cap layer 50, the groove 60 can extend downward from the right side of the cap layer 50, and the plurality of grooves 60 can also extend downward from both the left and right sides of the cap layer 50 at the same time. The heavily doped region 70 is at least located in the drift region 30 and at the bottom of the trench 60. It should be explained that the heavily doped region 70 may be a heavily doped concentration p region, at least a portion of the heavily doped region 70 is located in the drift region 30, and at least a portion of the heavily doped region 70 is located at the bottom of the trench 60. The first metal layer 80 covers a portion of the bottom of the trench 60, a portion of the mesa, and a sidewall connected to the portion of the bottom. It should be noted that the first metal layer 80 may cover the sidewall of the trench 60 connected to the portion of the bottom of the trench 60, that is, the sidewall in the trench away from the gate 1, and the first metal layer 80 may also cover a portion of the bottom of the trench 60 and the cap layer 50 on the portion of the mesa. The gate dielectric layer 90 and the gate 1 are located in the groove 60 and an isolation dielectric 11 is provided between the gate 1 and the first metal layer 80. It should be explained that, in the left-right direction shown in FIG. 1 , the gate 1 can be located in the groove 60 and the gate 1 can be arranged close to the left side of the adjacent doped base region 40 and the cap layer 50, and the isolation dielectric 11 can be located between the gate 1 and the first metal layer 80; the gate dielectric layer 90 can be located in the groove 60 and the gate 1 can be arranged close to the right side of the adjacent doped base region 40 and the cap layer 50, and a portion of the gate dielectric layer 90 can be arranged between the gate 1 and the doped base region 40. The first electrode 2 is located on the side of the substrate 10 away from the buffer layer 20, and the second electrode 3 is filled in the groove 60 and in contact with the first metal layer 80. It should be noted that in the up and down direction shown in FIG. 1, the first electrode 2 can be located below the substrate 10, and it can also be understood that the substrate 10 can be located between the first electrode 2 and the buffer layer 20, the second electrode 3 can be arranged above the groove 60, a part of the second electrode 3 can be filled in the groove 60, and the second electrode 3 is in contact with the first metal layer 80. The MOSFET transistor 100 has a first primitive cell region 110 and a second primitive cell region 120, and a part of the heavily doped region 70 located in the second primitive cell region 120 further extends to the side wall of the groove 60 on the side with the first metal layer 80. It should be explained that a part of the heavily doped region 70 located in the second primitive cell region 120 can extend to the side wall of the groove 60 with the first metal layer 80.

Among them, in the second original cell region 120, a part of the heavily doped region 70 can extend to the side wall of the trench 60, that is, away from the side wall of the gate 1, and the doped base region 40 can be connected to the second electrode 3 through the heavily doped region 70 at the side wall of the trench 60 in the second original cell region 120, so as to achieve a short circuit of the second electrode 3, the doped base region 40, and the cap layer 50, thereby suppressing the bipolar junction transistor effect of the MOSFET transistor 100. The active area of the MOSFET transistor 100 can be composed of two structures of primitive cell regions, and the primitive cell regions of the two structures can be a first primitive cell region 110 and a second primitive cell region 120 respectively. The first primitive cell region 110 and the second primitive cell region 120 can be arranged asymmetrically, and multiple trenches 60 can be located in the first primitive cell region 110 and/or the second primitive cell region 120. Specifically, in the left and right directions shown in Figure 1, the right side of the trench 60 can be the gate 1 and the gate dielectric layer 90, and the left side of the trench 60 can be the second electrode 3 and the first metal layer 80. The gate 1 and the second electrode 3 can be isolated by an isolation medium 11.

Thus, by providing the trench 60, the first primitive cell region 110 and the second primitive cell region 120, compared with the prior art, the heavily doped region shields the trench gate from the electric field, thereby improving the reliability of the device gate. The doped base region 40 is electrically connected to the second electrode 3, and the Schottky diode 200 is also connected in reverse parallel. Without affecting the size of the primitive cell, the difficulty of preparing the MOSFET transistor 100 can be reduced, the production cost of the MOSFET transistor 100 can be reduced, and the on-resistance of the MOSFET transistor 100 can also be reduced.

In some embodiments of the present invention, as shown in FIGS. 1 to 4 , an ohmic contact 130 may be formed between the first metal layer 80 in the second cell region 120 and the heavily doped region 70 at the sidewall of the trench 60 and at the bottom of the trench 60, and an ohmic contact 130 may be formed between the first metal layer 80 and the cap layer 50 on a portion of the mesa. A Schottky contact 140 may be formed between the first metal layer 80 in the first cell region 110 and the drift region 30, and an ohmic contact 130 may be formed between the first metal layer 80 and the cap layer 50 on a portion of the mesa. It should be noted that, in the second cell region 120, an ohmic contact 130 may be formed between the first metal layer 80 and the heavily doped region 70 at the sidewall of the trench 60, and at the same time, a portion of the first metal layer 80 may cover a portion of the mesa, and the first metal layer 80 may form an ohmic contact 130 with the cap layer 50 on a portion of the mesa. In the first cell region 110, the first metal layer 80 in the groove 60 can form a Schottky contact 140 with the n-type lightly doped drift region 30, and the first metal layer 80 in the groove 60 can also form a Schottky contact 140 with the doped base region 40. At the same time, a portion of the first metal layer 80 can cover a portion of the table surface, and the first metal layer 80 can form an ohmic contact 130 with the cap layer 50 on the portion of the table surface.

Furthermore, the primitive cells of the active area may be arranged in the same plane and alternately, and the arrangement period of the first primitive cell area 110 and the second primitive cell area 120 and the corresponding area ratio may be determined according to the size of the freewheeling current. For example, the arrangement of the primitive cells in the active area may be the first primitive cell area 110, the second primitive cell area 120, the first primitive cell area 110, the second primitive cell area 120, or the arrangement of the primitive cells in the active area may be the first primitive cell area 110, the first primitive cell area 110, the second primitive cell area 120, the first primitive cell area 110, the first primitive cell area 110, the second primitive cell area 120, but the present invention is not limited thereto. The arrangement of the primitive cells in the active area may also be other forms. The larger the proportion of the first primitive cell area 110, the stronger the freewheeling capability.

As an embodiment, as shown in Figures 1 to 4, the second electrode 3 can be electrically connected to the cap layer 50 on the table, the doped base region 40, the heavily doped region 70 in the groove 60, the heavily doped region 70 on the side wall of the groove 60, and the Schottky contact 140, and the heavily doped regions 70 are respectively arranged on both sides of the Schottky contact 140 in the first cell region 110, so that a Schottky diode 200 (MPS) structure embedded in a pn diode can be formed. Such a setting can shield the electric field at the Schottky contact 140 and reduce the reverse bias leakage current of the Schottky diode 200. At the same time, the parallel pn diode can also inject minority carriers to modulate the conductivity when the current is large, thereby increasing the surge current capability of the Schottky diode 200.

In some embodiments of the present invention, the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may have a first doping type, and the doped base region 40 and the heavily doped region 70 may have a second doping type. It should be noted that the first doping type may be n-type doping, and the second doping type may be p-type doping, that is, the doping type of the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may be n-type doping, and the doping type of the doped base region 40 and the heavily doped region 70 may be p-type doping, but the present invention is not limited thereto. The substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may have a second doping type, and the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 may have a second doping type. While the buffer layer 20, the drift region 30 and the cap layer 50 have the second doping type, the doped base region 40 and the heavily doped region 70 can have the first doping type, that is, the doping type of the substrate 10, the buffer layer 20, the drift region 30 and the cap layer 50 can be p-type doping, and the doping type of the doped base region 40 and the heavily doped region 70 can be n-type doping. This arrangement can flexibly change the doping type of the substrate 10, the buffer layer 20, the drift region 30, the cap layer 50, the doped base region 40 and the heavily doped region 70, thereby reducing the manufacturing difficulty of the MOSFET transistor 100 and further improving the manufacturing efficiency of the MOSFET transistor 100.

In some embodiments of the present invention, the substrate 10 and the cap layer 50 can both be heavily doped, and the drift region 30 can be lightly doped. It should be explained that the concentration of the doped base region 40 depends on the designed threshold voltage. The substrate 10 and the cap layer 50 can both be heavily doped with p-type, and the substrate 10 and the cap layer 50 can also be heavily doped with n-type. The drift region 30 can be lightly doped with p-type, and the drift region 30 can also be lightly doped with n-type. When the substrate 10 is heavily doped with p-type, the drift region 30 is lightly doped with p-type, the cap layer 50 is heavily doped with p-type, and the doped base region 40 is n-doped. When the substrate 10 is heavily doped with n-type, the drift region 30 is lightly doped with n-type, the cap layer 50 is heavily doped with n-type, and the doped base region 40 is p-doped. This arrangement can flexibly change the doping types of the substrate 10, the drift region 30, and the doped base region 40, thereby facilitating the manufacture of the MOSFET transistor 100.

In some embodiments of the present invention, the distance D between the orthographic projection of the heavily doped region 70 on the substrate 10 and the orthographic projection of the gate sidewall of the trench 60 on the substrate 10 may satisfy: 0≤D≤Th, where Th is the sum of the widths of the gate 1 and the isolation dielectric 11. It can also be understood that the orthographic projection of the heavily doped region 70 on the substrate 10 may coincide with the orthographic projection of the gate sidewall of the trench 60 on the substrate 10, and the length of the orthographic projection of the gate sidewall of the trench 60 on the substrate 10 may also be greater than the length of the orthographic projection of the heavily doped region 70 on the substrate 10, but the length of the orthographic projection of the sidewall of the trench 60 on the substrate 10 is greater than the length of the orthographic projection of the heavily doped region 70 on the substrate 10 and cannot be greater than the sum of the widths of the gate 1 and the isolation dielectric 11, and the distance between the orthographic projection of the heavily doped region 70 on the substrate 10 and the orthographic projection of the sidewall of the trench 60 on the substrate 10 may be designed according to the material structure and the performance of the MOSFET transistor 100, and such a setting can ensure that the ohmic contact 130 in the trench 60 is on the heavily doped region 70.

In some embodiments of the present invention, the thickness of the doped base region 40 may be not less than 0.2 microns to avoid punch-through of the base region. It should be noted that the concentration and thickness of the doped base region 40 may be formed by epitaxial growth or increased by ion implantation. According to the threshold voltage design and the breakdown voltage design, the thickness of the doped base region 40 may be greater than 0.2 microns. If the thickness of the doped base region 40 is too thin, it is easy to punch through. If the thickness of the doped base region 40 is too thick, the length and resistance of the trench 60 will be increased. At the same time, the doping concentration of the doped base region 40 may be set at 1×e ¹⁵ cm ^-3 -5×e ¹⁷ cm ^-3 . Such a setting can make the MOSFET transistor 100 have better working performance.

In some embodiments of the present invention, the thickness of the doped base region 40 can be 0.2-1 microns. It should be explained that the thickness of the doped base region 40 can be set between 0.2-1 microns. Preferably, the thickness of the doped base region 40 can be set to 0.5 microns. Such a setting can facilitate the production of the MOSFET transistor 100, and can also ensure that the MOSFET transistor 100 has better working performance.

As an embodiment, the doping concentration of the cap layer 50 located above the doped base region 40 may be greater than 1×e ¹⁹ cm ⁻³ , and the thickness of the cap layer 50 located above the doped base region 40 may be greater than 0.1 micron. Preferably, the thickness of the cap layer 50 is between 0.2 and 1 micron. Such a configuration can prevent the ohmic contact 130 from being easily penetrated, can prevent the on-resistance from being too large, and can also reduce the difficulty of etching the trench 60 .

In some embodiments of the present invention, the doping concentration of the heavily doped region 70 may be greater than 1×e ¹⁹ cm ^-3 . It should be noted that the heavily doped region 70 at the bottom of the trench 60 and the doped base region 40 may be electrically connected by performing p-type heavy doping on the sidewall of the trench 60 . The heavily doped region 70 at the bottom of the trench 60 and the heavily doped region 70 on the sidewall of the trench 60 may be formed by ion implantation in a vertical direction and ion implantation in an oblique direction. Thus, the second electrode 3 may be electrically connected to the doped base region 40 at the same time, thereby suppressing the bipolar junction transistor effect of the MOSFET transistor 100 and improving the reliability of the MOSFET transistor 100 . Furthermore, the doping concentration of the heavily doped region 70 at the bottom of the trench 60 and the heavily doped region 70 on the sidewall of the trench 60 may be greater than 1×e ¹⁹ cm ^-3 . Such a configuration is conducive to forming a good ohmic contact 130 .

In some embodiments of the present invention, the depth of the trench 60 structure may be greater than the thickness of the doped base region 40. It should be explained that when the depth of the trench 60 structure is greater than the thickness of the doped base region 40, the MOSFET transistor 100 may have better operating performance.

In some embodiments of the present invention, the depth of the portion of the groove 60 extending into the drift region 30 may be no less than 0.2 microns. It should be noted that the depth of the portion of the groove 60 extending into the drift region 30 may be 0.2 microns, and the depth of the portion of the groove 60 extending into the drift region 30 may be greater than 0.2 microns. The portion of the groove 60 extending into the drift region 30 may become a portion of the Schottky contact 140 region in the first cell region 110. The spacing between the p-type heavily doped regions in the two grooves 60 must meet the requirements for electric field shielding of the trench gate and the Schottky contact 140, and at the same time, a low-resistance conductive channel needs to be provided, thereby enabling the MOSFET transistor 100 to have better operating performance.

In some embodiments of the present invention, the MOSFET transistor 100 may further include: a lightly doped conductive layer 300 (n-type conductive layer), the lightly doped conductive layer 300 may be located in the drift region 30 and may be located between two adjacent heavily doped regions 70, the doping type of the lightly doped conductive layer 300 may be the same as the doping type of the drift region 30, and the doping concentration may be greater than the doping concentration of the drift region 30. It needs to be explained that a JFET (Junction Field-Effect Transistor) region can be provided between two adjacent heavily doped regions 70, and a lightly doped conductive layer 300 can be located in the drift region 30. The lightly doped conductive layer 300 can be located between two adjacent heavily doped regions 70. If the doping type of the drift region 30 is n-type doping, the doping type of the lightly doped conductive layer 300 is n-type doping. If the doping type of the drift region 30 is p-type doping, the doping type of the lightly doped conductive layer 300 is p-type doping. The doping concentration of the lightly doped conductive layer 300 can be greater than the doping concentration of the drift region 30. However, the effect of electric field shielding needs to be considered when designing the doping concentration of the lightly doped conductive layer 300. If the doping concentration of the lightly doped conductive layer 300 is too high, the electric field shielding of the trench 60 and the Schottky contact 140 will be weak. Such a setting can further reduce the on-resistance of the JFET region.

As an embodiment, the width of the JFET region can be smaller than the width of the entire cell. The smaller the width of the JFET region, the better the shielding effect of the heavily doped region 70 on the gate dielectric electric field at the bottom of the trench 60. Therefore, reducing the width of the JFET region can increase the reliability of the MOSFET transistor 100, and increasing the doping concentration of the JFET region can reduce the on-resistance of the JFET region. The high doping concentration below the heavily doped region 70 is conducive to better diffusion of carriers in all directions of the drift layer 30 after passing through the trench 60, thereby reducing the on-resistance. The drift layer 30 below the JFET region serves as the withstand voltage drift layer 30 of the MOSFET transistor 100. The doping concentration and doping thickness of the drift layer 30 can be determined according to the withstand voltage capability of the MOSFET transistor 100. For example, for a 1200V MOSFET transistor 100, the concentration can be 5×e ¹⁵ cm ^-3 -20×e ¹⁵ cm ^-3 , and the thickness can be between 7 and 15 microns.

In some embodiments of the present invention, the MOSFET transistor 100 may satisfy at least one of the following conditions: the material forming the substrate 10 includes SiC; the material forming the first metal layer 80 may include at least one of Ti, Mo, Ni, MoN, Pt, etc. The material forming the second electrode 3 may include at least one of TiAl, TiNiAg, TiAu, etc. The material forming the first electrode 2 may include TiNiAg, and the thickness of the first electrode 2 may be greater than 1 micron. The material forming the isolation dielectric 11 may include SiO ₂ and Si ₃ N _4. It should be noted that the material forming the isolation dielectric 11 may include one or more of SiO ₂ and Si _{3 N 4.} The gate 1 is a polysilicon gate. It should be noted that the material forming the gate ₁ may be polysilicon. Such a setting can facilitate the MOSFET transistor 100, and at _the same time, the MOSFET transistor 100 of different materials can be selected according to different situations, so as to improve the performance of the MOSFET transistor 100.

It should be noted that, since the sidewalls of the trench 60 are on other crystal planes, the thermal oxidation rate is more than twice that of the bottom surface of the trench 60. Therefore, the gate dielectric at the bottom of the trench 60 is much smaller than that at the sidewalls of the trench 60 by using a general thermal oxidation method to grow the gate dielectric, resulting in a large electric field at the bottom of the trench 60 under the working gate voltage of the MOSFET transistor 100, and even breakdown, which reduces the reliability and life of the MOSFET transistor 100. Therefore, in the gate dielectric preparation process, polysilicon can be first deposited by LPCVD method to make the thickness of the polysilicon at the bottom of the trench 60 greater than the thickness of the sidewalls of the trench 60, and then thermally oxidized, and then annealed in an atmosphere of NO or _N2O , _POCl3 , etc. to improve interface traps. The total SiO2 thickness at the bottom of the trench 60 is finally greater than or equal to that at the sidewalls of the trench 60. The gate dielectric thickness at the sidewalls of the trench 60 meets the design requirement of 20-100 nanometers.

The gate-source isolation dielectric 11 on the polysilicon can be SiO ₂ or Si ₃ N ₄ . The isolation dielectric 11 of the second electrode 3 and the polysilicon gate 1 in the trench 60 is preferably SiO ₂ , and preferably has a thickness greater than 0.5 microns. It can be generated by thermally oxidizing polysilicon, or by depositing SiO ₂ by LPCVD and then etching, or by a combination of the two, that is, first thermally oxidizing polysilicon and then depositing SiO ₂ by LPCVD.

The first metal layer 80 can be a metal such as Ti, Ni, Mo, MoN, Pt, etc., and annealing is performed after deposition to improve the Schottky contact 140. At the same time, due to the high doping concentration of the p+ region and the n+ region surface greater than 1E19cm- ³ , a good ohmic contact 130 is formed with the heavily doped region 70 in the groove 60 and the cap layer 50 on the table. In addition, there is another method, in which polysilicon is used on the side wall of the groove 60. Since the Fermi level of polysilicon is related to the doping concentration, the barrier height between SiC and the polysilicon is related to the doping concentration of polysilicon, and the barrier height can be adjusted by adjusting the doping concentration of polysilicon here. The heavily doped region 70 at the bottom of the groove 60 and the cap layer 50 on the table are formed of metal, such as Ni, and RTA is performed to form the ohmic contact 130 between the heavily doped region 70 at the bottom of the groove 60 and the cap layer 50 on the table, and the Schottky contact 140 is maintained at the side wall of the groove 60.

The metal of the second electrode 3 can be TiAl, TiNiAg, TiAu or the like, and the thickness is greater than 1 micrometer.

The first electrode 2 may include an ohmic contact of the first electrode 2 and a pressed metal of the first electrode 2 . The pressed metal may be TiNiAg or the like, and the thickness may be greater than 1 micrometer.

The entire MOSFET transistor 100 is composed of an active region, a junction terminal region and a scribe groove region, and the gate 1 and the second electrode 3 of each unit cell are respectively metal-leaded out on the active region and made with corresponding pressing block metal, which is beneficial to the subsequent packaging application of the MOSFET transistor 100.

It should be noted that, compared with the prior art, the gate channel of the MOSFET transistor 100 is only on one side of the trench 60, so the gate channel density is reduced by half, and the saturation current is reduced accordingly. The saturation current is determined by the channel resistance, and the short-circuit withstand time of the MOSFET transistor 100 is determined by the saturation current:

t _sC ＝4ρC _P ΔT _MAx /(E _C ×J _D,sat )

Where ρ is the semiconductor material density, C _P is the characteristic heat capacity of the material, ΔT _MAX is the maximum allowable temperature rise, and E _{C is} the critical electric field strength. Therefore, the saturation current is directly related to the short-circuit current withstand capability of the MOSFET transistor 100. Therefore, the short-circuit current capability of the MOSFET transistor 100 is doubled.

In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

In the description of the present invention, "plurality" means two or more.

In the description of the present invention, a first feature being “on” or “under” a second feature may include that the first and second features are directly in contact with each other, or may include that the first and second features are not in direct contact with each other but are in contact with each other via another feature therebetween.

In the description of the present invention, “on”, “over” and “above” a first feature from a second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims (9)

1. A kind of transistor of the MOSFET, characterized by comprising the following steps:

A substrate;

a buffer layer located at one side of the substrate;

A drift region located on a side of the buffer layer away from the substrate;

The doped base region is positioned at one side of the drift region far away from the buffer layer;

The cap layer is positioned on one side of the doped base region away from the drift region;

A plurality of trenches extending from one side of the cap layer to one side of the substrate and into the drift region;

A plurality of heavily doped regions at least in the drift region and at the bottom of the trench,

The first metal layer covers part of the table top and part of the bottom of the groove and the side wall connected with the part of the bottom;

The gate dielectric layer and the gate are positioned in the groove, an isolation medium is arranged between the gate and the first metal layer at intervals, and a part of the gate dielectric layer is arranged between the gate and the doped base region;

A first electrode and a second electrode, wherein the first electrode is positioned on one side of the substrate far away from the buffer layer, the second electrode is filled in the groove and is contacted with the first metal layer,

The MOSFET transistor is provided with a first primitive cell region and a second primitive cell region, and a part of the heavily doped region in the second primitive cell region further extends to the side wall of the groove on the side with the first metal layer.

2. The MOSFET transistor of claim 1, wherein said first metal layer in said second cell region forms an ohmic contact with said heavily doped region at said trench sidewalls and trench bottom and with a cap layer on said portion of the mesa;

And Schottky contact is formed between the first metal layer in the first primitive cell region and the drift region, and ohmic contact is formed between the first metal layer and the cap layer on the partial mesa.

3. The MOSFET transistor of claim 1, wherein the substrate, the buffer layer, the drift region, and the cap layer have a first doping type, and the doped base region and the heavily doped region have a second doping type.

4. A MOSFET transistor according to claim 3, characterized in that the substrate and the cap layer are heavily doped and the drift region is lightly doped.

5. The MOSFET transistor of claim 1, wherein a distance D between an orthographic projection of the heavily doped region on the substrate and an orthographic projection of a gate sidewall of the trench on the substrate satisfies:

0≤D≤Th，

And the Th is the sum of the widths of the grid electrode and the isolation medium.

6. The MOSFET transistor of claim 1, wherein a thickness of the doped base region is not less than 0.2 microns.

7. The MOSFET transistor of claim 1, wherein a depth of the trench is greater than a thickness of the doped base region.

8. The MOSFET transistor of claim 1, wherein a depth of a portion of the trench extending into the drift region is not less than 0.2 microns.

9. The MOSFET transistor of claim 1, further comprising:

the lightly doped conductive layer is positioned in the drift region and between two adjacent heavily doped regions, the doping type of the lightly doped conductive layer is the same as that of the drift region, and the doping concentration of the lightly doped conductive layer is larger than that of the drift region.