CN112183016A - Method, device, equipment and storage medium for quickly establishing equal-length constraints of pinpair - Google Patents
Method, device, equipment and storage medium for quickly establishing equal-length constraints of pinpair Download PDFInfo
- Publication number
- CN112183016A CN112183016A CN202011078170.3A CN202011078170A CN112183016A CN 112183016 A CN112183016 A CN 112183016A CN 202011078170 A CN202011078170 A CN 202011078170A CN 112183016 A CN112183016 A CN 112183016A
- Authority
- CN
- China
- Prior art keywords
- pinpair
- network
- starting point
- equal
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004590 computer program Methods 0.000 claims description 9
- 238000011161 development Methods 0.000 abstract description 4
- 230000005540 biological transmission Effects 0.000 description 10
- 238000005070 sampling Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000012545 processing Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/04—Constraint-based CAD
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/12—Printed circuit boards [PCB] or multi-chip modules [MCM]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a method, a device, equipment and a storage medium for quickly establishing equal-length constraints of pinpair. The method comprises the following steps: selecting a network group needing to establish equal-length constraints of pinpair, and designating a starting point device of pinpair; sequentially traversing each network in the network group to acquire all pin information of each network, and respectively taking the pin information belonging to and not belonging to a starting point device as a starting point and an end point of a pinpair for each network to create a corresponding pinpair; according to the starting point device and the end point device of each pinpair, each pinpair is added into the restriction group named by the corresponding starting point device and end point device. Compared with the prior art, the method for quickly establishing the Pinpair equal-length constraint can automatically create the Pinpair constraint group needing equal-length wiring in the designated network group by carrying out secondary development on PCB software, and finally guide the PCB to carry out equal-length wiring according to the constraint group, thereby avoiding errors caused by the operation of artificially generating the Pinpair constraint group and greatly improving the working efficiency and the accuracy.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a method, a device, equipment and a storage medium for quickly establishing equal-length constraints of pincarir.
Background
Data transmission is generally controlled by sequentially sending and receiving data signals through a clock. The chip can only send and receive data according to a specified time sequence, and the violation and functional disorder of the signal time sequence can be caused by overlong signal delay or improper signal delay matching, so that the chip cannot correctly receive and send data, and the system cannot normally work. For PCB design engineers, in order to ensure sufficient stability of system timing, the most effective approach is to ensure that transmission delays of signals on a PCB board are matched, that is, the lines of the signals to be matched are designed with equal length.
At present, isometric design is performed on one or more groups of signals, generally, on PCB design software (e.g., Allegro), corresponding pinpair (pad pair) is manually created, then isometric constraints are performed on the pinpair, and finally isometric wiring is directed on the PCB according to the isometric constraints.
However, with the development of technology, the PCB design is increasingly complex, the routing density is higher and higher, and the bus and the high-speed differential line which need to be controlled with equal length are more and more frequent, and the manual creation of the pincair mode has very low efficiency and is easy to make mistakes.
Disclosure of Invention
The invention aims to provide a method, a device, equipment and a storage medium for quickly establishing equal-length constraints of pincarir.
In order to achieve one of the above objects, an embodiment of the present invention provides a method for quickly establishing an isometric constraint of pincarir, where the method includes:
selecting a network group needing to establish equal-length constraints of pinpair, and designating a starting point device of pinpair;
sequentially traversing each network in the network group to acquire all pin information of each network, and respectively taking the pin information belonging to and not belonging to a starting point device as a starting point and an end point of a pinpair for each network to create a corresponding pinpair;
according to the starting point device and the end point device of each pinpair, each pinpair is added into the restriction group named by the corresponding starting point device and end point device.
As a further improvement of an embodiment of the present invention, the "creating, for each network, corresponding pinpair with pin information belonging to and not belonging to a starting point device as a starting point and an ending point of pinpair respectively" includes:
for each network, adding the pin information of the network belonging to the starting point device into a starting point list group of the corresponding network;
for each network, adding the pin information of the network which does not belong to the starting point device into a terminal list group of the corresponding network;
and respectively taking each pin information in the starting point list group as a starting point of the pinpair of the network, and respectively taking each pin information in the end point list group as an end point to establish corresponding pinpair.
As a further improvement of an embodiment of the present invention, each piece of pin information includes a device to which the pin belongs and a serial number of the pin in the device to which the pin belongs.
As a further improvement of an embodiment of the present invention, the "adding each pincair to a restriction group named with a corresponding start point device and end point device, respectively, according to the start point device and end point device of each pincair" includes:
each pincair comprises starting point pin information and end point pin information, and corresponding starting point devices and corresponding end point devices are obtained according to the starting point pin information and the end point pin information respectively;
each pincair is added to the set of constraints named with the corresponding origin and destination devices, respectively.
As a further refinement of an embodiment of the present invention, the name of each restriction group includes a prefix, a start device, and an end device.
As a further improvement of an embodiment of the present invention, the method further comprises:
and guiding all pinpair of the same constraint group to carry out equal-length wiring.
As a further improvement of an embodiment of the present invention, the number of the pin information in the start list group of a network is one or more. To achieve one of the above objects, an embodiment of the present invention provides an apparatus for quickly establishing equal-length pincair constraints:
the device uses the method for quickly establishing the equal-length constraints of pinpair.
In order to achieve one of the above objects, an embodiment of the present invention provides an electronic device, which includes a memory and a processor, where the memory stores a computer program that is executable on the processor, and the processor implements the steps in any one of the above methods for quickly establishing a Pinpair equal-length constraint when executing the program.
To achieve one of the above objects, an embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when executed by a processor, implements the steps in any one of the above methods for quickly establishing an isometric constraint of pincarir.
Compared with the prior art, the method for quickly establishing the pinpair equal-length constraint can automatically create the pinpair constraint group needing equal-length wiring in the designated network group by carrying out secondary development on PCB software (such as Allegro), and finally guide the PCB to carry out equal-length wiring according to the constraint group, thereby avoiding errors caused by the operation of artificially generating the pinpair constraint group and greatly improving the working efficiency and the accuracy.
Drawings
Fig. 1 is a sampling diagram of data arriving at the DDR terminal at the same clock when sampling points coincide.
Fig. 2 is a sampling chart of data sampling points arriving at the DDR terminal at the same clock, which are not consistent.
Fig. 3 is a schematic diagram of the structure of a data network of DDR _ DQ 0.
Fig. 4 is a flow chart of the method for quickly establishing equal length constraints of pinpair according to the present invention.
Detailed Description
The present invention will be described in detail below with reference to specific embodiments shown in the drawings. These embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to these embodiments are included in the scope of the present invention.
In order to improve the transmission rate of signals, many signals adopt a parallel signal transmission method, a plurality of data signals can be transmitted at one time, but the data signals can be correctly read only when meeting effective timing constraints without errors, so that the relative transmission time of the signals is basically consistent, and the signals can fall in an effective timing window at the same time.
Taking the DDR signal as an example, if 16 data lines are processed with equal length, and the driving strength of the CPU is consistent at this time, and the routing length is equal and the impedance is consistent, then the data transmission should be performed head-to-head, and then the data sampling points reaching the DDR end in the same clock are consistent. As shown in fig. 1, if the traces are consistent and equal in length, the data read at the clock sampling point is "00" under the same clock.
However, once the unequal length processing is performed, the problem as shown in fig. 2 may be caused: still with the data transmission the same as fig. 1, but the trace does not have isometric processing, so include transmission time and delay time in the actual transmission, because do not do isometric processing, then actual long trace will need more transmission time and delay time that comes more, will appear the situation of fig. 2 this moment, at the same sampling point, because of delaying, long trace data becomes 1 from "0", and whole data becomes "01", the data of transmission has changed this moment, the data error problem takes place. Therefore, equal length processing of the signals is required.
Fig. 3 is a network, U1 is CPU, U2, U3, U4 and U5 are DDR pellets (devices), signals from CPU to DDR pellets are data, address, control, clock, etc. signals in addition to this network, for a total of 30 more networks. During design, signals of U1-U2 are equal in length, signals of U1-U3 are equal in length, signals of U1-U4 are equal in length, and signals of U1-U5 are equal in length, so that correctness of signals such as data and commands can be guaranteed.
Assuming that one DDR grain has 16 pins (i.e., 16 pins), the net group consisting of devices U1 through U5 includes 16 data networks DDR _ DQ0 through DDR _ DQ 15. As shown in fig. 3, the data network of DDR _ DQ0 includes 5 pins, which are u1.dq0 to u5.dq0, and the data network of DDR _ DQ1 includes 5 pins, which are u1.dq1 to u5.dq1, and so on.
According to design requirements, the network lengths of the 16 data networks DDR _ DQ0 to DDR _ DQ15 need to be equal, but the network lengths of the 16 networks cannot be simply made equal, and in order to solve the problem more thoroughly, we need to make equal lengths between U1 and U2, equal lengths between U1 and U3, equal lengths between U1 and U4, and equal lengths between U1 and U5, so that pinpair (pad pair) needs to be set, for example, equal lengths between U1 and U2, we can set equal lengths between U1.dq0-U2.dq0, U1.dq1-U2.dq1 to U1.dq15-U2.dq15, which are 16 pairs of pinpair U1-U2, and then equal lengths between U1 to U2 are equal, so as to meet the design requirements.
According to the principle, the invention provides a method for quickly establishing Pinpair equal-length constraint, which can automatically create a Pinpair constraint group needing equal-length wiring in a designated network group by carrying out secondary development on PCB software (such as Allegro), and finally guide a PCB to carry out equal-length wiring according to the constraint group, thereby avoiding errors caused by the operation of artificially generating the Pinpair constraint group and greatly improving the working efficiency and the accuracy.
As shown in fig. 4, the method includes:
step S100: selecting a network group needing to establish equal-length constraints of the pinpair, and designating a starting point device of the pinpair.
The net group may be a net group consisting of devices U1-U5 as described above, including multiple nets (e.g., including 16 data nets DDR _ DQ 0-DDR _ DQ 15).
Then designating the starting device of pinpair, e.g., device U1 as the starting device, then the pins belonging to starting device U1 (e.g., U1.dq0 through U1.dq15) for each net are the starting points of pinpair.
Step S200: and traversing each network in the network group in sequence to acquire all pin information of each network, and for each network, respectively taking the pin information belonging to and not belonging to the starting point device as a starting point and an end point of the pinpair to create the corresponding pinpair.
And starting from the first network in the appointed network group, acquiring all pin information of the network, and adding the pin information of the network, which does not belong to the starting device, into the end point list group of the network. And adding the pin information of the network belonging to the starting point device into a starting point list group of the network, respectively taking the pin information in the starting point list group as the starting point of the pinpair of the network, and respectively taking each pin information in the end point list group as the end point to establish corresponding pinpair.
For example, for the DDR _ DQ0 data network shown in fig. 3, if U1 is designated as the starting device, then U1.dq0 is added to the starting listset of pinpair for this network, the other U2.dq0 to U5.dq0 are added to the ending listset of this network, and then the 4 pinpairs of U1.dq0 to U2.dq0, U1.dq0 to U3.dq0, U1.dq0 to U4.dq0, and U1.dq0 to U5.dq0 for the ending listset are established.
And then sequentially traversing the second network and the third network according to the operation until all the networks in the network group are traversed, and finally obtaining all the pinpair of the network group.
It should be noted that, for each network in the network group where the equal-length constraints of pinpair need to be established, there may be one or more pin information belonging to the starting point device, and when there are multiple pin information in one network as the starting points, multiple pinpairs of pinpairs are generated, for example, the starting points are u1.a1 and u1.b1, and the end points are u2.a1 and u2.b1, four pairs of pinpairs of u1.a1: u2.a1, u1.a1: u2.b1, u1.b1: u2.a1, and u1.b1: u2.b1 are generated.
It should be noted that each pin information includes the device to which the pin belongs and the serial number of the pin in the device to which the pin belongs, for example, the pin information U1.dq0 includes the device U1 to which the pin belongs and the serial number DQ0 in the device U1 to which the pin belongs.
Step S300: according to the starting point device and the end point device of each pinpair, each pinpair is added into the restriction group named by the corresponding starting point device and end point device.
Step S200 has automatically created all the pinpair of this network group, which this step needs to add to the corresponding restriction group.
Each pincair comprises starting point pin information and end point pin information, and corresponding starting point devices and corresponding end point devices are obtained according to the starting point pin information and the end point pin information. Each pincair is added to the set of constraints named with the corresponding origin and destination devices, respectively. Preferably, the name of the restriction group includes a prefix, a starting device and an end device. For example, the name of a constraint group may be RPD _ CPU _ DATA1_ U11-U28. It should be noted that before adding the corresponding constraint group, it is necessary to determine whether the constraint group exists, and if not, first perform an operation of creating the constraint group, and then add pinpair to the created constraint group. If the additive exists, the additive is directly added.
For example, in the case of pinpair from U1.dq0 to U2.dq0, the information of the starting point pin is U1.dq0, and thus the starting point device is U1, and the information of the ending point pin is U2.dq0, and thus the ending point device is U2. This pinpair is added to the constraint group RPD _ CPU _ DATA1_ U1-U2 named U1 and U2. Firstly, whether RPD _ CPU _ DATA1_ U1-U2 exists or not is judged, if not, the RPD _ CPU _ DATA1_ U1-U2 is created firstly and then added, otherwise, the RPD _ CPU _ DATA _ U is directly added.
Thus, all pinpair are added into the corresponding constraint group, and then all pinpair in the same constraint group are subjected to equal-length wiring.
By the method for quickly establishing the pinpair isometric constraint, the isometric constraint can be quickly and accurately set, the time is shortened from the previous minutes to even hours to the current seconds, and the working efficiency and the accuracy are greatly improved.
The invention also provides a device for quickly establishing the equal-length Pinpair constraint, and the device uses the scheme of the method for quickly establishing the equal-length Pinpair constraint.
The present invention further provides an electronic device, including a memory and a processor, where the memory stores a computer program operable on the processor, and the processor implements any one of the steps in the method for quickly establishing a Pinpair equal-length constraint, that is, implements the steps in any one of the technical solutions in the method for quickly establishing a Pinpair equal-length constraint.
The present invention further provides a computer-readable storage medium, on which a computer program is stored, where the computer program, when being executed by a processor, implements any one of the steps in the above method for quickly establishing a pinpair equal-length constraint, that is, implements the steps in any one of the above methods for quickly establishing a pinpair equal-length constraint.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (10)
1.A method for quickly establishing equal-length constraints of pinpair is characterized by comprising the following steps:
selecting a network group needing to establish equal-length constraints of pinpair, and designating a starting point device of pinpair;
sequentially traversing each network in the network group to acquire all pin information of each network, and respectively taking the pin information belonging to and not belonging to a starting point device as a starting point and an end point of a pinpair for each network to create a corresponding pinpair;
according to the starting point device and the end point device of each pinpair, each pinpair is added into the restriction group named by the corresponding starting point device and end point device.
2. The method for rapidly building equal-length constraints on pinpair according to claim 1, wherein the "for each network, using pin information belonging to and not belonging to a starting-point device as a starting point and an end point of pinpair respectively, and creating corresponding pinpair" comprises:
for each network, adding the pin information of the network belonging to the starting point device into a starting point list group of the corresponding network;
for each network, adding the pin information of the network which does not belong to the starting point device into a terminal list group of the corresponding network;
and respectively taking each pin information in the starting point list group as a starting point of the pinpair of the network, and respectively taking each pin information in the end point list group as an end point to establish corresponding pinpair.
3. The method for rapidly building equal-length Pinpair constraints according to claim 1, wherein the method comprises the following steps:
each piece of pin information comprises the device to which the pin belongs and the serial number of the pin in the device to which the pin belongs.
4. The method for rapidly building equal-length pinpair constraints according to claim 3, wherein the step of adding each pinpair to a constraint group named with a corresponding start device and end device according to the start device and end device of each pinpair comprises:
each pincair comprises starting point pin information and end point pin information, and corresponding starting point devices and corresponding end point devices are obtained according to the starting point pin information and the end point pin information respectively;
each pincair is added to the set of constraints named with the corresponding origin and destination devices, respectively.
5. The method for rapidly building equal length constraints on pinpair according to claim 4, wherein:
the name of each restriction group includes a prefix, a starting device, and an ending device.
6. The method for rapidly building equal length constraints on pinpair according to claim 1, wherein the method further comprises:
and guiding all pinpair of the same constraint group to carry out equal-length wiring.
7. The method for rapidly building equal-length Pinpair constraints according to claim 1, wherein the method comprises the following steps:
the pin information in the starting list group of a network is one or more.
8. The utility model provides a device of isometric restraint of quick establishment pinpair which characterized in that:
the apparatus uses the method of any of claims 1-7 to quickly establish an isometric constraint of a pinpair.
9. An electronic device comprising a memory and a processor, the memory storing a computer program operable on the processor, wherein the processor when executing the program implements the steps in the method for quickly establishing an isometric constraint of a pinpair as claimed in any one of claims 1 to 7.
10. A computer-readable storage medium, having stored thereon a computer program, wherein the computer program, when being executed by a processor, implements the steps of the method for quickly establishing an isometric constraint of a pincapir according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011078170.3A CN112183016B (en) | 2020-10-10 | 2020-10-10 | Method, device, equipment and storage medium for quickly establishing pinpair equal-length constraint |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011078170.3A CN112183016B (en) | 2020-10-10 | 2020-10-10 | Method, device, equipment and storage medium for quickly establishing pinpair equal-length constraint |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112183016A true CN112183016A (en) | 2021-01-05 |
| CN112183016B CN112183016B (en) | 2024-05-31 |
Family
ID=73948023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011078170.3A Active CN112183016B (en) | 2020-10-10 | 2020-10-10 | Method, device, equipment and storage medium for quickly establishing pinpair equal-length constraint |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112183016B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62168269A (en) * | 1986-01-20 | 1987-07-24 | Nec Corp | Wiring processing system |
| JPH11224902A (en) * | 1998-02-06 | 1999-08-17 | Sharp Corp | Method and device for net classification and computer-readable memory with classification program stored therein |
| US20060259891A1 (en) * | 2005-05-10 | 2006-11-16 | Wei-Fan Ting | System and method of generating an auto-wiring script |
| US20100115487A1 (en) * | 2008-11-03 | 2010-05-06 | Cadence Design Systems, Inc. | METHOD AND SYSTEM FOR SCHEMATIC-VISUALIZATION DRIVEN TOPOLOGICALLY-EQUIVALENT LAYOUT DESIGN IN RFSiP |
| CN102567553A (en) * | 2010-12-23 | 2012-07-11 | 研华股份有限公司 | Design guiding system and method for circuit board layout rule |
| CN106294905A (en) * | 2015-06-01 | 2017-01-04 | 鸿富锦精密电子(郑州)有限公司 | Printed circuit board wiring system and method |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
-
2020
- 2020-10-10 CN CN202011078170.3A patent/CN112183016B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62168269A (en) * | 1986-01-20 | 1987-07-24 | Nec Corp | Wiring processing system |
| JPH11224902A (en) * | 1998-02-06 | 1999-08-17 | Sharp Corp | Method and device for net classification and computer-readable memory with classification program stored therein |
| US20060259891A1 (en) * | 2005-05-10 | 2006-11-16 | Wei-Fan Ting | System and method of generating an auto-wiring script |
| US20100115487A1 (en) * | 2008-11-03 | 2010-05-06 | Cadence Design Systems, Inc. | METHOD AND SYSTEM FOR SCHEMATIC-VISUALIZATION DRIVEN TOPOLOGICALLY-EQUIVALENT LAYOUT DESIGN IN RFSiP |
| CN102567553A (en) * | 2010-12-23 | 2012-07-11 | 研华股份有限公司 | Design guiding system and method for circuit board layout rule |
| CN106294905A (en) * | 2015-06-01 | 2017-01-04 | 鸿富锦精密电子(郑州)有限公司 | Printed circuit board wiring system and method |
| CN109815570A (en) * | 2019-01-15 | 2019-05-28 | 郑州云海信息技术有限公司 | A method of it checks and whether there is cabling between differential signal via hole |
Non-Patent Citations (2)
| Title |
|---|
| 张艺凡;张艺夕;李琪;: "利用Allegro实现嵌入式系统高速电路设计", 微计算机信息, no. 11, pages 101 - 104 * |
| 熊丽萍;: "基于Cadence Allegro的智能多媒体路由器的PCB设计", 数字技术与应用, no. 02, pages 103 - 105 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112183016B (en) | 2024-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106104698B (en) | Memory physical layer interface logic for generating Dynamic Random Access Memory (DRAM) commands with programmable delay | |
| CN110632499B (en) | Test vector generation method based on test object and storage medium | |
| JPS6063644A (en) | Method and apparatus for modeling operation of digital device | |
| CN103970634B (en) | A kind of back-to-back loopback verification method of large-scale interconnection die based on addition detection logic | |
| WO2019134113A1 (en) | Automated test method and system | |
| CN114861578A (en) | Method, device, equipment and storage medium for repairing hold time violation | |
| CN113687994B (en) | Memory programming time system for multi-station concurrent test and programming method thereof | |
| CN112183016A (en) | Method, device, equipment and storage medium for quickly establishing equal-length constraints of pinpair | |
| CN110532654B (en) | Method and device for determining parameters on PCB of printed circuit board | |
| CN117076337B (en) | Data transmission method and device, electronic equipment and readable storage medium | |
| CN116663490A (en) | Verification method, platform, device and medium of asynchronous memory chip | |
| CN117370088A (en) | Performance test method and system for artificial intelligent accelerator card of domestic heterogeneous platform | |
| CN110688815A (en) | Memory interface circuit hybrid modeling simulation method based on memory access code pattern | |
| US8873421B2 (en) | Integrated test packet generation and diagnostics | |
| WO2022178793A1 (en) | Delay compensation method and related device | |
| CN115587057A (en) | Isometric design method and system for high-speed signals in server system | |
| CN102385547B (en) | Method and system for verifying timing sequence calibration function of dynamic random access memory (DRAM) controller | |
| Gavrilov et al. | Method of mathematical description for digital system blocks logical models | |
| CN115758963A (en) | Device, method and system for processing printing information in chip EDA simulation | |
| US9087036B1 (en) | Methods and apparatuses for time annotated transaction level modeling | |
| Dhar et al. | Coverage driven verification of I2C protocol using System Verilog | |
| CN114444423B (en) | Data processing method and system based on verification platform and electronic equipment | |
| CN113407408B (en) | Data transmission rule verification method, device, equipment and storage medium | |
| CN103605622B (en) | A kind of method and apparatus transmitting data | |
| CN116909935B (en) | Chip joint simulation method, device and medium based on single processing module interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Applicant after: Suzhou Shengke Communication Co.,Ltd. Address before: Xinghan Street Industrial Park of Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Applicant before: CENTEC NETWORKS (SUZHOU) Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |