CN112187233B - Reset device, method, clock system and electronic equipment - Google Patents
Reset device, method, clock system and electronic equipment Download PDFInfo
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Abstract
The application discloses a resetting device, a resetting method, a clock system and electronic equipment, and relates to the field of clock design, wherein the resetting device comprises: the output end of the clock generation circuit is connected with the clock signal input end, and the clock generation circuit is used for: when the system clock circuit is detected to not output a first clock signal, acquiring an asynchronous reset signal, wherein the asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit, and the first clock signal is used for executing reset operation on the synchronous reset circuit; and generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for executing a reset operation on the synchronous reset circuit. Thus, when the system does not output the first clock signal to reset the synchronous reset circuit, the clock generation circuit can generate a second clock signal for executing the reset operation on the synchronous reset circuit according to the asynchronous reset signal, so that the synchronous reset circuit can not reset when the synchronous reset circuit does not receive the first clock signal.
Description
Technical Field
The present application relates to the field of clock design, and more particularly, to a reset device, a reset method, a clock system, and an electronic device.
Background
Current systems on chip or other large scale integrated circuits may include processors, buses, and other electronic components, and because different electronic components may use different timing circuits, there may be both asynchronous reset timing circuits and synchronous reset timing circuits in the system on chip or other large scale integrated circuits, which may place new demands on the design of the system on chip.
Disclosure of Invention
The application provides a resetting device, a resetting method, a clock system and electronic equipment, so as to overcome the defects.
In a first aspect, an embodiment of the present application provides a reset device applied to a clock system, where the clock system includes an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input end of the synchronous reset circuit, the system clock circuit is configured to input a first clock signal to the clock signal input end, and the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, and the reset device includes: the output end of the clock generation circuit is connected with the clock signal input end, and the clock generation circuit is used for: when the system clock circuit is detected not to output a first clock signal, an asynchronous reset signal is obtained, and the asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit; and generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for triggering the synchronous reset circuit to execute reset operation.
In a second aspect, an embodiment of the present application further provides a clock system, including: the system clock circuit is connected with a clock signal input end of the synchronous reset circuit, the system clock circuit is used for inputting a first clock signal to the clock signal input end, the first clock signal is used for triggering the synchronous reset circuit to execute reset operation, and an output end of the clock generating circuit is connected with the clock signal input end.
In a third aspect, an embodiment of the present application further provides an electronic device, including a device body and the clock system described above, where the clock system is disposed in the device body.
In a fourth aspect, an embodiment of the present application further provides a reset method, applied to a clock system, where the clock system includes an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, where the system clock circuit is connected to a clock signal input end of the synchronous reset circuit, and the system clock circuit is configured to input a first clock signal to the clock signal input end, and the first clock signal is configured to trigger the synchronous reset circuit to perform a reset operation, where the method includes: when the system clock circuit is detected not to output a first clock signal, an asynchronous reset signal is obtained, and the asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit; generating a second clock signal according to the asynchronous reset signal; and inputting the second clock signal to the clock signal input end, and indicating the synchronous reset time sequence circuit to execute reset operation according to the second clock signal.
The application provides a reset device, a method, a clock system and an electronic device, which are applied to the clock system, wherein the clock system comprises an asynchronous reset time sequence circuit, a synchronous reset time sequence circuit and a system clock circuit, the system clock circuit is connected with a clock signal input end of the synchronous reset circuit, and the reset device comprises: a clock generation circuit. The system clock circuit can output a first clock signal to a clock signal input end of the synchronous reset circuit, the synchronous reset circuit executes reset operation when the clock signal input end receives the first clock signal, the clock generation circuit cannot reset according to the first clock when detecting that the system clock circuit does not output the first clock signal, and then the clock generation circuit generates a second clock signal according to the asynchronous reset signal when acquiring the asynchronous reset signal, and the second clock signal is input to the clock signal input end. The asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit, and the synchronous reset circuit cannot execute reset operation when the synchronous reset circuit does not receive the first clock signal, so that when the synchronous reset circuit is reset by the synchronous reset circuit without outputting the first clock signal, the clock generation circuit can generate a second clock signal for executing reset operation on the synchronous reset circuit according to the asynchronous reset signal, and the problem that when the synchronous reset circuit does not receive the first clock signal, if the asynchronous reset circuit is reset, the synchronous reset circuit is not reset, the output of the whole system is unstable is caused, and the disorder of the system is avoided.
Additional features and advantages of embodiments of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of embodiments of the application. The objectives and other advantages of embodiments of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a schematic diagram of an asynchronous reset circuit provided by an embodiment of the present application;
FIG. 2 is a schematic diagram of a synchronous reset circuit according to an embodiment of the present application;
FIG. 3 shows a timing diagram corresponding to FIG. 2;
FIG. 4 is a schematic circuit diagram of a reset device according to an embodiment of the present application;
FIG. 5 shows a timing diagram corresponding to FIG. 4;
FIG. 6 is a schematic circuit diagram of a reset device according to another embodiment of the present application;
FIG. 7 is a schematic circuit diagram of a reset device according to another embodiment of the present application;
FIG. 8 is a schematic circuit diagram of a reset device according to another embodiment of the present application;
FIG. 9 is a schematic circuit diagram of a reset device according to still another embodiment of the present application;
FIG. 10 shows a timing diagram corresponding to FIG. 9;
FIG. 11 is a flow chart illustrating a method of resetting according to an embodiment of the present application;
FIG. 12 shows a block diagram of a clock system provided by an embodiment of the application;
Fig. 13 is a schematic structural diagram of an electronic device according to an embodiment of the present application;
Fig. 14 shows a storage unit for storing or carrying program codes for implementing the method according to the embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
In a digital integrated circuit chip, a reset circuit is an indispensable part to ensure the normal operation of the chip. With the increasing chip scale, the structure of the reset circuit and the access mode of the reset circuit and other circuits are more and more complex. Particularly in very large scale integrated circuit chips, there are typically multiple clock domains, each of which has a respective reset signal. For example, in a complex System On Chip (SOC) design, it is often necessary to integrate multiple circuit designs, where the multiple circuits may include modules such as a CPU, bus, and accelerator. However, due to different circuit design rules, asynchronous reset and synchronous reset timing circuits may exist in the SOC at the same time, which puts new demands on the high-level reset logic design of the SOC.
The asynchronous reset time sequence circuit refers to a circuit which uses a clock and resets asynchronously. In particular, the timing circuit may be a register, and the asynchronous reset is implemented using a register with an asynchronous reset port, as shown in fig. 1, which resets the output at the instant the reset signal is detected to be active, the operation not being directly tied to the clock signal CLK input.
The synchronous reset timing circuit is a circuit that uses a clock and resets synchronously. In particular, the timing circuit may be a register, the register in the synchronous reset circuit design not having an asynchronous reset port, the data port selector being used to reset the type of register, the reset value being input to the data port of the register when the reset signal is active. As shown in fig. 2, the register J1 changes the output value of the register to the input value of the register at a time before the clock signal CLK is valid, and thus the synchronous reset timing circuit shown in fig. 2 needs to be equal to the reset value, for example, the reset value may be 0 at a time before the clock signal CLK is valid. In the embodiment of the present application, when the reset signal is valid, the output of the selector M1 is the input of the S1 terminal, and when the reset signal is not valid, the output of the selector M1 is the input of the S2 terminal. As an embodiment, the input signal may be a signal of a normally high level, i.e. the logic value of the input signal is normally 1.
Therefore, the synchronous reset timing circuit shown in fig. 2 needs to be active at a time before the clock signal CLK is active. It is assumed that the clock signal CLK is active to mean that the clock signal changes from low to high, i.e. a rising edge is triggered, and that the reset signal is active to mean that the reset signal is low, so that at the moment before the rising edge of the clock signal CLK, the reset signal should be low, so that the output of the selector M1, i.e. the input of the register J1, is low, i.e. D n =0, and further that when the rising edge of the clock signal CLK arrives, Q n+1＝Dn =0, where n denotes the moment. Therefore, the synchronous reset timing circuit requires that the reset signal be synchronous with the input clock.
However, the inventors found in the study that since the asynchronous reset timing circuit does not require the clock signal CLK, there is a possibility that the system does not generate the clock signal CLK at the time of resetting the asynchronous reset timing circuit, thereby causing the asynchronous reset timing circuit to be reset and the synchronous reset timing circuit to not be reset. As shown in fig. 3, the gate clock in fig. 3 is the clock signal CLK in fig. 2, wherein the system clock signal, the enable signal, and the gate enable signal are signals for generating the clock signal CLK. Specifically, the system clock signal is a basic clock signal provided by a system (such as a system on chip) for each chip in the system, and each chip can receive the system clock signal at an appropriate moment in a control mode of an enabling signal and a logic gate on the basis of the system clock signal according to own demand of clocks, and can also generate a new clock signal in a frequency multiplication, frequency division and latching mode.
The enable signal is used to enable the clock signal CLK in fig. 2, and for example, the enable signal may be used as an instruction for a processor such as a CPU to notify a system to input a clock to a register, the gate enable signal is used to go high when both the enable signal and the system clock signal are high, and the system clock signal is used as the clock signal CLK of the register when the gate enable signal is high.
As can be seen from fig. 3, the reset signal is valid, that is, the time periods of the low level are the 2 nd and 3 rd clocks of the system clock signal and the 7 th and 8 th clocks of the system clock signal, respectively, and it should be noted that one clock of the system clock signal refers to the time elapsed between the adjacent high level and low level, that is, the period of one clock signal, and the system clock signal is a clock signal with multiple periods.
At the time of the 7 th and 8 th clocks of the system clock signal, at the time of the rising edge between the 7 th to 8 th clocks, the output value of the output signal is equal to the 7 th clock, the input D of the register is at a low level, i.e., logic 0, so that at the time of the rising edge between the 7 th to 8 th clocks, the output of the register becomes 0, i.e., is reset. In the 2 nd and 3 rd clocks, the gate clock is not enabled, and is in a normally low state, and the rising edge is not triggered, so that the synchronous reset timing circuit is not reset, and the asynchronous reset timing circuit is reset, which may cause instability of the system. Specifically, assume that the circuits of the CPU in the SOC use synchronous reset, and the bus and the peripheral use asynchronous reset. During system power up, the CPU cannot be reset if the reset signal occurs before the clock is enabled. At this time, the internal register of the CPU is in an unstable state, and the unstable state is transmitted to the peripheral equipment along with the data and control buses connected with the internal register. After the system clock is started, the peripheral samples the unstable state signals from the CPU bus, and further transmits the unstable states, so that more registers in the SOC system are counted into the unstable states, and the normal operation of the whole system is affected.
Therefore, in order to overcome the above-mentioned drawbacks, the embodiment of the present application provides a reset device, which can be reset when the clock signal CLK of the synchronous reset timing circuit is not enabled, and can effectively avoid the situation that the asynchronous reset timing circuit completes the reset and the synchronous reset timing circuit cannot effectively reset in the SOC design where the asynchronous reset and the synchronous reset circuits coexist.
Specifically, referring to fig. 4, fig. 4 shows a reset device. The reset device is applied to a clock system, which may be the SOC described above, or may be other circuitry using clock signals, and the clock system includes an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, where the asynchronous reset timing circuit and the system clock circuit are not shown in the figure, and the register J1 and the selector M1 form the synchronous reset timing circuit. Specifically, the resetting device includes: a clock generation circuit 410.
As an embodiment, the system clock circuit is connected to the clock signal input terminal of the synchronous reset circuit (i.e. the clock terminal C of the register J1), and is configured to provide the synchronous reset circuit with a first clock signal, where the first clock signal is a clock signal provided by the system for triggering the synchronous reset circuit to perform a reset operation, i.e. the first clock signal is used as a trigger signal for the synchronous reset circuit to perform a reset operation. For example, the first clock signal may be the gate clock described above. The description of the asynchronous reset timing circuit and the synchronous reset timing circuit may refer to the foregoing, and will not be repeated here.
An output of the clock generation circuit 410 is connected to the clock signal input. Specifically, the output terminal of the clock generating circuit 410 is connected to the clock terminal C of the register J1, the control terminal CN of the selector M1 is configured to receive an asynchronous reset signal, when the asynchronous reset signal is at a high level, the logic value of the output terminal of the selector M1 is the logic value of the input signal at the S2 terminal, and when the asynchronous reset signal is at a low level, the logic value of the output terminal of the selector M1 is the logic value of the input signal at the S1 terminal. As can be seen from fig. 4, the logic value of the input signal at the S1 terminal is 0, so that when the reset signal is at the low level, the logic value of the input terminal D of the register J1 is 0, and thus, when the next rising edge of the clock terminal C of the register J1 arrives, the output value of the register J1 is equal to the logic value of the input terminal D when the reset signal is at the low level, that is, the output value of the register J1 is equal to 0, that is, is reset.
The clock generation circuit 410 is configured to obtain an asynchronous reset signal when it is detected that the system clock circuit does not output the first clock signal, where the asynchronous reset signal is used to perform a reset operation on the asynchronous reset timing circuit. For example, the asynchronous reset signal may be the reset signal in fig. 3 described above, specifically, when the asynchronous reset signal is at a low level, the asynchronous reset timing circuit is reset. Then, the clock generation circuit 410 generates a second clock signal according to the asynchronous reset signal; and the second clock signal is input to the clock signal input end and is used for triggering the synchronous reset circuit to execute reset operation, namely, the second clock signal is used as a trigger signal for the synchronous reset circuit to execute reset operation.
As an embodiment, the second clock signal generated by the clock generation circuit 410 can also generate an active level state, and the active level state is the same as the active level state that can be generated by the first clock signal provided by the system. For example, when the first clock signal is taken as the gate clock, the active level state of the first clock signal is a state in which the low level is changed to the high level, that is, a rising edge, and the second clock signal generated by the clock generation circuit 410 can also generate the rising edge.
As an embodiment, the clock generating circuit 410 may generate the second clock signal according to the asynchronous reset signal, where the clock generating circuit 410 is capable of generating the clock signal, specifically, the clock generating circuit 410 is a clock generator capable of receiving the system clock, and the second clock signal is generated by performing a preset process on the system clock, where the second clock signal may be the same as the first clock signal, that is, the period and the pulse width coincide, and the preset process may not perform any process, or may also be an operation manner such as frequency multiplication, frequency division, phase locking, or a logic operation, where the logic operation includes operations such as logical and, logical negation, for example, inverting the signal so that the high level of the signal becomes the low level, and the low level becomes the high level. The clock generation circuit 410 can generate the second clock signal to monitor the level change of the asynchronous reset signal when the level of the asynchronous reset signal becomes the designated level.
As an embodiment, the clock generation circuit 410 may generate the second clock signal according to the asynchronous reset signal, where the clock generation circuit 410 is capable of monitoring a level change of the asynchronous reset signal, and performing a preset process on the asynchronous reset signal to generate the second clock signal when the level of the asynchronous reset signal becomes a specified level. Specifically, an asynchronous reset signal may be directly used as the second clock signal, or the asynchronous reset signal may be processed by a logic element such as a flip-flop to obtain the second clock signal, which will be specifically described in the subsequent embodiments.
Therefore, when the system does not output the first clock signal to reset the synchronous reset circuit, the clock generation circuit can generate a second clock signal for triggering the synchronous reset circuit to execute the reset operation according to the asynchronous reset signal, so that the problem that when the synchronous reset circuit does not receive the first clock signal, if the asynchronous reset circuit is reset, the synchronous reset circuit is not reset, the output of the whole system is unstable is avoided, and the system disorder is avoided. In particular, referring to fig. 5, fig. 5 shows a timing diagram of a clock system. As can be seen from comparing fig. 5 with fig. 3, in a period in which the system clock circuit does not supply the first clock signal to the synchronous reset timing circuit, that is, a period in which the gate clock is not enabled for a state in which the gate clock is not received at the clock terminal C of the register J1, fig. 3, in which the output signal is not reset, that is, for a high level, and in fig. 5, in which the clock terminal C of the register J1 is able to change the output signal to the logic value of D of the low level stage of the reset signal in response to a transition in which the reset signal changes from the low level to the high level.
As can be seen from the above-described fig. 3 and 5, the asynchronous reset signal is a signal alternately changed between a first level and a second level, and the synchronous reset timing circuit is configured to perform a reset operation when a signal inputted to the clock signal input terminal is a designated level or a level change occurs, wherein the first level may be a low level or a high level, the second level is a high level if the first level is a low level, and the second level is a low level if the first level is a high level. As an embodiment, the specified level may be a low level or a high level, where the level change may occur from a low level to a high level (i.e., a rising edge) or from a high level to a low level (i.e., a falling edge).
Therefore, as an embodiment, the clock generation circuit 410 may directly use the asynchronous reset signal as the second clock signal, as shown in fig. 4, the clock generation circuit 410 may input the asynchronous reset signal to the clock terminal C of the register J1 when the asynchronous reset signal is acquired, so as the asynchronous reset signal is alternately changed between the first level and the second level, the signal of the clock terminal C of the register J1 is also alternately changed between the first level and the second level, so that the designated level can be changed or a level change occurs, and the register J1 is reset.
In addition, if the asynchronous reset signal is a pulse signal, and the pulse width is relatively narrow, the time is too short, so that the synchronous reset timing circuit cannot respond to the asynchronous reset signal, and the synchronous reset timing circuit cannot accurately assign an output value, and further, the output result is in an unstable state. Therefore, to avoid this problem, the clock generation circuit is also configured to: generating a signal that remains at a first level for a first length of time upon detecting that the asynchronous reset signal changes from a second level to a first level; when the asynchronous reset signal is detected to be changed from the first level to the second level, a signal which is kept at the second level for a second time period is generated, and the signal which is alternately changed between the first level and the second level and is generated by the clock generating circuit is used as a second clock signal.
As an embodiment, the first time length and the second time length may be set according to practical use, and in some embodiments, the signal output by the clock generating circuit is also a periodic signal that alternates between the first level and the second level, and the time length of one period is the sum of the time length T1 of the output signal at the first level and the time length T2 of the output signal at the second level, that is, the period t=t1+t2. As an implementation manner, the t1 and the t2 may be different or different, and in this embodiment of the present application, the period of the signal output by the clock generating circuit is the same as the period of the first clock signal. As another embodiment, in the case that the pulse width of the asynchronous reset signal is smaller than the specified width, the first time length is the same as the time length that the asynchronous reset signal is at a first level, the second time length is the same as the time length that the asynchronous reset signal is at a second level, that is, the period of the signal output by the clock generation circuit is the same as the period of the asynchronous reset signal, if the pulse width of the asynchronous reset signal is not smaller than the specified width, the pulse width of the signal output by the clock generation circuit can be made larger than the pulse width of the asynchronous reset signal by reasonably setting the first time length and the second time length, so that when the signal output by the clock generation circuit is taken as the second clock signal, the second clock signal can meet the requirement of the synchronous reset time sequence circuit, and the phenomenon that the pulse width of the second clock signal is too narrow to cause the synchronous reset time sequence circuit to output an unstable state can be avoided.
As an implementation manner, referring to fig. 6, fig. 6 shows that another embodiment of the present application provides a reset device, as shown in fig. 6, the clock generating circuit 410 further includes a flip-flop 411 and a valuation circuit 412, where a clock end of the flip-flop 411 is used to receive the asynchronous reset signal, an output end of the flip-flop 411 is connected to the clock signal input end, and the valuation circuit 412 is connected to the input end of the flip-flop 411, where an output end of the flip-flop 411 is used as an output end of the clock generating circuit 410.
As shown in fig. 6, the synchronous reset timing circuit may be composed of a register J1 and a selector M1, where the clock signal input terminal is a clock terminal C1 of the register J1, the evaluation circuit 412 and the flip-flop 411 can both receive an asynchronous reset signal, the control terminal CN of the selector M1 also receives an asynchronous reset signal, and the output terminal of the flip-flop 411 is connected to the clock terminal C of the register J1.
The assignment circuit 412 is configured to output a first signal when the asynchronous reset signal is at a second level, where the first signal is a signal at the first level; the flip-flop 411 is configured to output a signal equal to a first signal when the asynchronous reset signal received by the clock terminal changes from a second level to a first level, and output a signal equal to a signal after the first signal is inverted when the asynchronous reset signal received by the clock terminal changes from the first level to the second level. In one embodiment, the first level is a low level and the second level is a high level.
Specifically, as shown in fig. 7, the assignment circuit 412 includes a first selector M2 and a flip-flop L1, where the first selector M2 includes a first selection input terminal S22, a second selection input terminal S21, a first control terminal CN2, and a first selection output terminal P2, a signal input to the first selection input terminal S22 is a first level, that is, a logic value of the input S22 in fig. 7 is 0, and an output terminal of the flip-flop 411 is connected to the second selection input terminal S21 through the flip-flop, and the first control terminal CN2 is configured to receive the asynchronous reset signal. In the embodiment of the present application, the flip-flop 411 is the register J2 in fig. 7, and the register J2 may be a dual-edge flip-flop, that is, performing an assignment operation when the signals at the clock end are the rising edge and the falling edge.
The first selector M2 is configured to control the output signal of the first selection output terminal P2 to be the signal input to the first selection input terminal S22 when the asynchronous reset signal received by the first control terminal CN2 is at a high level, and control the output signal of the first selection output terminal P2 to be the signal input to the second selection input terminal S21 when the asynchronous reset signal received by the first control terminal CN2 is at a low level. As shown in fig. 7, the first selector M2 and the inverter L1 and the register J2 constitute a double-edge flip-flop, that is, the register J2 performs an assignment operation when the signal at the clock terminal C1 goes on a rising edge (low level changes to high level) or when the signal at the clock terminal C1 goes on a falling edge (high level changes to low level), that is, the output value is equal to the value at the D1 terminal at the time immediately before the rising edge or the falling edge.
Specifically, the logical value of each port varies as follows:
when the asynchronous reset signal is 1, CN2 is 1, P2 is equal to the value of S22, i.e., P2 is equal to 0, then the value of D1 end of the register J2 is also 0, and since the signal of clock end C of the register J1 does not have a rising edge, the value of the output end Q1 of the register J2 keeps the previous state value unchanged, for example, the previous state logic value is 1, and the output end Q1 of the register J2 is also 1.
When the asynchronous reset signal is 0, that is, the signal at the clock end C1 triggers the falling edge, CN2 is 0, P2 is equal to the value of S21, that is, P2 is equal to the inverted logical value of Q1, that is, P2 is equal to 0, then the logical value at the D1 end of the input register J2 is 0, the output value Q1 is equal to the previous time of the falling edge, that is, when the previous asynchronous reset signal is 1, the value at the D1 end, that is, the output value Q1 is 0, and at the current time, the value at the S21 end is the inverted value from Q1 to Q1, that is, the D1 at the current time is equal to 1.
When the asynchronous reset signal is again 1, i.e. the signal at the clock terminal C1 triggers a rising edge, P2 is equal to the value of S22, i.e. P2 is equal to 0, and the output value Q1 is equal to the previous time of the rising edge, i.e. the previous time the asynchronous reset signal was 0, the value at the terminal D1, i.e. the output value Q1 is 1, and D1 at the current time is 0.
Accordingly, the output Q1 is pulled low at the falling edge of the asynchronous reset signal is detected, and Q1 is pulled high at the rising edge of the asynchronous reset signal is detected, and thus this process produces a rising edge at Q1, the rising edge of Q1 serving as the reset clock signal for register J1.
In one embodiment, to facilitate the synchronous reset timing circuit to reset using the first clock signal when the system clock circuit outputs the first clock signal, and to reset using the second clock signal when the system clock circuit does not output the first clock signal, the reset device further includes a selection switch. As shown in fig. 8, assuming that the synchronous reset timing circuit is composed of the above-described register J1 and selector M1, both the system clock circuit 310 and the clock generation circuit 410 are connected to the clock terminal C of the register J1 through the selection switch 420. The selection switch 420 is used for: when it is detected that the system clock circuit 310 does not output the first clock signal, the system clock circuit 310 is turned off from the clock signal input terminal C, and the clock generation circuit 410 is turned on from the clock signal input terminal C; upon detecting that the system clock circuit 310 outputs a first clock signal, the system clock circuit 310 is turned on with the clock signal input terminal C, and the clock generation circuit 410 is turned off with the clock signal input terminal C.
As an embodiment, the selection switch may include two input terminals and an output terminal, where the two input terminals are respectively connected to the clock generating circuit 410 and the system clock circuit 310, the output terminal is connected to the clock terminal C of the register J1, and the control terminal is configured to detect whether the system clock circuit outputs the first clock signal according to the clock enable signal, where the clock enable signal may be the aforementioned enable signal or the gate enable signal, and when the clock enable signal is at an active level (e.g., a high level), the system clock circuit outputs the first clock signal, and when the clock enable signal is at a non-active level, the system clock circuit does not output the first clock signal. The control terminal can receive the clock enable signal and control connection between the input terminal and the output terminal of the clock generation circuit 410 to be turned on and the other input terminal and the output terminal to be turned off when the clock enable signal is at the inactive level. When the clock enable signal is active, the control is connected to the input and output of the system clock circuit 310, and the other input and output are turned off.
In the embodiment of the application, the selector can be an electronic device such as a triode, a transistor, a silicon controlled rectifier and the like, which is provided with a control end and two connecting ends.
Specifically, referring to fig. 9, the selection switch 420 may be the selector M3 in fig. 9, the selection switch 420 includes a second selector M3, the second selector M3 includes a third selection input terminal S31, a fourth selection input terminal S32, a second control terminal CN3, and a second selection output terminal P3, and the clock generating circuit is connected to the third selection input terminal S31, that is, the output terminal Q1 of the register J2 is connected to the third selection input terminal S31. The system clock circuit is connected to the fourth selection input terminal S32, the second selection output terminal P3 is connected to the clock signal input terminal, that is, the second selection output terminal P3 is connected to the clock terminal C of the register J1, the second control terminal CN3 is configured to receive the clock enable signal EN, and the system clock circuit 310 is configured to output the first clock signal when the clock enable signal EN is at an active level, where the active level may be a high level. The specific embodiment of the clock enable signal EN can refer to the aforementioned enable signal, and will not be described herein.
The selector M3 is for: when the clock enable signal EN received by the second control terminal CN3 is at an active level, controlling the output signal of the second selection output terminal P3 to be the first clock signal input to the fourth selection input terminal S32 by the system clock circuit 310; when the clock enable signal EN received by the second control terminal CN3 is not at an active level, the output signal of the second selection output terminal P3 is controlled to be the second clock signal input to the third selection input terminal S31 by the clock generation circuit.
The system clock circuit 310 includes a latch J3 and a logic and gate L2, where the latch J3 may be a register, and the latch J3 is active when the clock terminal E is low unlike the register J1 described above. In the embodiment of the present application, the register and the flip-flop may be D flip-flops.
The clock end E of the latch J3 is used for receiving the signal after the inversion of the system clock CLK, the input end D3 of the latch J3 is used for receiving the clock enable signal EN, the output end Q3 of the latch J3 is connected with one logic input end of the logic and gate L2, the other logic input end of the logic and gate L2 receives the system clock CLK, and the output end of the logic and gate L2 is connected with the fourth selection input end S32.
Specifically, the principle of fig. 9 is described in terms of logical values:
When the asynchronous reset signal is 0, the clock terminal C1 of the register J2 is 0, Q1 holds D1 in the previous state, that is, 0, q1=0, Q1 is 1 after inversion, and the output of the selector M2 is equal to the value of Q1 after inversion at this time, so D1 becomes 1.
At this time, the clock enable signal EN is 0, the system clock CLK is 1, the output terminal Q3 of the latch J3 holds the logic value of the clock enable signal EN of the previous state, that is, the output terminal Q3 of the latch J3 is equal to 0, then the output of the and gate is 0, the output of the selector M3 is equal to Q1, that is, the output of the selector M3 is 0, the output of the selector M1 is 0, and the output Q of the register J1 is also 0.
If the asynchronous reset signal becomes 1, the clock terminal C1 of the register J2 is 1, Q1 is equal to D1, i.e., Q1 is equal to 1, Q1 is 0 after the other, the output of the M selector M2 is equal to the value of S22 at this time, so D1 becomes 0, then, at this time, the clock enable signal EN is 0, the system clock CLK is 1, the output terminal Q3 of the latch J3 maintains the EN of the previous state, i.e., Q3 is equal to 0, then, the output of the and gate is 0, the output of the selector M3 is equal to Q1 at this time, the clock signal of the register J1 is high, and the output Q of the register J1 is equal to D at the previous time, i.e., equal to 1.
When the clock enable signal EN is at an active level, wherein the active level of the clock enable signal EN means that the clock enable signal EN is at a high level, i.e. the logic value is 1, and when the system clock CLK is at a low level, the Gate enable signal Gate EN output from the latch J3 is also at a high level, and when the Gate EN is also at a high level, the output of the and Gate is equal to the system clock, i.e. the Gate clock GATEED CLK is equal to the system clock CLK, and then the selector M3 inputs the Gate clock GATEED CLK as the first clock signal to the clock terminal C of the register J1.
As shown in fig. 10, the timing chart corresponding to fig. 9 shows that the gate clock is continuously in a low level state when the enable signal is in a low level state, and the register J1 cannot be reset as the reset clock of the register J1. In the case where the first clock signal, i.e., the gate clock, is not enabled, the output Q1 of the register J2 is also changed from low to high at the rising edge of the reset signal from low to high, i.e., the rising edge is triggered, and the input D of the register J1 is low at the time before the rising edge, and the logic value of the output signal of the register J1 is changed to 0, i.e., reset, at the rising edge of the output Q1. When the enable signal is at a high level, even in a period in which the enable signal is active, the logic value of the output signal of the register J1 becomes 0, i.e., is reset, at the time of the rising edge triggered by the gate clock. That is, in the period of the 7 th clock of the system clock, the asynchronous reset signal is at a low level, and the output of the selector M1 is caused to be 0, that is, the input terminal D of the register J1 is 0, then at the position of the rising edge of the 8 th clock of the system clock, the output signal of the register J1 is equal to the previous time of the rising edge, that is, the value of D in the period of the 7 th clock of the system clock, that is, equal to 0, thereby being reset.
Therefore, when the enable signal is not enabled, the second clock signal is obtained by using the asynchronous reset signal, so that the synchronous reset timing circuit can be reset according to the second clock signal, and as can be seen from the above timing chart, when the asynchronous reset signal is at a low level, the asynchronous reset timing circuit is reset, and at the timing when the asynchronous reset signal is pulled high, the synchronous reset timing circuit is reset, so that the asynchronous reset timing circuit and the synchronous reset timing circuit can be reset successively even when the first clock signal is not enabled.
Referring to fig. 11, a reset method according to an embodiment of the present application is applied to the clock system, as an implementation manner, the method is applied to the reset device, and specifically, the method includes: s1101 to S1103.
S1101: and acquiring an asynchronous reset signal when the system clock circuit is detected to not output the first clock signal.
The asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit, and the first clock signal is used for triggering the synchronous reset circuit to execute reset operation.
As an embodiment, when the system clock circuit does not output the first clock signal, the asynchronous reset signal may be obtained by turning off the system clock circuit and the clock signal input terminal, turning on the clock generating circuit and the clock signal input terminal, and obtaining the asynchronous reset signal when the selection switch detects that the system clock circuit does not output the first clock signal. When the selection switch detects that the system clock circuit outputs a first clock signal, the system clock circuit is conducted with the clock signal input end, and the clock generating circuit is cut off with the clock signal input end.
S1102: and generating a second clock signal according to the asynchronous reset signal.
The second clock signal is used for triggering the synchronous reset circuit to execute reset operation.
As an embodiment, the asynchronous reset signal is a signal that alternates between a first level and a second level, and the synchronous reset timing circuit is configured to perform a reset operation when a signal input to the clock signal input terminal is a specified level or a level change occurs, where the specified level is the first level or the second level, and the second clock signal may be generated according to the asynchronous reset signal by using the asynchronous reset signal as the second clock signal.
As another embodiment, the asynchronous reset signal is a signal alternately changing between a first level and a second level, and the synchronous reset timing circuit is configured to perform a reset operation when a signal inputted to the clock signal input terminal is changed from the first level to the second level. An embodiment of generating the second clock signal according to the asynchronous reset signal may be that, when the asynchronous reset signal is detected to be changed from the second level to the first level, a signal maintained at the first level for a first period of time is generated; when the asynchronous reset signal is detected to be changed from the first level to the second level, a signal of the second level is generated within a second time period, and the signal alternately changed between the first level and the second level is generated by the clock generation circuit as a second clock signal.
In some embodiments, the evaluation circuit outputs a first signal when the asynchronous reset signal is at a second level, the first signal being a signal at the first level; the trigger outputs a signal equal to a first signal when the asynchronous reset signal received by the clock terminal is changed from a second level to a first level, and outputs a signal equal to a signal after the first signal is inverted when the asynchronous reset signal received by the clock terminal is changed from the first level to the second level.
S1103: and the second clock signal is input to the clock signal input end so as to trigger the synchronous reset circuit to execute reset operation.
Referring to fig. 12, a clock system provided in an embodiment of the application is shown, where the clock system 100 may be the SOC described above, or other circuitry using clock signals. As an embodiment, the clock system may be arranged on at least one chip. As shown in fig. 12, the clock system 100 includes an asynchronous reset timing circuit 320, a synchronous reset timing circuit 330, a system clock circuit 310, and a reset device 400, the system clock circuit 310 is connected to a clock signal input terminal of the synchronous reset circuit 330, and a clock generation circuit is connected to the clock signal input terminal.
In particular, the above-mentioned embodiments of the asynchronous reset timing circuit 320, the synchronous reset timing circuit 330, the system clock circuit 310 and the reset device 400 can refer to the above-mentioned embodiments, and are not repeated here.
Fig. 13 is a block diagram illustrating a structure of an electronic device according to an embodiment of the present application. The electronic device 10 may be a smart phone, tablet, electronic book, or other electronic device capable of running applications. The electronic device 10 of the present application may include a device body 11 and a clock system 100, the clock system 100 being disposed within the device body 11. Wherein, the device body 11 includes a housing and a main display screen disposed on the housing. The shell can be made of metal, such as steel and aluminum alloy. In this embodiment, the main display screen generally includes a display panel, and may also include a circuit for performing a touch operation on the display panel in response to the touch operation. In some embodiments, the display panel is simultaneously a touch screen. As one embodiment, the clock system 100 is disposed within a housing. Specifically, the motherboard of the electronic device is located in the housing, and the clock system 100 is disposed on the motherboard of the electronic device.
In addition, the electronic device may also include a processor, a memory, and one or more application programs, wherein the one or more application programs may be stored in the memory and configured to be executed by the one or more processors, the one or more program configured to perform the methods as described in the foregoing method embodiments.
The processor may include one or more processing cores. The processor uses various interfaces and lines to connect various portions of the overall electronic device 100, perform various functions of the electronic device 100, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in memory, and invoking data stored in memory. Alternatively, the processor may be implemented in at least one hardware form of digital signal processing (DIGITA L SIGNA L processing, DSP), field programmable gate array (Fie ld-Programmab LE GATE ARRAY, FPGA), programmable logic array (Programmab le Logic Array, PLA). The processor may integrate one or a combination of several of a central processing unit (Centra l Process ing Un it, CPU), an image processor (Graph ics Process ing Un it, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for being responsible for rendering and drawing of display content; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor and may be implemented solely by a single communication chip.
The Memory may include random access Memory (Random Access Memory, RAM) or Read-only Memory (ROM). The memory may be used to store instructions, programs, code sets, or instruction sets. The memory may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described below, etc. The storage data area may also store data created by the electronic device 100 in use (e.g., phonebook, audiovisual data, chat log data), and the like.
Referring to fig. 14, a block diagram of a computer readable storage medium according to an embodiment of the present application is shown. The computer readable medium 1300 has stored therein program code that can be invoked by a processor to perform the methods described in the method embodiments above.
The computer readable storage medium 1300 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Optionally, computer readable storage medium 1300 includes non-volatile computer readable media (non-trans itory computer-readab le storage med ium). The computer readable storage medium 1300 has storage space for program code 1310 that performs any of the method steps described above. The program code can be read from or written to one or more computer program products. Program code 1310 may be compressed, for example, in a suitable form.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be appreciated by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not drive the essence of the corresponding technical solutions to depart from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A reset device, characterized in that it is applied to a clock system, the clock system includes an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input terminal of the synchronous reset timing circuit, the system clock circuit is used for inputting a first clock signal to the clock signal input terminal, the first clock signal is used for triggering the synchronous reset timing circuit to execute a reset operation, the reset device includes:
The output end of the clock generation circuit is connected with the clock signal input end, and the clock generation circuit is used for:
When the system clock circuit is detected not to output a first clock signal, an asynchronous reset signal is obtained, and the asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit;
generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for triggering the synchronous reset timing circuit to execute reset operation,
The asynchronous reset signal is a signal alternately changing between a first level and a second level, the synchronous reset timing circuit is used for executing a reset operation when a signal input to the clock signal input terminal changes from the first level to the second level, and the clock generating circuit is further used for:
generating a signal that remains at a first level for a first length of time upon detecting that the asynchronous reset signal changes from a second level to a first level;
when the asynchronous reset signal is detected to be changed from the first level to the second level, a signal which is kept at the second level for a second time period is generated, and the signal which is alternately changed between the first level and the second level and is generated by the clock generating circuit is used as a second clock signal.
2. The apparatus of claim 1, wherein the asynchronous reset signal is a signal that alternates between a first level and a second level, the synchronous reset timing circuit is configured to perform a reset operation when a signal input to the clock signal input is at a specified level or a change in level occurs, the specified level being either the first level or the second level, the clock generation circuit is further configured to:
the asynchronous reset signal is taken as the second clock signal.
3. The apparatus of claim 1, wherein the clock generation circuit comprises a flip-flop having a clock terminal for receiving the asynchronous reset signal, an output terminal coupled to the clock signal input terminal, and a evaluation circuit coupled to the input terminal of the flip-flop, wherein the output terminal of the flip-flop is the output terminal of the clock generation circuit;
The assignment circuit is used for outputting a first signal when the asynchronous reset signal is at a second level, wherein the first signal is a signal at a first level;
The trigger is used for outputting a signal equal to a first signal when the asynchronous reset signal received by the clock end is changed from a second level to a first level, and outputting a signal equal to a signal after the first signal is inverted when the asynchronous reset signal received by the clock end is changed from the first level to the second level.
4. The apparatus of claim 3, wherein the evaluation circuit comprises a first selector and an inverter, the first selector comprising a first select input, a second select input, a first control, and a first select output, the signal input to the first select input being at a first level, the output of the flip-flop being coupled to the second select input through the inverter, the first control being for receiving the asynchronous reset signal, the first selector being for:
And when the asynchronous reset signal received by the first control end is at a second level, controlling the output signal of the first selection output end to be a signal input into the first selection input end, and when the asynchronous reset signal received by the first control end is at a first level, controlling the output signal of the first selection output end to be a signal input into the second selection input end.
5. A device according to claim 3, wherein the trigger is a D-trigger.
6. The device of any one of claims 1-5, wherein the reset device further comprises:
The system clock circuit and the clock generation circuit are both connected with the clock signal input end through the selection switch, and the selection switch is used for:
when the system clock circuit is detected not to output a first clock signal, the system clock circuit is cut off from the clock signal input end, and the clock generating circuit is conducted from the clock signal input end;
When the system clock circuit is detected to output a first clock signal, the system clock circuit is conducted with the clock signal input end, and the clock generating circuit is cut off with the clock signal input end.
7. The apparatus of claim 6, wherein the selection switch comprises a second selector comprising a third selection input, a fourth selection input, a second control, and a second selection output, the clock generation circuit coupled to the third selection input, the system clock circuit coupled to the fourth selection input, the second selection output coupled to the clock signal input, the second control to receive a clock enable signal, the system clock circuit to output a first clock signal when the clock enable signal is at an active level, the selector to:
When the clock starting signal received by the second control end is in an effective level, controlling the output signal of the second selection output end to be a first clock signal input by the system clock circuit into the fourth selection input end;
And when the clock starting signal received by the second control end is not in a valid level, controlling the output signal of the second selection output end to be a second clock signal input by the clock generating circuit into the third selection input end.
8. A clock system, comprising: the reset device of any one of the preceding claims 1-7, wherein the system clock circuit is connected to a clock signal input terminal of the synchronous reset timing circuit, the system clock circuit is configured to input a first clock signal to the clock signal input terminal, the first clock signal is configured to trigger the synchronous reset timing circuit to perform a reset operation, and an output terminal of the clock generating circuit is connected to the clock signal input terminal.
9. An electronic device comprising a device body and the clock system of claim 8, the clock system disposed within the device body.
10. A reset method, characterized in that it is applied to a clock system, the clock system includes an asynchronous reset timing circuit, a synchronous reset timing circuit, and a system clock circuit, the system clock circuit is connected to a clock signal input terminal of the synchronous reset timing circuit, the clock signal input terminal is connected to an output terminal of a clock generation circuit, the system clock circuit is configured to input a first clock signal to the clock signal input terminal, and the first clock signal is configured to trigger the synchronous reset timing circuit to perform a reset operation, the method includes:
When the system clock circuit is detected not to output a first clock signal, an asynchronous reset signal is obtained, and the asynchronous reset signal is used for executing reset operation on the asynchronous reset time sequence circuit;
Generating a second clock signal according to the asynchronous reset signal, wherein the second clock signal is used for triggering the synchronous reset time sequence circuit to execute reset operation;
inputting the second clock signal to the clock signal input terminal to trigger the synchronous reset timing circuit to execute a reset operation, wherein,
The asynchronous reset signal is a signal which alternates between a first level and a second level, and the synchronous reset timing circuit is used for executing a reset operation when a signal input to the clock signal input terminal is changed from the first level to the second level;
generating a signal that remains at a first level for a first length of time upon detecting that the asynchronous reset signal changes from a second level to a first level;
when the asynchronous reset signal is detected to be changed from the first level to the second level, a signal which is kept at the second level for a second time period is generated, and the signal which is alternately changed between the first level and the second level and is generated by the clock generating circuit is used as a second clock signal.
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| CN101082939A (en) * | 2006-05-31 | 2007-12-05 | 中国科学院微电子研究所 | Reset circuit design method in system-on-chip design |
| CN100464281C (en) * | 2006-10-13 | 2009-02-25 | 启攀微电子（上海）有限公司 | Method and circuit for processing chip reset |
| CN104348465B (en) * | 2013-07-26 | 2018-08-14 | 华为技术有限公司 | A kind of control method and control circuit |
| CN104426511A (en) * | 2013-08-22 | 2015-03-18 | 京微雅格（北京）科技有限公司 | Technical mapping method and integrated circuit for automatically generating global asynchronous reset signals |
| CN105425926B (en) * | 2015-12-22 | 2018-11-02 | 无锡芯响电子科技有限公司 | The controllable reset circuit of asynchronous reset synchronous release bandwidth |
| CN107452426B (en) * | 2017-07-24 | 2020-04-07 | 中国空间技术研究院 | Detection circuit and detection method for storage element in FPGA chip |
| CN109032498B (en) * | 2018-07-25 | 2021-03-30 | 电子科技大学 | Waveform quantization synchronization method of multi-FPGA multi-channel acquisition system |
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