CN112150971A

CN112150971A - Shift register circuit of active matrix organic light emitting display and display thereof

Info

Publication number: CN112150971A
Application number: CN201910563594.XA
Authority: CN
Inventors: 杨轩
Original assignee: Incoflex Semiconductor Technology Ltd
Current assignee: Incoflex Semiconductor Technology Ltd
Priority date: 2019-06-26
Filing date: 2019-06-26
Publication date: 2020-12-29

Abstract

The invention provides a shift register circuit of an active matrix organic light-emitting display, which comprises a plurality of transistors and a plurality of capacitors; wherein the grid of the first transistor is connected with the first node, the constant high voltage input end and the signal output end; the grid electrode of the second transistor is connected with the second node, the signal output end and the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the second node and the signal input end; the grid electrode of the fourth transistor is connected with the second node, the first clock signal end and the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the constant low voltage input end and the first node; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end. Therefore, the area of layout is effectively saved, and the voltage holding port intermittently writes the holding potential to make the working state of the whole circuit more stable.

Description

Shift register circuit of active matrix organic light emitting display and display thereof

Technical Field

The invention relates to the field of electronic circuits, in particular to a shift register circuit structure and an active matrix organic light-emitting display with the same.

Background

Organic Light Emitting Diodes (OLEDs), which are current type Light Emitting devices, are increasingly used in high performance display fields due to their characteristics of self-luminescence, fast response, wide viewing angle, and being fabricated on flexible substrates. The OLED can be classified into a PMOLED (Passive Matrix Driving OLED) and an AMOLED (Active Matrix Driving OLED) according to a Driving method. The conventional PMOLED generally requires a reduction in driving time of a single pixel as the size of a display device increases, and thus requires an increase in transient current, resulting in a large increase in power consumption. In the AMOLED technology, each OLED scans an input current line by line through a TFT (Thin Film Transistor) switching circuit, and thus the problems can be solved well.

For process or technical reasons, the pixel driving circuit needs to implement the function of threshold voltage compensation through the pixel compensation circuit. In order to achieve a better display effect, the pixel compensation circuit does not want an Organic Light Emitting Diode (OLED) to emit light when the pixel compensation circuit operates in the operations of reset, data writing, compensation, and the like, so a switching TFT is usually used to control a main circuit to be turned off, thereby avoiding abnormal light emission of the OLED. In the prior art, the scheme for controlling the light emission of the OLED generally generates a sequential pulse signal, and then generates a shift light emission control signal by performing a logic operation on the sequential pulse signal, specifically, generates the sequential pulse signal by a trigger, and then generates the shift light emission control signal by a logic circuit. For example, the chinese patent application with publication number CN100514419C discloses a technical solution, which does not consider the problem of loss of the cascaded output threshold voltage, so that the waveform voltage may not be maintained after several stages are cascaded.

Still another prior art solution is to generate a shifted light emitting control signal by generating a sequential pulse signal and controlling the base number and the even number rows respectively by using two cascaded output waveforms with a certain phase difference, such as that disclosed in chinese patent application publication No. CN 102760406A. A disadvantage of this type of solution is that the required clock signal is multiplied, which has a negative effect on stability and reliability. For example, the chinese patent application with publication number CN103886836B discloses a technical solution that can directly generate a shift emission control signal, but at the time of the reset and compensation stages when the output stage TFTs are turned off simultaneously (high resistance state), the output can be maintained only by the parasitic capacitance, and the influence of crosstalk of other signal lines may be caused.

In view of the above, the present inventors have made diligent experiments and studies to overcome the above-mentioned shortcomings in the prior art, and finally have devised a novel shift register circuit of an active matrix organic light emitting display, which uses a shift register circuit of a PMOS transistor to achieve the purposes of high anti-interference capability and high reliability.

Disclosure of Invention

The invention aims to: the shift register circuit of the active matrix organic light-emitting display is provided, so that the area of layout is effectively saved, and a narrow-frame display device is more favorably realized; the holding potential can be written into the capacitor voltage holding port discontinuously in the holding state, the working state of the whole circuit is more stable, and the anti-interference and impact capabilities are stronger, so that the technical problems in the prior art are solved.

To achieve an objective of the present invention, a technical solution provided by the present invention is as follows:

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the signal output end; the grid electrode of the second transistor is connected with the second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the signal input end; the grid of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first clock signal end, and the second pole of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are PMOS thin film transistors.

To achieve another objective of the present invention, the present invention provides a technical solution as follows:

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the signal output end; the grid electrode of the second transistor is connected with the second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the first pole of the sixth transistor, and the second pole of the third transistor is connected with the signal input end; the grid electrode of the fourth transistor is connected with the first electrode of the sixth transistor, the first electrode of the fourth transistor is connected with the first clock signal end, and the second electrode of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the sixth transistor is connected with the constant low-voltage input end, the first pole of the sixth transistor is connected with the grid electrode of the fourth transistor, and the second pole of the sixth transistor is connected with the second node; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor and the fifth transistor are PMOS thin film transistors.

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the second capacitor; the grid electrode of the second transistor is connected with a second node, the first pole of the second transistor is connected with the second capacitor, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the first pole of the sixth transistor, and the second pole of the third transistor is connected with the signal input end; the grid electrode of the fourth transistor is connected with the first electrode of the sixth transistor, the first electrode of the fourth transistor is connected with the first clock signal end, and the second electrode of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the sixth transistor is connected with the constant low-voltage input end, the first pole of the sixth transistor is connected with the grid electrode of the fourth transistor, and the second pole of the sixth transistor is connected with the second node; a gate of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the constant high voltage input terminal, and a second pole of the seventh transistor is connected to the signal output terminal; the grid electrode of the eighth transistor is connected with the second node, the first pole of the eighth transistor is connected with the signal output end, and the second pole of the eighth transistor is connected with the second clock signal end; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are PMOS thin film transistors.

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the second capacitor; the grid electrode of the second transistor is connected with a second node, the first pole of the second transistor is connected with the second capacitor, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the first pole of the sixth transistor, and the second pole of the third transistor is connected with the signal input end; the grid electrode of the fourth transistor is connected with the first electrode of the sixth transistor, the first electrode of the fourth transistor is connected with the first clock signal end, and the second electrode of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the sixth transistor is connected with the constant low-voltage input end, the first pole of the sixth transistor is connected with the grid electrode of the fourth transistor, and the second pole of the sixth transistor is connected with the second node; a gate of the seventh transistor is connected to the first node, a first pole of the seventh transistor is connected to the constant high voltage input terminal, and a second pole of the seventh transistor is connected to the signal output terminal; the grid electrode of the eighth transistor is connected with the second node, the first pole of the eighth transistor is connected with the signal output end, and the second pole of the eighth transistor is connected with the second clock signal end; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS thin film transistors.

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a seventh transistor and an eighth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the signal output end; the grid electrode of the second transistor is connected with the second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the signal input end; the grid of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first clock signal end, and the second pole of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the seventh transistor is connected with the signal output end, the first pole of the seventh transistor is connected with the first pole of the eighth transistor, and the second pole of the seventh transistor is connected with the first node; a gate of the eighth transistor is connected to the first node, a first pole of the eighth transistor is connected to the first pole of the seventh transistor, and a second pole of the eighth transistor is connected to the constant high voltage input terminal; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are PMOS thin film transistors.

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the signal output end; the grid electrode of the second transistor is connected with the second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the second node, and the second pole of the third transistor is connected with the first pole of the sixth transistor; the grid of the fourth transistor is connected with the second node, the first pole of the fourth transistor is connected with the first clock signal end, and the second pole of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the sixth transistor is connected with the first clock signal end, the first pole of the sixth transistor is connected with the second pole of the third transistor, and the second pole of the sixth transistor is connected with the signal input end; the grid electrode of the seventh transistor is connected with the signal output end, the first pole of the seventh transistor is connected with the first pole of the eighth transistor, and the second pole of the seventh transistor is connected with the first node; a gate of the eighth transistor is connected to the first node, a first pole of the eighth transistor is connected to the first pole of the seventh transistor, and a second pole of the eighth transistor is connected to the constant high voltage input terminal; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS thin film transistors.

a shift register circuit of an active matrix organic light emitting display includes: the circuit comprises a first clock signal end, a second clock signal end, a signal input end, a signal output end, a constant high voltage input end, a constant low voltage input end, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor; wherein the grid of the first transistor is connected with the first node, the first pole of the first transistor is connected with the constant high voltage input end, and the second pole of the first transistor is connected with the signal output end; the grid electrode of the second transistor is connected with the second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end; the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the first pole of the sixth transistor, and the second pole of the third transistor is connected with the first pole of the ninth transistor; the grid electrode of the fourth transistor is connected with the first electrode of the sixth transistor, the first electrode of the fourth transistor is connected with the first clock signal end, and the second electrode of the fourth transistor is connected with the first node; the grid electrode of the fifth transistor is connected with the first clock signal end, the first pole of the fifth transistor is connected with the constant low voltage input end, and the second pole of the fifth transistor is connected with the first node; the grid electrode of the sixth transistor is connected with the constant low-voltage input end, the first pole of the sixth transistor is connected with the grid electrode of the fourth transistor, and the second pole of the sixth transistor is connected with the second node; the grid electrode of the seventh transistor is connected with the signal output end, the first pole of the seventh transistor is connected with the first pole of the eighth transistor, and the second pole of the seventh transistor is connected with the first node; a gate of the eighth transistor is connected to the first node, a first pole of the eighth transistor is connected to the first pole of the seventh transistor, and a second pole of the eighth transistor is connected to the constant high voltage input terminal; the grid electrode of the ninth transistor is connected with the first clock signal end, the first pole of the ninth transistor is connected with the second pole of the third transistor, and the second pole of the ninth transistor is connected with the signal input end; one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node; one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS thin film transistors.

an active matrix organic light emitting display includes a plurality of shift register circuits and is connected by cascade.

In the above possible design, a first pole of the ninth transistors of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is a drain, and a second pole of the ninth transistors of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is a source.

Drawings

FIG. 1 is a diagram of a shift register circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram of a shift register circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram of a shift register circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram of a shift register circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram of a shift register circuit according to a fifth embodiment of the present invention.

FIG. 6 is a diagram of a shift register circuit according to a sixth embodiment of the present invention.

FIG. 7 is a diagram of a shift register circuit according to a seventh embodiment of the present invention.

FIG. 8 is a timing chart of the driving of FIGS. 1 to 7 according to the present invention.

Description of reference numerals: M1-M9-a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, C1-C2-a first capacitor, a second capacitor, CKV 1-a first clock signal end, CKV 3-a second clock signal end, an IN-signal input end, an OUT-signal output end, a VGH-constant high voltage input end, a VGL-constant low voltage input end, and T1-T4-driving timing.

Detailed Description

The following detailed description and technical contents of the present invention are described with reference to the drawings, which are provided for reference and illustration purposes only and are not intended to limit the present invention. Various embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the present invention is not limited to only these embodiments. The invention is intended to cover alternatives, modifications, equivalents, and alternatives that may be included within the spirit and scope of the invention. In the following description of the preferred embodiments of the present invention, specific details are set forth in order to provide a thorough understanding of the present invention, and it will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

The present invention will disclose a plurality of embodiments of a shift register circuit of an active matrix organic light emitting display, and will be described in detail in sequence, where the active matrix organic light emitting display includes a display area and a non-display area surrounding the display area; the display region has pixels arranged in a matrix and a pixel circuit structure configured at a portion where scanning control lines in a row form to which control signals are supplied and signal lines in a column form to which data signals are supplied cross each other. The first to seventh embodiments of the shift register circuit of an active matrix organic light emitting display according to the present invention will be described in sequence, and the transistors will be described by grouping numbers according to the sequence of the signal input/output terminals connected to the gates in the following description of the related circuit driving.

[ first embodiment ]

Referring to fig. 1, in a preferred embodiment of the present invention, a shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 1. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 5 transistors (M1 to M5), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

the plurality of transistors include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5; the plurality of transistors may be PMOS transistors or NMOS transistors, but the manufacturing process of the NMOS transistors is more complicated and costly than the PMOS transistors, and thus, the cost of the shift register circuit can be reduced using the PMOS transistors. In the present embodiment, the plurality of transistors employ PMOS thin film transistors; the plurality of capacitors includes a first capacitor C1 and a second capacitor C2.

The gate of the first transistor M1 is connected to the first node N1, the first pole thereof is connected to the constant high voltage input terminal VGH and the second pole thereof is connected to the signal output terminal OUT;

the gate of the second transistor M2 is connected to the second node N2, the first pole thereof is connected to the signal output terminal OUT and the second pole thereof is connected to the second clock signal terminal CKV 3;

the gate of the third transistor M3 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the second node N2 and the second pole thereof is connected to the signal input terminal IN;

a gate of the fourth transistor M4 is connected to the second node N2, a first pole thereof is connected to the first clock signal terminal CKV1, and a second pole thereof is connected to the first node N1;

the gate of the fifth transistor M5 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the constant low voltage input terminal VGL and the second pole thereof is connected to the first node N1;

the first capacitor C1 has one end connected to the constant high voltage input terminal VGH and the other end connected to the first node N1, and the second capacitor C2 has one end connected to the second node N2 and the other end connected to the signal output terminal OUT.

In one embodiment, the first pole of the 5 transistors (M1-M5) is the drain, and the second pole of the 5 transistors (M1-M5) is the source.

In one embodiment, the 5 transistors (M1-M5) may be enhancement MOSFETs, depletion MOSFETs, bipolar junction transistors.

[ second embodiment ]

Referring to fig. 2, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 2. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 6 transistors (M1 to M6), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

the plurality of transistors includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. In the present embodiment, the plurality of transistors employ PMOS thin film transistors; the plurality of capacitors includes a first capacitor C1 and a second capacitor C2.

the gate of the third transistor M3 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the first pole of the sixth transistor M6 and the second pole thereof is connected to the signal input terminal IN;

the gate of the fourth transistor M4 is connected to the first pole of the sixth transistor M6, the first pole thereof is connected to the first clock signal terminal CKV1, and the second pole thereof is connected to the first node N1;

a gate of the sixth transistor M6 is connected to the constant low voltage input terminal VGL, a first pole thereof is connected to the gate of the fourth transistor M4 and a second pole thereof is connected to the second node N2;

the first capacitor C1 has one end connected to the constant high voltage input VGL and the other end connected to the first node N1, and the second capacitor C1 has one end connected to the second node N2 and the other end connected to the signal output terminal OUT.

In one embodiment, the first pole of the 6 transistors (M1-M6) is the drain, and the second pole of the 6 transistors (M1-M6) is the source.

In one embodiment, the 6 transistors (M1-M6) may be enhancement MOSFETs, depletion MOSFETs, bipolar junction transistors.

[ third embodiment ]

Referring to fig. 3, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 3. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 8 transistors (M1 to M8), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

the plurality of transistors includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. In the present embodiment, the plurality of transistors employ PMOS thin film transistors; the plurality of capacitors includes a first capacitor C1 and a second capacitor C2.

The gate of the first transistor M1 is connected to the first node N1, the first pole thereof is connected to the constant high voltage input VGH and the second pole thereof is connected to the second capacitor C2;

the gate of the second transistor M2 is connected to the second node N2, the first pole thereof is connected to the second capacitor C2 and the second pole thereof is connected to the second clock signal terminal CKV 3;

a gate of the seventh transistor M7 is connected to the first node N1, a first pole thereof is connected to the constant high voltage input terminal VGH and a second pole thereof is connected to the signal output terminal OUT;

the gate of the eighth transistor M8 is connected to the second node N2, the first pole thereof is connected to the signal output terminal OUT and the second pole thereof is connected to the second clock signal terminal CKV 3;

In one embodiment, the first pole of the 8 transistors (M1-M8) is the drain, and the second pole of the 8 transistors (M1-M8) is the source.

In one embodiment, the 8 transistors (M1-M8) may be enhancement MOSFETs, depletion MOSFETs, bipolar junction transistors.

[ fourth embodiment ]

Referring to fig. 4, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 4. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 8 transistors (M1 to M8), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

the plurality of transistors includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a seventh transistor M7, and an eighth transistor M8. In the present embodiment, the plurality of transistors employ PMOS thin film transistors; the plurality of capacitors includes a first capacitor C1 and a second capacitor C2.

the gate of the second transistor M2 is connected to the second node N1, the first pole thereof is connected to the signal output terminal OUT and the second pole thereof is connected to the second clock signal terminal CKV 3;

a gate of the seventh transistor M7 is connected to the signal output terminal OUT, a first pole thereof is connected to the first pole of the eighth transistor M8 and a second pole thereof is connected to the first node N1;

the gate of the eighth transistor M8 is connected to the first node N1, the first pole thereof is connected to the first pole of the seventh transistor M7 and the second pole thereof is connected to the constant high voltage input terminal VGH;

[ fifth embodiment ]

Referring to fig. 5, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 5. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 8 transistors (M1 to M8), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

[ sixth embodiment ]

Referring to fig. 6, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 6. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 8 transistors (M1 to M8), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

a gate of the third transistor M3 is connected to the first clock signal terminal CKV1, a first pole thereof is connected to the second node N2, and a second pole thereof is connected to a first pole of the sixth transistor M6;

a gate of the fourth transistor M3 is connected to the second node N2, a first pole thereof is connected to the first clock signal terminal CKV1, and a second pole thereof is connected to the first node N1;

the gate of the sixth transistor M6 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the second pole of the third transistor M3 and the second pole thereof is connected to the signal input terminal IN;

[ seventh embodiment ]

Referring to fig. 7, in another preferred embodiment of the present invention, the shift register circuit includes 2 input clock ports, a plurality of transistors and a plurality of capacitors, and a schematic diagram of the shift register circuit is shown in fig. 7. IN this embodiment, the shift register circuit includes a first clock signal terminal CKV1, a second clock signal terminal CKV3, a signal input terminal IN, a signal output terminal OUT, a constant high voltage input terminal VGH (high level), a constant low voltage input terminal VGL (low level), 9 transistors (M1 to M9), and 2 capacitors (C1 to C2). For simplicity of the schematic, all components having the same name in the figure are connected together by nodes (N1, N2) even if not directly connected. The structure of the shift register circuit is described as follows:

the plurality of transistors includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. In the present embodiment, the plurality of transistors employ PMOS thin film transistors; the plurality of capacitors includes a first capacitor C1 and a second capacitor C2.

the gate of the third transistor M3 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the first pole of the sixth transistor M6 and the second pole thereof is connected to the first pole of the ninth transistor M9;

the gate of the ninth transistor M9 is connected to the first clock signal terminal CKV1, the first pole thereof is connected to the second pole of the third transistor M3 and the second pole thereof is connected to the signal input terminal IN;

In one embodiment, the first pole of the 9 transistors (M1-M9) is the drain, and the second pole of the 9 transistors (M1-M9) is the source.

In one embodiment, the 9 transistors (M1-M9) may be enhancement MOSFETs, depletion MOSFETs, bipolar junction transistors.

Referring to fig. 8, in the driving process, fig. 8 provides timing waveforms of the shift register circuits according to the first to seventh embodiments of the present invention. In the present embodiment, the first clock signal terminal has a waveform of CKV1, and the second clock signal terminal has a waveform of CKV 3. At any moment, only one clock signal terminal of CKV1 and CKV3 outputs low level at most. The high level of the two clock signal terminals is VGH, and the low level is VGL. In order to sequentially generate the scan signals, a plurality of shift register circuits are cascaded. With reference to fig. 1 and the timing diagram (fig. 8), the following mainly describes the operation process of the shift register circuit according to the first embodiment of the present invention.

For convenience of explanation, a point at which the gate of the first transistor M1, the second pole of the fourth transistor M4, the second pole of the fifth transistor M5, and one end of the first capacitor C1 are connected is represented as a first node N1, and a point at which the gate of the second transistor M2, the first pole of the third transistor M3, one end of the second capacitor C1, and the gate of the fourth transistor M4 are connected is represented as a N2 node, as shown in fig. 1.

At stage T1, the first clock signal terminal CKV1 is a low voltage signal, the second clock signal terminal CKV3 is a high voltage signal, and the signal input terminal IN is a high voltage signal; at this time, the third transistor M3 and the fifth transistor M5 are turned on, the high voltage signal inputted from the signal input terminal IN is transferred to the second node N2 through the third transistor M3, resulting IN that the fourth transistor M4 and the second transistor M2 are turned off, the low voltage signal inputted from the constant low voltage input terminal VGL is transferred to the first node N1 through the fifth transistor M5, so that the first transistor M1 is turned on, and the high voltage signal inputted from the constant high voltage input terminal VGH is outputted from the signal output terminal OUT through the first transistor M1.

At stage T2, the first transistor M1 is turned on based on the first capacitor C1 and the first clock signal terminal CKV1, and the signal output terminal OUT of the shift register circuit outputs a high voltage signal. Specifically, during the period T2, the first clock signal terminal CKV1 turns into a high voltage signal, the second clock signal terminal CKV3 turns into a low voltage signal, and the signal input terminal IN holds the high voltage signal; at this time, the third transistor M3 and the fifth transistor M5 are turned off; meanwhile, under the coupling action of the second capacitor C2, the potential of the second node N2 becomes higher, so that a higher voltage of the second node N2 at the time of output is ensured, the second transistor M2 is completely turned off by the high voltage signal of the constant high voltage input terminal VGH, and the high voltage signal continuously input by the constant high voltage input terminal VGH is output from the signal output terminal OUT through the first transistor M1, without affecting the stability of the signal output by the signal output terminal OUT.

At stage T3, the first clock signal terminal CKV1 is converted into a low voltage signal, the second clock signal terminal CKV3 is converted into a high voltage signal, and the signal input terminal IN is converted into a low voltage signal; at this time, the third transistor M3 and the fifth transistor M5 are turned on again, the low voltage signal inputted from the signal input terminal IN is transmitted to the second node N2 through the third transistor M3, which causes the fourth transistor M4 and the second transistor M2 to be turned on, the low voltage signal inputted from the first clock signal terminal CKV1 is transmitted to the first node N1 through the fourth transistor M4, the potential of the first node N1 becomes lower due to the coupling effect of the second capacitor C2, which ensures that the first transistor M1 is fully turned on, and the high voltage signal continuously inputted from the constant high voltage input terminal VGH is outputted from the signal output terminal OUT through the first transistor M1, while the high voltage signal inputted from the second clock signal terminal CKV3 is outputted from the signal output terminal OUT through the first transistor M1.

At stage T4, the first clock signal terminal CKV1 is converted to a high voltage signal, the second clock signal terminal CKV3 is converted to a low voltage signal, and the signal input terminal IN is converted to a high voltage signal; at this time, the third transistor M3 and the fifth transistor M5 are turned off again, and the fourth transistor M4 and the second transistor M2 are turned on; meanwhile, the high voltage signal input by the constant high voltage input terminal VGH causes the potential of the first node N1 to rise due to the fourth transistor M4, so that the first transistor M1 turns off, and at this time, the first transistor M1 and the third transistor M3 play a role of current limiting, so that the first node N1 is prevented from sharing the potential of the second node N2, a lower voltage of the second node N2 at the time of output is ensured, and the second transistor M2 is ensured to be turned on, while the low voltage signal input by the second clock signal terminal CKV3 is output from the signal output terminal OUT through the second transistor M2, so that the signal output by the signal output terminal OUT is shifted.

The next stage is actually the process of repeating stages T1-T4, and thus is not described in detail. The present invention is described by taking the driving timing of the shift register circuit of the first embodiment as an example, and the waveforms of the driving timing of the other embodiments are all as shown in fig. 8.

In summary, the shift register circuit provided in the first to seventh embodiments of the present invention is made of PMOS transistors, and has the characteristics of simple structure and good reliability, and can effectively simplify the circuit structure and reduce the cost of the shift register; moreover, after an effective low potential is output, each capacitor holding node has a constant potential to be written in discontinuously, so that the stability of low voltage of the node is ensured, and the stability of the shift register circuit is further improved; compared with other circuits, the circuit has strong anti-interference capability and high reliability, and can be widely applied to driving circuits in various display industries.

The foregoing description shows and describes several preferred embodiments of the invention, but as before, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

the circuit comprises a first clock signal terminal, a second clock signal terminal, a signal input terminal, a signal output terminal, a constant high voltage input terminal, a constant low voltage input terminal, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor;

wherein the gate of the first transistor is connected to a first node, the first pole of which is connected to the constant high voltage input terminal and the second pole of which is connected to the signal output terminal;

the grid electrode of the second transistor is connected with a second node, the first pole of the second transistor is connected with the signal output end, and the second pole of the second transistor is connected with the second clock signal end;

a gate of the third transistor is connected to the first clock signal terminal, a first pole thereof is connected to the second node, and a second pole thereof is connected to the signal input terminal;

a gate of the fourth transistor is connected to the second node, a first pole of the fourth transistor is connected to the first clock signal terminal, and a second pole of the fourth transistor is connected to the first node;

a gate of the fifth transistor is connected to the first clock signal terminal, a first pole thereof is connected to the constant low voltage input terminal, and a second pole thereof is connected to the first node;

one end of the first capacitor is connected with the constant high-voltage input end, and the other end of the first capacitor is connected with the first node;

one end of the second capacitor is connected with the second node, and the other end of the second capacitor is connected with the signal output end; and

the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are PMOS thin film transistors.

2. The shift register circuit of an active matrix organic light emitting display according to claim 1, wherein first poles of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are drain electrodes, and second poles of the first transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are source electrodes.

3. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

the circuit comprises a first clock signal terminal, a second clock signal terminal, a signal input terminal, a signal output terminal, a constant high voltage input terminal, a constant low voltage input terminal, a plurality of transistors and a plurality of capacitors, wherein the plurality of transistors comprise a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, and the plurality of capacitors comprise a first capacitor and a second capacitor;

the grid electrode of the third transistor is connected with the first clock signal end, the first pole of the third transistor is connected with the first pole of the sixth transistor, and the second pole of the third transistor is connected with the signal input end;

a gate of the fourth transistor is connected to a first pole of the sixth transistor, a first pole of the fourth transistor is connected to the first clock signal terminal, and a second pole of the fourth transistor is connected to the first node;

the grid electrode of the sixth transistor is connected with the constant low voltage input end, the first pole of the sixth transistor is connected with the grid electrode of the fourth transistor, and the second pole of the sixth transistor is connected with the second node;

the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are PMOS thin film transistors.

4. The shift register circuit of claim 3, wherein first electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are drain electrodes, and second electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are source electrodes.

5. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

a first clock signal terminal, a second clock signal terminal, a signal input terminal, a signal output terminal, a constant high voltage input terminal, a constant low voltage input terminal, a plurality of transistors including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, and a plurality of capacitors including a first capacitor and a second capacitor;

wherein the gate of the first transistor is connected to a first node, a first pole thereof is connected to the constant high voltage input terminal and a second pole thereof is connected to the second capacitor;

the grid electrode of the second transistor is connected with a second node, the first pole of the second transistor is connected with the second capacitor, and the second pole of the second transistor is connected with the second clock signal end;

a gate of the seventh transistor is connected to the first node, a first pole thereof is connected to the constant high voltage input terminal, and a second pole thereof is connected to the signal output terminal;

a gate of the eighth transistor is connected to the second node, a first pole of the eighth transistor is connected to the signal output terminal, and a second pole of the eighth transistor is connected to the second clock signal terminal;

the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are PMOS thin film transistors.

6. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

a first clock signal terminal, a second clock signal terminal, a signal input terminal, a signal output terminal, a constant high voltage input terminal, a constant low voltage input terminal, a plurality of transistors including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a seventh transistor, and an eighth transistor, and a plurality of capacitors including a first capacitor and a second capacitor;

a gate of the seventh transistor is connected to the signal output terminal, a first pole of the seventh transistor is connected to the first pole of the eighth transistor, and a second pole of the seventh transistor is connected to the first node;

a gate of the eighth transistor is connected to the first node, a first pole of the eighth transistor is connected to the first pole of the seventh transistor, and a second pole of the eighth transistor is connected to the constant high voltage input terminal;

the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are PMOS thin film transistors.

7. The shift register circuit of claim 6, wherein first electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are drain electrodes, and second electrodes of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the seventh transistor, and the eighth transistor are source electrodes.

8. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

9. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

a gate of the third transistor is connected to the first clock signal terminal, a first pole thereof is connected to the second node, and a second pole thereof is connected to a first pole of the sixth transistor;

a gate of the sixth transistor is connected to the first clock signal terminal, a first pole thereof is connected to the second pole of the third transistor, and a second pole thereof is connected to the signal input terminal;

10. The shift register circuit of any one of claims 5, 8, and 9, wherein a first electrode of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a drain electrode, and a second electrode of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor is a source electrode.

11. A shift register circuit of an active matrix organic light emitting display is characterized by comprising:

a first clock signal terminal, a second clock signal terminal, a signal input terminal, a signal output terminal, a constant high voltage input terminal, a constant low voltage input terminal, a plurality of transistors including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, and a plurality of capacitors including a first capacitor and a second capacitor;

a gate of the third transistor is connected to the first clock signal terminal, a first pole of the third transistor is connected to the first pole of the sixth transistor, and a second pole of the third transistor is connected to the first pole of the ninth transistor;

a gate of the ninth transistor is connected to the first clock signal terminal, a first pole of the ninth transistor is connected to the second pole of the third transistor, and a second pole of the ninth transistor is connected to the signal input terminal;

the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are PMOS thin film transistors.

12. The shift register circuit of an active matrix organic light emitting display according to claim 10, wherein a first electrode of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is a drain electrode, and a second electrode of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor is a source electrode.

13. An active matrix organic light emitting display, comprising the plurality of shift register circuits of claims 1,3,5-6,8-9,11, the plurality of shift register circuits being connected in cascade.