CN112104343B - A current type level transition monitoring unit - Google Patents

Abstract

The invention discloses a current-type level jump monitoring unit, which is used for monitoring late-arriving data jump in an adaptive voltage and frequency adjustment technology, and is characterized by comprising: a charging path unit 1, a charging path unit 2, a controllable Switch M9, inverter U1 and high threshold buffer U2. The jump monitoring unit of the present invention has obvious advantages in response time and minimum operating voltage, and can work stably in the region as low as the near-threshold value, thereby expanding the range of voltage regulation to the near-threshold region, and the overall power consumption benefit is relatively large; The response time of the clock is very short, and the data transition during the high level of the clock can be monitored in a very short time.

Description

A current type level jump monitoring unit

technical field

The invention relates to a current-type level jump monitoring unit applied in the adaptive voltage technology. The circuit can be used in the adaptive voltage adjustment technology to monitor circuit timing errors, so as to issue early warnings for timing violations. and avoid timing errors. The whole circuit is realized by pure digital logic, which belongs to the field of integrated circuit design.

Background technique

With the continuous growth of the scale and computing power of integrated circuits, and application scenarios such as the Internet of Things, embedded devices, mobile terminals, supercomputers and data centers, the energy consumption of devices is increasingly demanding. In IoT applications, terminal devices often require a long battery life. Therefore, energy consumption plays a vital role in the survivability and functional integrity of IoT devices. For mobile terminals, higher requirements are put forward for their standby time. However, due to the slow development of battery technology in recent years, device power consumption has become an important factor affecting user experience in the mobile Internet era. For supercomputers and data centers, scaling up computer performance is also severely constrained by energy consumption.

The development of high-energy-efficiency integrated circuits is an important means to solve the problem of energy consumption in computing systems, and reducing the operating voltage of chips can greatly reduce the power consumption of chips. One of the problems solved.

Near-threshold integrated circuit design can achieve substantial performance improvement by reducing the power supply voltage of a chip or circuit to a level close to the threshold voltage of a transistor. It is considered to be one of the most promising technologies for improving computing performance in the future.

While near-threshold technology brings about a substantial improvement in chip energy efficiency, it also poses challenges to designers. In the application of near-threshold technology, the performance of integrated circuits is affected by process (Process), voltage (Voltage), temperature (Temperature) deviations, that is, PVT deviations. This makes the delay distribution of the circuit larger, which in turn causes the deviation of the path delay to increase exponentially. In order to ensure that the chip can work stably under various conditions, traditional designers usually need to reserve a large amount of timing margin to meet the worst-case timing constraints. At the same time, in order to prevent the influence of circuit aging, random noise, 1/f noise and other factors, designers also need to leave some margin in the design process. This results in a great waste of performance and power consumption, which greatly weakens the energy efficiency improvement brought by the near-threshold design.

In order to reduce the excessive design margin of the circuit, better release the potential of wide voltage design, and overcome the problem of severe PVT deviation under low voltage, Adaptive Voltage Frequency Scaling (AVFS) technology came into being . In the actual operation of the chip, the probability of extreme environments is extremely low, and the adaptive voltage design scheme can adaptively adjust the working voltage and frequency of the chip according to the different working environments, which can not only ensure the correctness of the chip function, but also Reduce the design margin reserved by the chip as much as possible, so as to achieve the purpose of saving power consumption.

The core of the adaptive voltage frequency adjustment technology is to monitor the timing of the circuit on-line, and adjust the operating voltage/frequency of the control chip in real time according to the tightness of the timing. The current research on adaptive voltage design, especially the adaptive voltage technology under wide voltage. Surveillance is the main method. The most typical representative of direct monitoring is the Razor series researched by the University of Michigan. However, this method usually replaces the flip-flop at the end of the critical path with a timing monitoring unit and a latch.

Timing monitoring can be achieved with a transition monitor, which monitors for late arriving data transitions. A qualified jump unit should have the following characteristics: First, it can effectively monitor the timing of the circuit, because the core function of the monitoring unit module is to monitor the timing of the circuit; The in-situ monitoring method needs to insert the monitoring unit module into the original design, and the original design needs to be modified, which will affect the timing of the inserted path; third, the area overhead should be as small as possible. And the present invention fully meets the requirements of these three points.

Contents of the invention

Purpose of the invention:

The object of the present invention is to provide a stable, fast, and small area cost timing monitoring unit to monitor late data transitions and provide information on timing violations for adaptive voltage and frequency adjustment.

Technical solutions:

In order to achieve the purpose of the above invention, the technical solution of the present invention is a jump monitoring unit suitable for stable operation under wide voltage, small area cost and fast response speed, which is used to monitor whether the timing of the digital integrated circuit is violated, that is, whether there is a Late data jumps, if any, generate a pulse signal.

输入数据信号D、反相输入数据信号DN；所述充电路径单元2包括三个控制输入端，分别连接时钟信号Pck、输入数据信号D、反相输入数据信号DN；所述充电路径单元1、充电路径单元2的输出端均连接至可控开关M9的一端形成节点Error，可控开关M9的另一端接地，其控制端连接反相时钟信号

当时钟信号Pck为有效电平时，使能跳变监测单元，可控开关M9断开，充电路径单元1或充电路径单元2响应输入数据信号D的电平跳变对节点Error进行充电，节点Error输出时序预警信号。A current-type level jump monitoring unit is characterized in that it includes: a charging path unit 1, a charging path unit 2, a controllable switch M9, an inverter U1 and a buffer U2; the input terminal of the inverter U1 is connected to The input data signal D is input, the input end of the buffer U2 is connected to the output end of the inverter U1, and the output end of the buffer U2 outputs an inverted input data signal DN; the charging path unit 1 includes three control input ends, respectively Connecting an Inverted Clock Signal

Input data signal D, inverting input data signal DN; the charging path unit 2 includes three control input terminals, respectively connected to the clock signal Pck, input data signal D, and inverting input data signal DN; the charging path unit 1, The output ends of the charging path unit 2 are connected to one end of the controllable switch M9 to form a node Error, the other end of the controllable switch M9 is grounded, and its control end is connected to an inverted clock signal

When the clock signal Pck is at an active level, the transition monitoring unit is enabled, the controllable switch M9 is turned off, and the charging path unit 1 or charging path unit 2 charges the node Error in response to the level transition of the input data signal D, and the node Error Output timing warning signal.

The jump monitoring unit in the present invention monitors whether the data signal jumps when the clock signal is at an effective level (designed as a high level in the specific embodiment of the invention), and generates a timing warning signal, and when the clock signal is at When the level is inactive (designed as a low level in the specific embodiment of the present invention), it does not respond to the transition of data. The present invention divides the transition of the data signal into two cases, respectively: 1) transition of the data signal from low to high; 2) transition of the data signal from high to low. Two charging paths are used to respond to these two forms of jumps respectively, and to complete the charging of the output node Error.

In the specific embodiment of the present invention, the buffer is implemented by a high-threshold transistor, so that it has a relatively large delay, which ensures that the above-mentioned charging path has enough time to charge the node Error to the same potential as VDD in the two cases, thereby ensuring The jump monitoring unit can work stably in the low to near-threshold area.

When the jump monitoring unit of the present invention is used for timing monitoring in the detected main circuit, a group of jump monitoring units are usually placed in several critical paths of the main circuit, and all output Error signals can be collected and generated by dynamic OR gates The total early warning signal, combined with the downstream control logic for adaptive adjustment of voltage and frequency, can effectively avoid possible timing errors. The jump monitoring unit of the present invention can monitor the data jump during the high level of the clock in a very short time, thereby gaining more time for voltage frequency adjustment for the whole system.

Beneficial effect:

The jump monitoring unit provided by the present invention can monitor timing errors in the digital integrated circuit path, and in the application of adaptive voltage frequency adjustment (AVS) technology, can effectively reduce the influence of PVT deviation and other factors in the design process. The reserved margin can greatly stimulate the potential of integrated circuits and improve energy efficiency. Compared with similar timing monitoring units in the world, the jump monitoring unit described in the present invention has obvious advantages in response time and minimum operating voltage, and can work stably in the low to near-threshold region, thereby expanding the range of voltage regulation In the near-threshold area, the overall power consumption gain is greater; in addition, its response time is very short, and the data transition during the high level of the clock can be monitored in a very short time.

Description of drawings

Figure 1 is a schematic diagram of the application of the jump monitoring unit;

Fig. 2 is a transistor structure diagram of the jump monitoring unit;

Fig. 3 is the timing diagram of the working principle of the jump monitoring unit;

Figure 4 is a HSPICE simulation diagram of the jump monitoring unit;

Figure 5 shows the frequency gain of the adaptive voltage frequency regulation using the jump monitoring unit.

Detailed ways

The application mode of the monitoring circuit of the present invention in the main circuit is shown in FIG. 1 , which belongs to the direct monitoring method, and the trigger at the end of the critical path is replaced by a timing monitoring unit and a latch. The timing monitoring unit is realized by the jump monitoring unit of the present invention.

The content of the present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

The main structure of this embodiment is shown in FIG. 2 . The jump monitoring unit described in the present invention is composed of 3 NMOS transistors M5, M6, M9, 6 PMOS transistors M1, M2, M3, M4, M7, M8, 1 inverter U1 and 1 buffer U2 , consisting of a total of 15 transistors. The transistors M1, M2, and M3 form a charging path unit 1, and the transistors M4, M5, M6, M7, and M8 form a charging path unit 2, respectively completing the charging of the node Error. The error warning signal Error output of the jump monitoring unit is directly connected to the gate input of the NMOS transistor of the dynamic OR gate. The input of the buffer U2 is connected to the output of the inverter U1 for generating the inverted signal DN of the input data signal D. It should be noted that under different PVT conditions, the delay of D and DN must be kept large enough to ensure the normal timing warning function. Therefore, the buffer unit U2 of the present invention uses a high threshold (HVT) transistor to increase the delay of D and DN. time delay, other cells use low threshold (LVT) transistors.

The source of the NMOS transistor M9 is grounded, the drain is the virtual ground node Error, and the gate is connected to the inverse signal of the clock. M9 plays the role of a switch, it is always on when the clock signal Pck is low level, and discharges the node Error to low level, at this time the whole transition monitoring circuit does not work, and its output is always zero; and when the clock signal is high When the level is high, M9 is closed, and the jump monitoring unit performs its function at this time, and generates a high-level pulse through the node Error, indicating that a timing violation has been detected.

PMOS管M2的源极与PMOS管M1的漏极相连，而PMOS管M2的漏极，则是与PMOS管M3的源极相连，PMOS管M2的栅极输入为反相输入数据信号DN。PMOS管M3的源极与PMOS管M2的漏极相连，PMOS管M3的漏极与节点Error相连，PMOS管M3的栅极与输入数据信号D相连。上述3个晶体管M1、M2、M3组成充电路径单元1，监测时钟高电平期间数据D是否发生了从高到低的跳变。The source of the PMOS transistor M1 is connected to the power supply VDD, the drain is connected to the source of the PMOS transistor M2, and the gate input is an inverted clock signal

The source of the PMOS transistor M2 is connected to the drain of the PMOS transistor M1, and the drain of the PMOS transistor M2 is connected to the source of the PMOS transistor M3, and the gate input of the PMOS transistor M2 is an inverted input data signal DN. The source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M3 is connected to the node Error, and the gate of the PMOS transistor M3 is connected to the input data signal D. The above three transistors M1, M2 and M3 form a charging path unit 1, which monitors whether the data D transitions from high to low during the high level period of the clock.

The source of the PMOS transistor M4 is connected to the power supply VDD, the drain is connected to the node m, and the gate is connected to a clock signal. The drain of the NMOS transistor M5 is connected to the node m, the source is connected to the drain of the NMOS transistor M6, and the gate input is the inverted data signal DN. The drain of the NMOS transistor M6 is connected to the drain of the NMOS transistor M5, the source is grounded, and the data signal D is used as its gate input. Node m serves as the input of PMOS transistors M7 and M8, and M7 and M8 are connected in series. The drain of the PMOS transistor M8 is connected to the node Error. The above five transistors M7, M8, M4, M5, M6 together form a charging path unit 2, which monitors whether the data D transitions from low to high during the high level period of the clock. Wherein, the transistors M7, M8 form the charging path, and the transistors M4, M5, M6 form the control unit, which provide the charging control signal for the charging path M7, M8. The node Error is used as the output end of the circuit sequence error early warning signal, and is connected with the downstream dynamic OR gate.

The working principle of the jump monitoring unit is as follows:

When the data D changes from low to high, the data DN changes from high to low, but because there is a large delay in the high-threshold buffer U2, there is also a certain delay in the change of the data DN relative to the data D. During this time The internal data D and DN are kept high. The transistors M5 and M6 are kept turned on. At this time, the charges at the node m are discharged through the transistors M5 and M6, and the level of the node m is discharged to a low level. The node m is used as the input of the PMOS transistors M7 and M8, so that M7 and M8 are turned on, thereby charging the node Error and generating a high-level warning signal.

When the data D changes from high to low, the data DN changes from low to high, but also due to the delay of the inverter U1 and the buffer U2, the change of the data DN relative to the data D has a certain delay. During this period of time, the data D and DN are kept at low level, the transistors M2 and M3 are kept on, the node Error will be charged to the same potential as VDD, and an early warning signal is issued.

The timing diagram of the jump monitoring unit is shown in Figure 3, which is mainly divided into the following four situations:

Case1, Case2: When the clock signal is at low level, regardless of the change of data D from low to high or from high to low, since the transistor M9 remains on at this time, the node Error remains "0", and the warning signal is always remains low.

·Case3: When the clock signal is at a high level, when the data D changes from low to high, an early warning signal is issued at this time. When the clock is at a high level, the transistor M9 is turned off, and the transistor M4 is turned off. When the data D changes from low to high, the data DN changes from high to low, but due to the delay of the units U1 and U2, the data DN relative to the data D There is a certain delay in the change. During this period, the data D and DN are kept at high level, and the transistors M5 and M6 are kept on. At this time, the charge of node m is discharged through transistors M5 and M6, and the level of node m is discharged. to a low level, at this time transistors M7 and M8 remain turned on. The node Error will be charged to the same potential as VDD while the data D and DN are both at a high level, that is, the warning signal Error becomes a high level. Under different PVT conditions, the time delay of D and DN must be kept large enough to guarantee the normal sequence early warning function. Therefore, in the present invention, unit U2 adopts a high threshold value (HVT) unit to increase the time delay of D and DN, Other cells use low threshold (LVT).

·Case4: When the clock signal is at a high level, when the data D changes from high to low, an early warning signal is issued at this time. When the clock is at a high level, the transistor M9 is turned off, and the MOS transistor M1 is turned on. When the data D changes from high to low, the data DN changes from low to high, but due to the delay of the units U1 and U2, the data DN is relative to the data D There is a certain delay in the change of the data D and DN during this period. At this time, the transistors M2 and M3 are kept on, and the node Error will be charged to the same potential as VDD, that is, the warning signal Error becomes high level.

·Other situations: During the high or low level period of the clock, the data D does not flip, and there is no timing warning at this time. When the data D does not flip, there is no charging path to the node Error, and the node Error remains at a low level.

Under normal operation, when no errors occur, data arrives before the rising edge of the clock, and the error pre-alarm signal remains low at this time. When a timing error occurs due to delayed arrival of a signal, a positive pulse is generated as an error warning signal. To reduce the propagation delay of false early warning signals, a dynamic OR gate is used to aggregate all early warning signals from different paths. A dynamic OR gate can collect error warning signals from up to 10 transition detection units. The output signal of the dynamic OR gate is ORed by the traditional OR gate to generate a global error warning signal, which is used to control the clock gating circuit and reset to 0 by the reset signal.

When a timing error signal is detected, the time borrowing (Time-borrowing) of the latch can still transmit data correctly, so as to avoid real timing errors.

Fig. 4 is the simulation result of the present invention. In order to verify the correctness of the transition monitoring unit function described in the present invention, design is carried out under the 28nm CMOS technology, and Monte Carlo simulation is carried out to it, and the working condition of simulation is 0.46V, 25 ℃, Monte Carlo simulation (5000 times), The operating frequency of the clock is 50MHz, and the specific simulation results are shown in Figure 4, where the signal Pck is the clock signal, D is the data input signal, and Error is the early warning signal. It can be seen from the figure that when the data D jumps during the high level period of the clock signal, the warning signal Error becomes high level; in other cases, the level of the node Error is always kept at low level.

As shown in Figure 5, the effect of the jump monitoring unit applied to the adaptive voltage frequency adjustment design. The verification platform adopted is 8-bit AES (Advanced Encryption Standard, AES) circuit. There are a total of 24 chips tested this time, and 8 chips were selected from the three wafers of FF, TT, and SS for testing. The reference frequency refers to the highest operating frequency after considering the timing margin reserved by the chip. Considering the actual test conditions, the test temperature range is 0°C to 85°C, and the worst process corner uses the worst performance chip in this batch. chip instead. According to the screening criteria, conduct actual tests on these chips to find the reference frequency. According to the method of finding the reference frequency, the reference frequency under different voltages was tested. At the same time, a chip with a typical process angle was selected to measure its highest frequency under 0.55V ~ 1.1V, the highest operating frequency and reference frequency of the test. The distribution diagram is shown in the figure. Under the voltage of 0.55V, the maximum operating frequency of the chip is three times of its reference frequency, so the adaptive voltage design designed in this paper can improve the performance by three times under the voltage of 0.55V. It should be pointed out that due to the temperature inversion effect, the worst operating temperature of the chip at 0.8V~1.1V is 85°C, and the worst operating temperature at 0.5V~0.7V is 0°C.

If the above system is changed to adjust the voltage to eliminate the margin, compared with the traditional design with margin, the adaptive voltage design of the jump monitoring unit can obtain power consumption benefits.

Table 1 is a parameter comparison between the jump monitoring unit of the present invention and the same kind of timing monitoring unit in the world, wherein the number of transistors of the standard latch (Latch) as a comparison reference in the table is 19 (with a reset terminal), and the additional Transistor count, area penalty, power consumption penalty and response time are compared to standard latches. Compared with the foreign excellent timing monitoring unit design, the jump monitoring unit designed in the present invention has obvious advantages in response time and minimum working voltage, and its minimum working voltage is 0.46V.

Table 1 Comparison of parameters between the jump monitoring unit and similar timing monitoring units in the world

As stated above, while the invention has been shown and described with reference to certain preferred embodiments, this should not be construed as limiting the invention itself. Various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

[references]

[1] Seongjong Kim and Mingoo Seok. Variation-Tolerant, Ultra-Low-Voltage Microprocessor with a Low-Overhead, Within-a-Cycle In-Situ Timing-ErrorDetection and Correction Technique[J].IEEE J.Solid-State Circuits, 2015, 50(6): 1478-1490

[2]S.Das et al.A 1GHz hardware loop-accelerator with razor-baseddynamic adaptation for energy-efficient operation[J].IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, 61(8): 2290-2298

[3] Zhang Y, Khayatzadeh M, Yang K, et al. iRazor: 3-transistor current-based error detection and correction in an arm cortex-r4 processor [C]. IEEE Solid-State Circuits Conference (ISSCC), 2016: 160 -162

Claims (7)

1. A current mode level jump monitoring unit, comprising: a charging path unit 1, a charging path unit 2, a controllable switch M9, an inverter U1 and a buffer U2; the input end of the phase inverter U1 is connected with an input data signal D, and the output end of the buffer U2The input end is connected with the output end of the phase inverter U1, and the output end of the buffer U2 outputs an inverted input data signal DN; the charging path unit 1 comprises three control input ends which are respectively connected with inverted clock signals

An input data signal D, an inverted input data signal DN; the charging path unit 2 comprises three control input ends which are respectively connected with a clock signal Pck, an input data signal D and an inverted input data signal DN; the output ends of the charging path unit 1 and the charging path unit 2 are connected to one end of a controllable switch M9 to form a node Error, the other end of the controllable switch M9 is grounded, and the control end of the controllable switch is connected with an inverted clock signal

When the clock signal Pck is at an effective level, the jump monitoring unit is enabled, the controllable switch M9 is turned off, the charging path unit 1 or the charging path unit 2 charges the node Error in response to the level jump of the input data signal D, and the node Error outputs a timing early warning signal.

2. A current mode level-jump monitoring unit as claimed in claim 1, wherein: the buffer U2 is implemented using high threshold transistors.

3. A current mode level transition monitoring unit as claimed in claim 1 or 2, wherein: the charging path unit 1 comprises three MOS transistors connected in series between a power supply VDD and a node Error, and gates of the three MOS transistors are used as three control input ends of the charging path unit 1.

4. A current mode level-jump monitoring unit as claimed in claim 3, wherein: the charging path unit 1 comprises PMOS transistors M1, M2 and M3, the PMOS transistors M1, M2 and M3 are sequentially connected in series, the source electrode of the PMOS transistor M1 is connected with a power supply VDD, the drain electrode of the PMOS transistor M3 is connected with a node Error, and the PMOS transistors M1, M2 and M3The grids are respectively connected with the inverted clock signals

Inverted input data signal DN, input data signal D.

5. A current mode level jump monitoring unit according to claim 1 or 2, wherein: the charging path unit 2 includes two MOS transistors connected in series between a power supply VDD and a node Error, and a control circuit that supplies a charging control signal to the two MOS transistors, the control circuit includes three MOS transistors connected in series between the power supply VDD and ground, and gates of the three MOS transistors serve as three control input terminals of the charging path unit 2.

6. A current mode level jump monitoring unit according to claim 5, wherein: the charging path unit 2 comprises PMOS transistors M4, M7 and M8 and NMOS transistors M5 and M6, the PMOS transistor M4 and the NMOS transistors M5 and M6 are sequentially connected in series, the PMOS transistors M7 and M8 are sequentially connected in series, the sources of the PMOS transistor M4 and the PMOS transistor M7 are respectively connected with a power supply VDD, the source of the NMOS transistor M6 is grounded, the drain of the PMOS transistor M8 is connected with a node Error, and the gates of the PMOS transistor M4 and the NMOS transistors M5 and M6 are respectively connected with a clock signal Pck, an inverted input data signal DN and an input data signal D; the gates of the PMOS transistors M7, M8 are connected to form a node M, and the drains of the PMOS transistor M4 and the NMOS transistor M5 are connected to the node M.

7. A current mode level-jump monitoring unit as claimed in claim 1 or 2, characterized in that: the controllable switch M9 is implemented by a MOS transistor.

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