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CN111968975A - Circuit chip, three-dimensional memory and method for preparing three-dimensional memory - Google Patents

Circuit chip, three-dimensional memory and method for preparing three-dimensional memory Download PDF

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Publication number
CN111968975A
CN111968975A CN202010786389.2A CN202010786389A CN111968975A CN 111968975 A CN111968975 A CN 111968975A CN 202010786389 A CN202010786389 A CN 202010786389A CN 111968975 A CN111968975 A CN 111968975A
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China
Prior art keywords
substrate
circuit chip
isolation structure
trench isolation
transistor
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Pending
Application number
CN202010786389.2A
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Chinese (zh)
Inventor
陈亮
刘威
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN202010786389.2A priority Critical patent/CN111968975A/en
Publication of CN111968975A publication Critical patent/CN111968975A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The present invention provides a circuit chip, including: a substrate; a transistor circuit formed on a front side of a substrate, including a plurality of transistor cells arranged on the substrate; the isolation structure is arranged between the transistor units and used for electrically isolating the adjacent transistor units, and comprises a shallow trench isolation structure and a back-side deep trench isolation structure which are formed in the substrate, wherein the back-side deep trench isolation structure is in contact with the shallow trench isolation structure and extends to the back side of the circuit chip, and the back side of the circuit chip is arranged opposite to the front side of the substrate.

Description

Circuit chip, three-dimensional memory and method for preparing three-dimensional memory
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a circuit chip, a three-dimensional memory, and a method for manufacturing a three-dimensional memory.
Background
In three-dimensional NAND memories, chip size may limit the spacing between high voltage NMOS devices in the word line decode pass transistor circuit in the X and Y directions. During a cell programming operation, the pass transistor needs to pass the high voltage of 25V of the source/drain region at a gate voltage of 29V, and the voltage difference between adjacent high voltage NMOS devices is about 25V.
In the prior art, punch-through is suppressed by forming p-type field implants between the high voltage NMOS devices in the X-direction, and latch-up is suppressed by forming p + taps between the high voltage NMOS devices in the Y-direction, but this prevents the pitch between the high voltage NMOS devices from being further reduced, which results in the chip not being further reduced in size.
Disclosure of Invention
The application provides a circuit chip, a three-dimensional memory and a method for preparing the three-dimensional memory, which effectively solve the problem that the size of the chip cannot be further reduced due to the fact that the distance between high-voltage NMOS devices cannot be continuously reduced.
In order to solve the above problem, the present invention provides a circuit chip including:
a substrate;
a transistor circuit formed on a front side of the substrate, including a plurality of transistor cells arranged on the substrate;
an isolation structure between the transistor cells for electrically isolating adjacent transistor cells, and comprising: a shallow trench isolation structure formed in the substrate, and; a backside deep trench isolation structure formed in the substrate and contacting the shallow trench isolation structure and extending to a backside of the circuit chip, wherein the backside of the circuit chip is disposed opposite the front side of the substrate.
Further preferably, the transistor units are arranged in an array along the row and column directions, and the isolation structures are formed between adjacent rows and adjacent columns of the transistor units.
Further preferably, an extraction structure is further formed in the substrate, and one end of the extraction structure is in contact with the substrate, and the other end of the extraction structure extends to the back side of the circuit chip.
Further preferably, the one end of the extraction structure extends to a common doped region of the transistor unit.
Further preferably, a bottom metal layer is formed on the back side of the circuit chip, and the bottom metal layer is in contact with the other end of the lead-out structure and is used for connecting a control circuit outside the circuit chip.
Further preferably, the spacing between adjacent transistor cells is less than 0.5 microns.
Further preferably, the transistors are high voltage NMOS transistors, and the difference in bias voltage between adjacent transistors is 20V or more.
In another aspect, the present invention further provides a three-dimensional memory, which includes a memory array chip and a circuit chip bonded to the memory array chip up and down as a peripheral circuit as described in any one of the above.
In another aspect, the present invention further provides a method for manufacturing a three-dimensional memory, where the method includes a step of forming a circuit chip, and specifically includes:
providing a substrate;
providing a transistor circuit formed on a front side of the substrate, comprising a plurality of transistor cells arranged on the substrate;
providing a shallow trench isolation structure formed in the substrate, and;
providing a backside deep trench isolation structure formed in the substrate and contacting the shallow trench isolation structure and extending to a backside of the circuit chip, wherein the backside of the circuit chip is disposed opposite the front side of the substrate and the shallow trench isolation structure and the backside deep trench isolation structure form an isolation structure.
Further preferably, before the step of providing the backside deep trench isolation structure, the method further includes:
and providing a storage array chip, and connecting the storage array chip and the circuit chip in a wafer bonding mode to form the three-dimensional memory.
Further preferably, before the step of providing the backside deep trench isolation structure, the method further includes:
and thinning the substrate.
Further preferably, after the step of providing the backside deep trench isolation structure, the method further includes:
and providing an extraction structure, wherein the extraction structure is formed in the substrate, one end of the extraction structure is in contact with the substrate, and the other end of the extraction structure extends to the back side of the circuit chip.
Further preferably, the one end of the extraction structure extends to a common doped region of the transistor unit.
Further preferably, after the step of providing the lead-out structure, the method further includes:
and providing a bottom metal layer, wherein the bottom metal layer is formed on the back side of the circuit chip, is in contact with the other end of the lead-out structure and is used for connecting a control circuit outside the circuit chip.
The invention has the beneficial effects that: the present invention provides a circuit chip, including: a substrate; a transistor circuit formed on a front side of a substrate, including a plurality of transistor cells arranged on the substrate; the isolation structure is arranged between the transistor units and used for electrically isolating the adjacent transistor units, and comprises a shallow trench isolation structure and a back-side deep trench isolation structure which are formed in the substrate, wherein the back-side deep trench isolation structure is in contact with the shallow trench isolation structure and extends to the back side of the circuit chip, and the back side of the circuit chip is arranged opposite to the front side of the substrate.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments according to the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic front view of a circuit chip according to a first embodiment of the present invention.
Fig. 2 is a schematic top view of a circuit chip according to a first embodiment of the present invention.
Fig. 3 is a schematic front view of a circuit chip according to a second embodiment of the present invention.
Fig. 4 is a schematic top view of a circuit chip according to a second embodiment of the present invention.
Fig. 5 is a schematic front view of a three-dimensional memory according to an embodiment of the invention.
Fig. 6 is a flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
It should be noted that the thicknesses and shapes in the drawings of the present invention do not reflect actual proportions, and are merely intended to schematically illustrate various embodiments of the present invention.
The embodiment of the invention is used for solving the problem that the size of a circuit chip in the prior art cannot be further reduced because the distance between high-voltage NMOS devices cannot be continuously reduced.
Referring to fig. 1 and fig. 2, fig. 1 is a front view structural diagram of a circuit chip according to a first embodiment of the invention, fig. 2 is a top view structural diagram of the circuit chip according to the first embodiment of the invention, and the components and the relative position relationship of the components of the embodiment of the invention can be seen from the diagrams.
As shown in fig. 1 and fig. 2, the circuit chip 110 includes a substrate 111, a transistor circuit 112, and an isolation structure 113, wherein:
the transistor circuit 112 is formed on the front side of the substrate 111, and includes a plurality of transistor cells 1121 arranged on the substrate 111, and each transistor cell 1121 includes at least one transistor 11211;
the isolation structure 113 is located between the transistor cells 1121 for electrically isolating adjacent transistor cells 1121, and the isolation structure 113 includes:
a shallow trench isolation structure 1131 formed in the substrate 111;
the backside deep trench isolation structure 1132 is formed in the substrate 111, contacts the shallow trench isolation structure 1131, and extends to a backside of the circuit chip 110, wherein the backside of the circuit chip 110 is opposite to the front side of the substrate 111.
Further, the spacing between adjacent transistor cells 1121 is less than 0.5 microns.
Further, the transistors 11211 are high-voltage NMOS transistors, and the difference in bias voltage between adjacent transistors 11211 is 20V or more.
Further, the cross-sectional width of each of the backside deep trench isolation structures 1132 may be different parallel to the front side of the substrate 111, and the trench depth of each of the shallow trench isolation structures 1131 from the front side (i.e., the trench opening) of the substrate 111 to the bottom of the shallow trench isolation structure 1131 may also be different.
Further, the shallow trench isolation structure 1131 is located at the side of the source and the drain of the transistor cell 1121 to prevent premature breakdown between the active region of the transistor cell 1121 and the substrate 111.
Further, in this embodiment, the substrate 111 may be a silicon substrate, and the substrate 111 may include a P-type doped region 1111 and an N-type doped region 1112, wherein the P-type doped region 1111 is a common doped region of all the transistors 11211, the N-type doped region 1112 is a source/drain region of the transistor 11211, the source/drain electrode 112112 of the transistor 11211 is formed on the N-type doped region 1112, and the transistor 11211 further includes a gate electrode 112111 formed on the substrate 111.
As shown in fig. 2, the transistor cells 1121 are arranged in an array along the row and column directions, and the isolation structures 113 are formed between adjacent rows and adjacent columns of the transistor cells 1121.
Unlike the prior art, the present invention provides a circuit chip 110, including: a substrate 111; a transistor circuit 112 formed on the front side of the substrate 111, including a plurality of transistor cells 1121 arranged on the substrate 111; isolation structures 113 between the transistor cells 1121 to electrically isolate adjacent transistor cells 1121, the isolation structure 113 includes a shallow trench isolation structure 1131 and a backside deep trench isolation structure 1132 formed in the substrate 111, the backside deep trench isolation structure 1132 contacts the shallow trench isolation structure 1131, and extends to the backside of the circuit chip 110, wherein the backside of the circuit chip 110 is disposed opposite to the front side of the substrate 111, the circuit chip 110 provided by the present invention is formed by disposing the isolation structure 113 between the transistor units 1121, so that the circuit chip 110 will not punch through between the high voltage NMOS devices and the electrical property can be led out, the spacing between the high voltage NMOS devices can continue to shrink, thereby reducing the size of the circuit chip 110, and, because the circuit chip 110 under this structure does not need to be routed through the metal on the front surface, the problem of wire winding at the rear end of the circuit chip 110 is not caused.
Referring to fig. 3 and 4, fig. 3 is a schematic front view structure diagram of a circuit chip according to a second embodiment of the present invention, fig. 4 is a schematic top view structure diagram of the circuit chip according to the second embodiment of the present invention, and the components and the relative position relationship of the components according to the embodiment of the present invention can be seen from the diagrams.
As shown in fig. 3 and 4, the circuit chip 210 includes a substrate 211, a transistor circuit 212, an isolation structure 213, a lead-out structure 214, and a bottom metal layer 215, wherein:
the transistor circuit 212 is formed on the front side of the substrate 211, and includes a plurality of transistor cells 2121 arranged on the substrate 211, and each transistor cell 2121 includes at least one transistor 21211;
the isolation structure 213 is located between the transistor units 2121 and electrically isolates the adjacent transistor units 2121, and the isolation structure 213 includes a shallow trench isolation structure 2131 formed in the substrate 211 and a backside deep trench isolation structure 2132, the backside deep trench isolation structure 2132 contacts the shallow trench isolation structure 2131 and extends to a backside of the circuit chip 210, wherein the backside of the circuit chip 210 is opposite to the front side of the substrate 211;
the lead-out structure 214 is formed in the substrate 211, and one end of the lead-out structure 214 is in contact with the substrate 211 and the other end extends to the back side of the circuit chip 210;
the bottom metal layer 215 is formed on the back side of the circuit chip 210, and the bottom metal layer 215 contacts with the other end of the lead-out structure 214 for connecting to a control circuit outside the circuit chip 210.
Further, a dielectric layer 216 is formed on the back side of the substrate 211, and the other end of the lead-out structure 214 penetrates through the dielectric layer 216 and extends to the back side of the circuit chip 210.
Further, one end of the extraction structure 214 extends to the common doped region of the transistor cell 2121.
Further, in this embodiment, the substrate 211 may be a silicon substrate, and the substrate 211 may include a P-type doped region 2111 and an N-type doped region 2112, wherein the P-type doped region 2111 is a common doped region of all the transistors 21211, the N-type doped region 2112 is a source drain region of the transistor 21211, the source/drain electrode 212112 of the transistor 21211 is formed on the N-type doped region 2112, and the transistor 21211 further includes a gate electrode 212111 formed on the substrate 211.
Further, the spacing between adjacent transistor cells 2121 is less than 0.5 microns.
Further, the transistor 21211 is a high-voltage NMOS transistor, and the difference in bias voltage between adjacent transistors 21211 is 20V or more.
Further, the cross-sectional width of each backside deep trench isolation structure 2132 may be different on the front side parallel to the substrate 211, and the trench depth of each shallow trench isolation structure 2131 from the front side (i.e., the trench opening) of the substrate 211 to the bottom of the shallow trench isolation structure 2131 may also be different.
Further, the shallow trench isolation structure 2131 is located at the side of the source and the drain of the transistor unit 2121 to prevent premature breakdown between the active region of the transistor unit 2121 and the substrate 211.
Further, bottom metal layer 215 may be disposed within dielectric layer 216 such that the backside of bottom metal layer 215 is planar with the backside of dielectric layer 216.
As shown in fig. 4, the transistor cells 2121 are arranged in an array along the row and column directions, and the isolation structures 213 are formed between adjacent rows and adjacent columns of the transistor cells 2121.
Unlike the prior art, the present invention provides a circuit chip 210, comprising: a substrate 211; a transistor circuit 212 formed on the front side of the substrate 211, including a plurality of transistor cells 2121 arranged on the substrate 211; an isolation structure 213 located between the transistor cells 2121 for electrically isolating adjacent transistor cells 2121, the isolation structure 213 comprising a shallow trench isolation structure 2131 formed in the substrate 211 and a backside deep trench isolation structure 2132, the backside deep trench isolation structure 2132 contacting the shallow trench isolation structure 2131 and extending to a backside of the circuit chip 210, wherein the backside of the circuit chip 210 is disposed opposite to the front side of the substrate 211; a lead-out structure 214 formed in the substrate 211, one end of the lead-out structure 214 being in contact with the substrate 211 and the other end extending to the back side of the circuit chip 210; the circuit chip 210 provided by the present invention has the isolation structures 213 disposed between the transistor units 2121, the lead-out structure 214 disposed in the substrate 211, and the bottom metal layer 215 disposed on the back side of the circuit chip 210, so that the circuit chip 210 does not have punch-through between the high-voltage NMOS devices, and the electrical characteristics of the circuit chip can be led out, and the pitch between the high-voltage NMOS devices can be further reduced, thereby reducing the size of the circuit chip 210, and further, because the circuit chip 210 under this structure does not need to be wired by the metal on the front side, the wire winding problem at the back end of the circuit chip 210 is not caused.
Referring to fig. 5, fig. 5 is a schematic front view of a three-dimensional memory according to an embodiment of the invention, in which components and relative positions of the components can be visually seen.
As shown in fig. 5, the three-dimensional memory 100 includes a circuit chip 210 and a memory array chip 120, wherein the circuit chip 210 is bonded to the memory array chip 120 up and down and serves as a peripheral circuit of the memory array chip 120.
Although not shown in the drawings, the chip bonded to the memory array chip 120 and serving as the peripheral circuit in the three-dimensional memory 100 may be the circuit chip 110.
Referring to fig. 6, fig. 6 is a schematic flow chart illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present invention, which is described with reference to fig. 3 and 5.
As shown in fig. 3, 5 and 6, the method for manufacturing the three-dimensional memory specifically includes the steps of:
a substrate forming step S101. providing a substrate 211;
a transistor circuit forming step s102. providing a transistor circuit 212, the transistor circuit 212 being formed on the front side of the substrate 211, including a plurality of transistor cells 2121 arranged on the substrate 211;
a shallow trench isolation structure forming step S103, providing a shallow trench isolation structure 2131, wherein the shallow trench isolation structure 2131 is formed in the substrate 211;
a backside deep trench isolation structure forming step s104, providing a backside deep trench isolation structure 2132, where the backside deep trench isolation structure 2132 is formed in the substrate 211, contacts the shallow trench isolation structure 2131, and extends to a backside of the circuit chip 210, where the backside of the circuit chip 210 is opposite to the front side of the substrate 211, and the shallow trench isolation structure 2131 and the backside deep trench isolation structure 2132 form an isolation structure 213.
Specifically, in the process flow, the shallow trench isolation structure 2131 is formed before the transistor circuit 212.
Specifically, the shallow trench isolation structure 2131 is located at the side of the source and the drain of the transistor unit 2121 to avoid premature breakdown between the active region of the transistor unit 2121 and the substrate 211.
Further, before the backside deep trench isolation structure forming step S104, the method further includes:
the memory array chip 120 is provided, and the memory array chip 120 and the circuit chip 210 are connected by wafer bonding to form the three-dimensional memory 100.
Further, before the backside deep trench isolation structure forming step S104, a step of thinning the three-dimensional memory 100 is further included:
the substrate 211 of the circuit chip 210 is thinned.
Specifically, this step follows the step of "connecting the memory array chips 120 and the circuit chips 210 by wafer bonding to form the three-dimensional memory 100". And the thinning process may include one or more of a chemical mechanical polishing process (CMP), a wet etching process, and a dry etching process.
Further, after the step S104 of forming the backside deep trench isolation structure, a step of forming a dielectric layer 216 is further included:
a dielectric layer 216 is provided, the dielectric layer 216 being formed on the backside of the substrate 211.
Further, after the step of providing the dielectric layer 216, the step of forming the extraction structure 214 is further included:
an extraction structure 214 is provided, the extraction structure 214 is formed in the substrate 211, and one end of the extraction structure 214 is in contact with the substrate 211 and the other end extends to the back side of the circuit chip 210.
In particular, one end of the extraction structure 214 extends to a common doped region of the transistor cell 2121.
Specifically, in this embodiment, the substrate 211 may be a silicon substrate, and the substrate 211 may include a P-type doped region 2111 and an N-type doped region 2112, wherein the P-type doped region 2111 is a common doped region of all the transistors 21211, the N-type doped region 2112 is a source drain region of the transistor 21211, the source/drain electrode 212112 of the transistor 21211 is formed on the N-type doped region 2112, and the transistor 21211 further includes a gate electrode 212111 formed on the substrate 211.
Further, after the step of providing the lead-out structure 214, the step of forming a bottom metal layer 215 is further included:
a bottom metal layer 215 is provided, and the bottom metal layer 215 is formed on the back side of the circuit chip 210 and contacts with the other end of the lead-out structure 214 for connecting to the control circuit outside the circuit chip 210.
Specifically, bottom metal layer 215 may be disposed within dielectric layer 216 such that the backside of bottom metal layer 215 is planar with the backside of dielectric layer 216.
In addition to the above embodiments, the present invention may have other embodiments. All technical solutions formed by using equivalents or equivalent substitutions fall within the protection scope of the claims of the present invention.
In summary, although the preferred embodiments of the present invention have been described above, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.

Claims (14)

1. A circuit chip, comprising:
a substrate;
a transistor circuit formed on a front side of the substrate, including a plurality of transistor cells arranged on the substrate;
an isolation structure between the transistor cells for electrically isolating adjacent transistor cells, and comprising: a shallow trench isolation structure formed in the substrate, and; a backside deep trench isolation structure formed in the substrate and contacting the shallow trench isolation structure and extending to a backside of the circuit chip, wherein the backside of the circuit chip is disposed opposite the front side of the substrate.
2. The circuit chip of claim 1, wherein the transistor cells are arranged in an array along rows and columns, and the isolation structures are formed between adjacent rows and adjacent columns of the transistor cells.
3. The circuit chip of claim 1, wherein an extraction structure is further formed in the substrate, one end of the extraction structure being in contact with the substrate and the other end extending to the back side of the circuit chip.
4. The circuit chip of claim 3, wherein the one end of the extraction structure extends to a common doped region of the transistor cell.
5. The circuit chip of claim 3, wherein a bottom metal layer is further formed on the back side of the circuit chip, and the bottom metal layer contacts the other end of the lead structure for connecting to a control circuit outside the circuit chip.
6. The circuit chip of claim 1, wherein a spacing between adjacent transistor cells is less than 0.5 microns.
7. The circuit chip of claim 1, wherein the transistors are high voltage NMOS transistors, and a difference in bias voltage between adjacent transistors is 20V or more.
8. A three-dimensional memory comprising a memory array chip and a circuit chip bonded to the memory array chip up and down as a peripheral circuit according to any one of claims 1 to 7.
9. A method for preparing a three-dimensional memory is characterized by comprising the step of forming a circuit chip, and specifically comprises the following steps:
providing a substrate;
providing a transistor circuit formed on a front side of the substrate, comprising a plurality of transistor cells arranged on the substrate;
providing a shallow trench isolation structure formed in the substrate, and;
providing a backside deep trench isolation structure formed in the substrate and contacting the shallow trench isolation structure and extending to a backside of the circuit chip, wherein the backside of the circuit chip is disposed opposite the front side of the substrate and the shallow trench isolation structure and the backside deep trench isolation structure form an isolation structure.
10. The method of claim 9, further comprising, prior to the step of providing a backside deep trench isolation structure:
and providing a storage array chip, and connecting the storage array chip and the circuit chip in a wafer bonding mode to form the three-dimensional memory.
11. The method of claim 9, further comprising, prior to the step of providing a backside deep trench isolation structure:
and thinning the substrate.
12. The method of claim 9, further comprising, after the step of providing a backside deep trench isolation structure:
and providing an extraction structure, wherein the extraction structure is formed in the substrate, one end of the extraction structure is in contact with the substrate, and the other end of the extraction structure extends to the back side of the circuit chip.
13. The method of claim 12, wherein the one end of the extraction structure extends to a common doped region of the transistor cell.
14. The method of claim 12, further comprising, after the step of providing an extraction structure:
and providing a bottom metal layer, wherein the bottom metal layer is formed on the back side of the circuit chip, is in contact with the other end of the lead-out structure and is used for connecting a control circuit outside the circuit chip.
CN202010786389.2A 2020-08-07 2020-08-07 Circuit chip, three-dimensional memory and method for preparing three-dimensional memory Pending CN111968975A (en)

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