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CN111883506B - 电子封装件及其承载基板与制法 - Google Patents

电子封装件及其承载基板与制法 Download PDF

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Publication number
CN111883506B
CN111883506B CN201910728198.8A CN201910728198A CN111883506B CN 111883506 B CN111883506 B CN 111883506B CN 201910728198 A CN201910728198 A CN 201910728198A CN 111883506 B CN111883506 B CN 111883506B
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circuit
circuit member
circuit structure
carrier substrate
adjacent
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CN201910728198.8A
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CN111883506A (zh
Inventor
何祈庆
马伯豪
薛宇廷
曾景鸿
陆冠华
张宏达
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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Priority claimed from TW108126794A external-priority patent/TWI802726B/zh
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Abstract

本发明涉及一种电子封装件及其承载基板与制法，包括设置至少一线路构件于第一线路结构上，再形成包覆层于该第一线路结构上以包覆该线路构件，之后形成第二线路结构于该包覆层上，且令该第二线路结构电性连接该线路构件，以经由现有封装制程将该线路构件嵌埋于该包覆层中，以增加布线区，故对于大尺寸板面的封装基板的需求，不仅具有量产性且制程成本低。

Description

电子封装件及其承载基板与制法
技术领域
本发明有关一种封装结构，尤指一种电子封装件及其承载基板与制法。
背景技术
随着电子产品在功能及处理速度的需求的提升，作为电子产品的核心组件的半导体芯片需具有更高密度的线路构件(Electronic Components)及电子电路(ElectronicCircuits)，故半导体芯片在运行时将随之产生大量的热能，此外，包覆该半导体芯片的封装胶体为一种导热系数仅0.8Wm-1k-1的不良传热材料(即热量的逸散效率不佳)，因而若不能有效逸散所产生的热量，将会造成半导体芯片的损害或造成产品信赖性问题。
为了能迅速将热能散逸至大气中，业界通常在半导体封装结构中配置散热片(Heat Sink或Heat Spreader)，该散热片经由散热胶，如导热介面材(Thermal InterfaceMaterial，简称TIM)，结合至半导体芯片背面，以借散热胶与散热片逸散出半导体芯片所产生的热量，此外，通常令散热片的顶面外露出封装胶体或直接外露于大气中为佳，以取得较佳的散热效果。
如图1所示，现有半导体封装件1的制法为先将一半导体芯片11以其作用面11a利用覆晶接合方式(即通过导电凸块110与底胶111)设于一封装基板10上，再将一散热件13以其顶片130经由TIM层12(其包含焊锡层与助焊剂)回焊结合于该半导体芯片11的非作用面11b上，且该散热件13的支撑脚131经由粘着层14架设于该封装基板10上。接着，进行封装压模作业，以供封装胶体(图略)包覆该半导体芯片11及散热件13，并使该散热件13的顶片130外露出封装胶体而直接与大气接触。之后，将该半导体封装件1以其封装基板10经由多个焊球15接置于一电路板8上。
于运行时，该半导体芯片11所产生的热能经由该非作用面11b、TIM层12而传导至该散热件13的顶片130以散热至该半导体封装件1的外部。
然而，随着产业应用的发展，近年来逐渐朝着大尺寸封装规格的趋势进行研发，以应用于高密度线路/高传输速度/高叠层数/大尺寸设计的高阶产品。
然而，现有半导体封装件1中，对于大尺寸板面的封装基板10的需求，如板体尺寸100*100㎜2的需求，尚不具量产性，且单一板体的制作成本极高，因而不具市场竞争力。
因此，如何克服上述现有技术的种种问题，实已成为目前业界亟待克服的难题。
发明内容
鉴于上述现有技术的种种缺陷，本发明提供一种电子封装件及其承载基板与制法，可降低制作成本。
本发明的承载基板，包括：一第一线路结构，其具有相对的第一侧与第二侧；至少一线路构件，其设于该第一线路结构的第一侧上；以及一包覆层，其形成于该第一线路结构的第一侧上以包覆该线路构件。
本发明还提供一种承载基板的制法，包括：提供一具有相对的第一侧与第二侧的第一线路结构；设置至少一线路构件于该第一线路结构的第一侧上；以及形成包覆层于该第一线路结构的第一侧上，以令该包覆层包覆该线路构件。
前述的承载基板及其制法中，还包括形成第二线路结构于该包覆层上，且令该第二线路结构电性连接该线路构件。例如，该线路构件经由多个导电体电性连接该第二线路结构。又包括形成导电柱于该第一线路结构的第一侧上，以令该包覆层包覆该导电柱，且该导电柱电性连接该第一线路结构与第二线路结构。或者，可包括形成多个导电凸块于该第二线路结构上。
前述的承载基板及其制法中，该包覆层包覆至少四个该线路构件。
前述的承载基板及其制法中，该线路构件为封装基板。
前述的承载基板及其制法中，该线路构件为无核心层的线路结构。
前述的承载基板及其制法中，该线路构件具有硅穿孔结构。
前述的承载基板及其制法中，该线路构件经由多个导电体电性连接该第一线路结构。
本发明还提供一种电子封装件，包括：一前述的承载基板；以及至少一电子元件，其设于该承载基板的第一侧与第二侧的其中一者上。
本发明更提供一种电子封装件的制法，包括：提供一前述的承载基板；以及设置至少一电子元件于该承载基板的第一侧与第二侧的其中一者上。
前述的电子封装件及其制法中，该电子元件为主动元件、被动元件或其二者组合。
前述的电子封装件及其制法中，还包括形成多个导电元件于该承载基板的第一侧与第二侧中未设有该电子元件之者上。
前述的电子封装件及其制法中，还包括配置散热件于该承载基板上。例如，该散热件接触该电子元件。
由上可知，本发明的电子封装件及其承载基板与制法中，主要经由将线路构件设置于第一线路结构上并嵌埋于包覆层中，以增加布线区，故相比于现有技术，对于大尺寸板面的封装基板的需求，本发明不仅具有量产性，且单一承载基板的制作成本极低，因而极具市场竞争力。
此外，该线路结构用于调配该线路构件的布线层数，使该线路构件的布线层数降低，以提高该线路构件的制作良率。
附图说明
图1为现有半导体封装件的剖视示意图。
图2A至图2E为本发明的承载基板的制法的第一实施例的剖视示意图。
图2F至图2G为本发明的电子封装件的制法的第一实施例的剖视示意图。
图2G’为图2G的另一实施例的剖视示意图。
图2G”为图2E的另一实施例的剖视示意图。
图3A至图3B为本发明的承载基板的制法的第二实施例的剖视示意图。
图3C至图3D为本发明的电子封装件的制法的第二实施例的剖视示意图。
符号说明
1 半导体封装件 10 封装基板
11 半导体芯片 11a,30a 作用面
11b,30b 非作用面 110,29 导电凸块
111,33 底胶 12 TIM层
13,3a 散热件 130 顶片
131,31 支撑脚 14,91,310 粘着层
15 焊球 2,2’,2”,3a 承载基板
2a 线路板块 20 第一线路结构
20a 第一侧 20b 第二侧
200 第一绝缘层 201,201’ 第一线路重布层
21 线路构件 21a 顶面
21b 底面 210 线路层
211 绝缘体 212 保护膜
213 电性接触垫 22,22’ 导电体
22a,23a 端面 23 导电柱
24 结合层 25 包覆层
26 第二线路结构 260 第二绝缘层
261 第二线路重布层 27 导电元件
28 绝缘保护层 290 凸块底下金属层
3,3’ 电子封装件 30 电子元件
300 电极垫 32 散热体
320 导热介面层 4 电子装置
8 电路板 9 承载板
90 离型层 S 切割路径。
具体实施方式
以下经由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等的用语，也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2E为本发明的承载基板2的制法的第一实施例的剖面示意图。
如图2A所示，提供一线路板块2a，其包含多个线路构件21。
于本实施例中，该线路构件21为如具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构(图中为呈现coreless型)，其具有绝缘体211及结合该绝缘体211的多个线路层210，如扇出(fan out)型重布线路层(redistribution layer，简称RDL)，且形成该绝缘体211的材料为如聚对二唑苯(Polybenzoxazole，简称PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材；或者，该线路构件21可具有硅穿孔(Through Silicon Via，简称TSV)结构。应可理解地，该线路构件21也可为其它配置布线的板体，如有机板材(organicmaterial)、半导体板材(silicon)、陶瓷板材(ceramic)或其它具有金属布线(routing)的载板，并不限于上述。
此外，该线路构件21上结合并电性连接多个导电体22，且该导电体22为如导电线路、焊球的圆球状、或如铜柱、焊锡凸块等金属材的柱状、或焊线机制作的钉状(stud)，但不限于此。另外，该线路构件21的顶面21a可形成有一如钝化材的保护膜212，以令部分线路层210(如多个电性接触垫213)外露出该保护膜212，且该导电体22形成于该电性接触垫213上并凸出该保护膜212。
如图2B所示，切割该线路板块2a以获取多个线路构件21，再将一个或多个(如图所示的四个以上)线路构件21设于一第一线路结构20上，其中，该第一线路结构20形成于承载板9上且具有相对的第一侧20a与第二侧20b，该第一线路结构20以其第二侧20b结合至该承载板9上，而该线路构件21设于该第一线路结构20的第一侧20a上。另一方面，于该第一线路结构20的第一侧20a上也形成多个电性连接该第一线路结构20的导电柱23，其中，该线路构件21与该导电柱23的设置顺序可依需求选择先后顺序。
于本实施例中，该第一线路结构20包括至少一第一绝缘层200与设于该第一绝缘层200上的第一线路重布层(RDL)201。例如，形成该第一线路重布层201的材料为铜，且形成该第一绝缘层200的材料为如聚对二唑苯(PBO)、聚酰亚胺(PI)、预浸材(PP)或其它等的介电材。
此外，该承载板9例如为半导体材料(如硅或玻璃)的圆形板体，其上以涂布方式依序形成有一离型层90与一粘着层91，以供该第一线路结构20设于该粘着层91上。
又，该导电柱23设于该第一线路重布层201上并电性连接该第一线路重布层201，且形成该导电柱23的材料为如铜的金属材或焊锡材。
另外，该线路构件21以其底面21b经由一如胶材的结合层24粘固于该第一线路结构20的第一侧20a上。
如图2C所示，形成一包覆层25于该第一线路结构20的第一侧20a上，以令该包覆层25包覆该线路构件21、结合层24、该多个导电体22与该多个导电柱23，再经由整平制程，令该导电柱23的端面23a与该导电体22的端面22a外露于该包覆层25，使该包覆层25的外表面齐平该导电柱23的端面23a与该导电体22的端面22a。
于本实施例中，该包覆层25为绝缘材，如环氧树脂的封装胶体，其可用压合(lamination)或模压(molding)的方式形成于该第一线路结构20的第一侧20a上。
此外，该整平制程经由研磨方式，移除该导电柱23的部分材料、该导电体22的部分材料与该包覆层25的部分材料。
如图2D所示，形成一第二线路结构26于该包覆层25上，且该第二线路结构26电性连接该导电柱23与该导电体22。
于本实施例中，该第二线路结构26包括多个第二绝缘层260、及设于该第二绝缘层260上的多个第二线路重布层(RDL)261，且最外层的第二绝缘层260可作为防焊层，以令最外层的第二线路重布层261外露于该防焊层。或者，该第二线路结构26也可仅包括单一第二绝缘层260及单一第二线路重布层261。
此外，形成该第二线路重布层261的材料为铜，且形成该第二绝缘层260的材料为如聚对二唑苯(PBO)、聚酰亚胺(Polyimide，简称PI)、预浸材(Prepreg，简称PP)或其它等的介电材。
如图2E所示，移除该承载板9及其上的离型层90与粘着层91，以外露该第一线路结构20，进而形成本发明的承载基板2。
因此，本发明的承载基板2的制法中，主要经由现有封装制程将该线路构件21嵌埋于该包覆层25中，以增加布线区，故相比于现有技术，对于大尺寸板面的封装基板的需求，本发明的承载基板2的制法不仅具有量产性，且单一承载基板2的制作成本极低，因而极具市场竞争力。
此外，该第一线路结构20(或该第二线路结构26)用于调配该线路构件21的布线层数，使该线路构件21的布线层数降低，以提高该线路构件21的制作良率。
如图2F所示，该承载基板2可于最外层的第二线路重布层261上接置一个或多个电子元件30，以形成电子封装件3，另该承载基板2可于该第一线路结构20的第二侧20b上形成多个如焊球的导电元件27。
于本实施例中，可形成一如防焊层的绝缘保护层28于该第一线路结构20的第二侧20b上，且形成多个开孔于该绝缘保护层28上，以令该第一线路重布层201外露于该多个开孔，以供结合多个该导电元件27。
此外，该电子元件30为主动元件、被动元件或其二者组合等，其中，该主动元件例如为半导体芯片，且该被动元件为例如电阻、电容及电感。例如，该电子元件30为半导体芯片，其具有相对的作用面30a与非作用面30b，且以其作用面30a的电极垫300经由多个如焊锡材料的导电凸块29采用覆晶方式设于该第二线路重布层261上并电性连接该第二线路重布层261，且以底胶33包覆该导电凸块29；或者，该电子元件30以其非作用面30b设于该该第二线路结构26上，并可经由多个焊线(图略)以打线方式电性连接该第二线路重布层261；亦或通过如导电胶或焊锡等导电材料(图略)电性连接该第二线路重布层261。然而，有关该电子元件30电性连接该第二线路重布层261的方式不限于上述。
另外，可形成一凸块底下金属层(Under Bump Metallurgy，简称UBM)290于最外层的第二线路重布层261上，以利于结合该导电凸块29。
如图2G所示，沿如图2F所示的切割路径S进行切单制程，以令该承载基板2于后续制程中经由该导电元件27接置于一如封装结构或如电路板的电子装置4上。
于本实施例中，该电子封装件3可依需求配置一散热件3a，其包含有支撑脚31及散热体32，且以其支撑脚31经由粘着层310结合于该第二线路结构26上，并使该散热件3a的散热体32经由导热介面层320结合该电子元件30。例如，多个支撑脚31为一体成形于该散热体32上；或者，多个支撑脚31也可以接合方式设于该散热体32上。
此外，该导热介面层320也可先形成于该散热体32上，再将该散热体32以该导热介面层320结合至该电子元件30的非作用面30b上。同理地，该粘着层310也可先形成于该支撑脚31上，再将该支撑脚31经由该粘着层310结合至该第二线路结构26上。
又，为了提升该导热介面层320与该电子元件30之间的接着强度，可于该电子元件30的表面上覆金(即所谓的Coating Gold On Chip Back)。具体地，于该电子元件30的非作用面30b与该散热体32的表面上形成一金层，且进一步配合助焊剂(flux)，以利于该导热介面层320接着于该金层上。
另外，于其它实施例中，该承载基板2’可省略该导电柱23的制作，如图2G’所示。或者，如图2G”所示的承载基板2”，该线路构件21于相对两侧上均结合并电性连接多个导电体22,22’，且其中一侧的导电体22电性连接该第二线路结构26，而另一侧的导电体22’电性连接该第一线路结构20的第一线路重布层201’。
图3A至图3B为本发明的承载基板3a的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于省略第二线路结构的制程，其它制程大致相同，故以下不再赘述相同处。
如图3A所示，采用图2G”所示的线路构件21进行图2A至图2C所示的制程，包括：提供多个线路构件21，各该线路构件21于相对两侧上均结合并电性连接多个导电体22,22’，将多个线路构件21及多个导电柱23电性连接至位于承载板9上的第一线路结构20，接着形成包覆层25并进行整平制程。
如图3B所示，移除该承载板9及其上的离型层90与粘着层91，以外露该第一线路结构20的第二侧20b，进而形成本发明的承载基板3a。
因此，本发明的承载基板3a的制法中，主要经由现有封装制程将该线路构件21嵌埋于该包覆层25中，以增加布线区，故相比于现有技术，对于大尺寸板面的封装基板的需求，本发明的承载基板3a的制法不仅具有量产性，且单一承载基板3a的制作成本极低，因而极具市场竞争力。
此外，该第一线路结构20用于调配该线路构件21的布线层数，使该线路构件21的布线层数降低，以提高该线路构件21的制作良率。
如图3C所示，该承载基板3a可于该第一线路结构20的第二侧20b的第一线路重布层201上接置一个或多个电子元件30，另该承载基板3a可于该线路构件21上经由该些导电体22结合多个如焊球的导电元件27，以令该承载基板3a于后续制程中经由该些导电元件27接置于一如图2G所示的电子装置4上。
如图3D所示，沿如图3C所示的切割路径S进行切单制程，以获取电子封装件3’。
本发明还提供一种电子封装件3,3’，包括一承载基板2,2’,2”,3a以及至少一设于该承载基板2,2’,2”,3a其中一侧上的电子元件30，其中，该承载基板2,2’,2”,3a包括：一第一线路结构20、一线路构件21以及一包覆层25。
所述的第一线路结构20具有相对的第一侧20a与第二侧20b，该第一侧20a上可依需求形成有多个导电柱23，且该导电柱23电性连接该第一线路结构20。
所述的线路构件21设于该第一线路结构20的第一侧20a上，且该线路构件21上结合并电性连接多个导电体22,22’。
所述的包覆层25形成于该第一线路结构20的第一侧20a上，以令该包覆层25包覆该线路构件21、该导电体22,22’与该导电柱23，且令该导电柱23的端面23a与该导电体22的端面22a外露于该包覆层25。
于一实施例中，该线路构件21经由多个导电体22’电性连接该第一线路结构20。
于一实施例中，所述的电子封装件3,3’还包括多个导电元件27，形成于该承载基板2,2’,2”,3a的另一侧上。
于一实施例中，所述的承载基板2,2’,2”还包括第二线路结构26，其形成于该包覆层25上，且该第二线路结构26电性连接该导电柱23，并经由该导电体22电性连接该线路构件21。又包括形成于该第二线路结构26上的多个导电凸块29。
于一实施例中，该电子元件30为主动元件、被动元件或其二者组合。
于一实施例中，所述的电子封装件3还包括一配置于该第二线路结构26上的散热件3a。例如，该散热件3a接触该电子元件30。
综上所述，本发明的电子封装件及其承载基板与制法中，经由现有封装制程将线路构件设置于第一线路结构上并嵌埋于包覆层中，以增加布线区，故对于大尺寸板面的封装基板的需求，本发明的承载基板不仅具有量产性，且单一承载基板的制作成本极低，因而极具市场竞争力。
此外，该线路结构可用于调配该线路构件的布线层数，使该线路构件的布线层数降低，进而提升该线路构件的制作良率。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (26)

1.一种承载基板，其特征在于，包括：
一第一线路结构，其具有相对的第一侧与第二侧；
相邻的第一线路构件与第二线路构件，其分别经由相邻的绝缘的第一结合层与第二结合层设于该第一线路结构的第一侧上，其中，该第一线路构件与该第二线路构件为封装基板或无核心层的线路结构，该第一结合层位于该第一线路结构与该第一线路构件之间，该第二结合层位于该第一线路结构与该第二线路构件之间，且相邻的该第一线路构件与该第二线路构件皆未直接接触该第一线路结构的第一侧；
一包覆层，其形成于该第一线路结构的第一侧上、相邻的该第一线路构件与该第二线路构件两者之间及相邻的该第一结合层与该第二结合层两者之间以包覆该第一线路构件、该第二线路构件、该第一结合层与该第二结合层；以及
第一导电柱与第二导电柱，其分别形成于该包覆层中，且相邻的该第一线路构件与该第二线路构件及相邻的该第一结合层与该第二结合层皆位于该第一导电柱与该第二导电柱之间。
2.根据权利要求1所述的承载基板，其特征在于，该承载基板还包括一第二线路结构，其形成于该包覆层上且电性连接该第一线路构件或该第二线路构件。
3.根据权利要求2所述的承载基板，其特征在于，该第一线路构件或该第二线路构件经由多个导电体电性连接该第二线路结构。
4.根据权利要求2所述的承载基板，其特征在于，该第一导电柱与该第二导电柱皆电性连接该第一线路结构与第二线路结构。
5.根据权利要求2所述的承载基板，其特征在于，该承载基板还包括形成于该第二线路结构上的多个导电凸块。
6.根据权利要求1所述的承载基板，其特征在于，该包覆层包覆四个相邻的该第一线路构件、该第二线路构件、一第三线路构件与一第四线路构件。
7.根据权利要求1所述的承载基板，其特征在于，该第一线路构件或该第二线路构件具有硅穿孔结构。
8.根据权利要求1所述的承载基板，其特征在于，该承载基板还包括保护膜，其形成于该第一线路构件或该第二线路构件的顶面上。
9.一种电子封装件，其特征在于，包括：
一根据权利要求1至8中任一项所述的承载基板；以及
至少一电子元件，其设于该承载基板的第一侧与第二侧的其中一者上。
10.根据权利要求9所述的电子封装件，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
11.根据权利要求9所述的电子封装件，其特征在于，该电子封装件还包括多个导电元件，其设于该承载基板的第一侧与第二侧中未设有该电子元件之者上。
12.根据权利要求9所述的电子封装件，其特征在于，该电子封装件还包括配置于该承载基板上的散热件。
13.根据权利要求12所述的电子封装件，其特征在于，该散热件接触该电子元件。
14.一种承载基板的制法，其特征在于，包括：
提供一具有相对的第一侧与第二侧的第一线路结构；
将相邻的第一线路构件与第二线路构件分别经由相邻的绝缘的第一结合层与第二结合层设于该第一线路结构的第一侧上，其中，该第一线路构件与该第二线路构件为封装基板或无核心层的线路结构，该第一结合层位于该第一线路结构与该第一线路构件之间，该第二结合层位于该第一线路结构与该第二线路构件之间，且相邻的该第一线路构件与该第二线路构件皆未直接接触该第一线路结构的第一侧；以及
形成包覆层于该第一线路结构的第一侧上、相邻的该第一线路构件与该第二线路构件两者之间及相邻的该第一结合层与该第二结合层两者之间，以令该包覆层包覆该第一线路构件、该第二线路构件、该第一结合层与该第二结合层，其中，该包覆层中分别形成有第一导电柱与第二导电柱，且相邻的该第一线路构件与该第二线路构件及相邻的该第一结合层与该第二结合层皆位于该第一导电柱与该第二导电柱之间。
15.根据权利要求14所述的承载基板的制法，其特征在于，该制法还包括形成第二线路结构于该包覆层上，且令该第二线路结构电性连接该第一线路构件或该第二线路构件。
16.根据权利要求15所述的承载基板的制法，其特征在于，该第一线路构件或该第二线路构件经由多个导电体电性连接该第二线路结构。
17.根据权利要求15所述的承载基板的制法，其特征在于，该第一导电柱与该第二导电柱分别形成于该第一线路结构的第一侧上，且该第一导电柱与该第二导电柱皆电性连接该第一线路结构与第二线路结构。
18.根据权利要求15所述的承载基板的制法，其特征在于，该制法还包括形成多个导电凸块于该第二线路结构上。
19.根据权利要求14所述的承载基板的制法，其特征在于，该包覆层包覆四个相邻的该第一线路构件、该第二线路构件、一第三线路构件与一第四线路构件。
20.根据权利要求14所述的承载基板的制法，其特征在于，该第一线路构件或该第二线路构件具有硅穿孔结构。
21.根据权利要求14所述的承载基板的制法，其特征在于，该制法还包括形成保护膜于该第一线路构件或该第二线路构件的顶面上。
22.一种电子封装件的制法，其特征在于，包括：
提供一根据权利要求1至8中任一项所述的承载基板；以及
设置至少一电子元件于该承载基板的第一侧与第二侧的其中一者上。
23.根据权利要求22所述的电子封装件的制法，其特征在于，该电子元件为主动元件、被动元件或其二者组合。
24.根据权利要求22所述的电子封装件的制法，其特征在于，该制法还包括形成多个导电元件于该承载基板的第一侧与第二侧中未设有该电子元件之者上。
25.根据权利要求22所述的电子封装件的制法，其特征在于，该制法还包括配置散热件于该承载基板上。
26.根据权利要求25所述的电子封装件的制法，其特征在于，该散热件接触该电子元件。
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