CN111752327A - Ramp voltage generator and ramp voltage generation method - Google Patents
Ramp voltage generator and ramp voltage generation method Download PDFInfo
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- CN111752327A CN111752327A CN202010561158.1A CN202010561158A CN111752327A CN 111752327 A CN111752327 A CN 111752327A CN 202010561158 A CN202010561158 A CN 202010561158A CN 111752327 A CN111752327 A CN 111752327A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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Abstract
The invention relates to the field of integrated circuits, and discloses a ramp voltage generator and a ramp voltage generation method, which comprise the following steps: v of active capacitorAEnd connected to voltage input end, V of active capacitorBThe end is grounded, and a first charging circuit used for charging the active capacitor to the reference voltage is formed between the voltage input end and the active capacitor; v of active capacitorAThe end of the active capacitor is connected with one end of an integrating capacitor for outputting voltage and the positive input end of an operational Amplifier (AMP) in sequence, the other end of the integrating capacitor is grounded, and the V of the active capacitorBThe ends of the input signal are sequentially connected to the output V of the operational amplifier AMPpA negative input end of the operational amplifier AMP and a terminal, wherein the active capacitor and the operational amplifier AMP form a second charging circuit for distributing charges to the integrating capacitor; the control signal generating circuit is used for enabling the first charging circuit and the second charging circuit to be conducted alternately to charge the integrating capacitor so that the voltage of the integrating capacitor reaches the target voltage required by an output user. The invention can generate ramp voltage with high linearity.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a ramp voltage generator and a ramp voltage generating method.
Background
The voltage ramp signal may be used in a circuit requiring a linear change in voltage, and is typically used as a reference signal, a slope compensator, or a voltage sweep generator. The ramp voltage generator can be used in a display device or a signal conversion situation, and generally comprises an integrator formed by an operational amplifier, and can perform mathematical operation of integration, that is, the output voltage can be made to respond to the change of the input voltage along with time, and the principle is that the output voltage generated by the integrator formed by the operational amplifier is proportional to the integral of the input voltage.
The following description is made in conjunction with two amplifier integration circuits. FIG. 1 shows a conventional operational amplifier integrator circuit, as shown in FIG. 1, in which a feedback capacitor C starts to charge due to the influence of an input voltage and has an impedance XcSlowly increasing in proportion to its charge rate. The capacitor charges at a rate determined by the RC time constant of the RC series network, and the negative feedback forces the operational amplifier A to produce an output voltage-VoutThe voltage V generated across the capacitor C is maintained at a virtual ground at the inverting input of the operational amplifiercSlowly increases, resulting in a charging current IfDecreasing with increasing capacitor impedance. This results in Xc/Rin(RinThe resistance value of a resistor that is an RC series network) increases, producing a linearly increasing ramped output voltage that continues to increase until the capacitor is fully charged. When the capacitor is fully charged, the capacitor acts as an open circuit, blocking any further direct current. The ratio of the feedback capacitance C to the input resistance R is now infinite, resulting in infinite gain. The result of this high gain is that the output of the amplifier goes into saturation. Fig. 2 is a circuit diagram of another integration circuit, and the integration circuit of fig. 2 includes a high-gain operational amplifier a, a high-speed MOS switch, and an integration capacitor C. The Reset signal Reset controls the MOS switch to determine the operation range of the ramp voltage. The slope of the ramp voltage is determined by the reference current and the capacitanceAnd (4) determining. In the actual Reset signal generation system in the integration circuit of fig. 2, the high gain operational amplifier used is not an ideal device, and when the Reset signal Reset is generated, the linearity of the ramp voltage is not good due to the influence of the production process, the power supply, the voltage and the temperature, and the output ramp voltage range has an amplitude limitation, so that it is difficult to achieve the precision required by the design in the application.
Disclosure of Invention
The invention aims to provide a ramp voltage generator and a ramp voltage generation method, which can generate a ramp voltage with high linearity.
In order to achieve the above object, the present invention provides a ramp voltage generator, comprising: the circuit comprises a switch group, an operational Amplifier (AMP), an active capacitor, an integral capacitor and a control signal generating circuit; wherein V of the active capacitorAEnd connected to voltage input end, V of the active capacitorBThe voltage input end and the active capacitor form a first charging circuit used for charging the active capacitor to a reference voltage; v of the active capacitorAThe end of the integrating capacitor is connected with one end of the integrating capacitor for generating output voltage and the positive input end of the operational amplifier AMP in sequence, the other end of the integrating capacitor is grounded, and the V of the active capacitor is connected with the groundBThe end is connected with the output V of the operational amplifier AMP in sequencepA negative input terminal of the operational amplifier AMP and a terminal, wherein the active capacitor and the operational amplifier AMP form a second charging circuit for distributing charges to the integrating capacitor; the control signal generating circuit is used for generating a control signal, wherein the control signal is configured to control the switch groups arranged in the first charging circuit and the second charging circuit to be switched on or switched off, so that the first charging circuit and the second charging circuit are alternately switched on to charge the integrating capacitor to enable the voltage of the integrating capacitor to reach a target voltage required by an output user.
Preferably, the switch block includes: a first switch, a second switch, a third switch and a fourth switch; wherein the first switch is arranged atV of the active capacitorABetween the terminal and the voltage input terminal, the second switch is arranged at V of the active capacitorBThe third switch is arranged between the end and the ground and is arranged at V of the active capacitorABetween the end and the integrating capacitor, the fourth switch is arranged at V of the active capacitorBTerminal and output V of the operational amplifier AMPpBetween the ends.
Preferably, the control signal generating circuit includes: a clock circuit for generating non-overlapping clock signals and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signals; the clock circuit receives a CLK clock signal and sends the non-overlapping clock signal to the first switch, the second switch and the timing adjustment circuit, and the timing adjustment circuit sends the non-overlapping clock signal with the adjusted timing to the third switch and the fourth switch.
Preferably, at least one of the first switch, the second switch, the third switch and the fourth switch is composed of a PMOS transistor; or at least one of the first switch, the second switch, the third switch and the fourth switch is composed of an NMOS tube.
Preferably, the voltage input terminal is configured to input a reference voltage, wherein the reference voltage is less than a target voltage for outputting a user demand.
In addition, an integrated circuit is also provided, and the integrated circuit comprises the ramp voltage generator.
In addition, a ramp voltage generation method is provided, the ramp voltage generation method uses the ramp voltage generator, and the ramp voltage generation method includes: in an integration period, controlling a switch set in the first charging circuit to be turned on and a switch set in the second charging circuit to be turned off so that the voltage of the active capacitor reaches a reference voltage reflecting the change rate of the voltage required by a user, and continuously controlling the switch set in the first charging circuit to be turned off and the switch set in the second charging circuit to be turned on based on the reference voltage so as to charge all the charges on the active capacitor to the integration capacitor; and repeating a plurality of the integration periods to enable the voltage of the integration capacitor to reach a target voltage of an output user demand, wherein the target voltage is larger than the reference voltage.
According to the technical scheme, the first charging circuit and the second charging circuit are controlled to be switched on or switched off by using a designed switch group, wherein when the first charging circuit is switched on, the active capacitor can store reference voltage, and when the second charging circuit is switched on, the active capacitor can be matched with the integrating capacitor and the operational Amplifier (AMP) to distribute the charge on the active capacitor to the integrating capacitor, so that the voltage of the integrating capacitor reaches the target voltage required by an output user. The control circuit overcomes the defects of insufficient linearity and easy saturation of output voltage of the traditional integrating circuit, and can keep better linearity within the range of target voltage.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a prior art integrating circuit diagram of an operational amplifier;
FIG. 2 is a prior art integration circuit diagram of another operational amplifier;
FIG. 3 is a circuit diagram illustrating a ramp voltage generator of the present invention;
FIG. 4 is a circuit diagram illustrating one embodiment of a ramp voltage generator of the present invention;
FIG. 5 is a timing diagram illustrating the control timing of the control signals of the switch block of the present invention;
FIG. 6 is a simulated output waveform illustrating the ramp voltage of the present invention; and
fig. 7 is a flow chart illustrating a ramp voltage generation method of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present invention, are given by way of illustration and explanation only, not limitation.
Fig. 1-2 are prior art operational amplifier integrating circuits for generating the ramp voltage shown in fig. 3. The operational amplifier integrated circuits of fig. 1 and 2 of the present invention have great differences in either structure or control principle. The ramp voltage generator of the present invention is described in detail below with reference to fig. 3-6.
Fig. 3 is a circuit diagram of a ramp voltage generator of the present invention, as shown in fig. 3, the ramp voltage generator comprising: a switch group (the switch group comprises 4 switches), an operational amplifier AMP, an active capacitor C0, an integrating capacitor C1 and a control signal generating circuit; the control signal generating circuit outputs signals for controlling the switches S1, S2, S3 and S4. Wherein V of the active capacitor C0AEnd connected to voltage input end VR, V of active capacitor C0BThe voltage input end VR and the active capacitor C0 form a first charging circuit for charging the active capacitor C0 to a reference voltage; v of the active capacitor C0AThe terminals of the integrating capacitor C1 are connected to one terminal of the integrating capacitor C1 for generating an output voltage and the positive input terminal of the operational amplifier AMP in sequence, the other terminal of the integrating capacitor C1 is grounded, and V of the active capacitor C0 is set to be VBThe end is connected with the output V of the operational amplifier AMP in sequencepA terminal and a negative input terminal of the operational amplifier AMP, the active capacitor C0 and the operational amplifier AMP forming a second charging circuit for distributing charge to the integrating capacitor C1; the control signal generating circuit is used for generating a control signal, wherein the control signal is configured to be used for controlling the switch groups arranged in the first charging circuit and the second charging circuit to be switched on or switched off, so that the first charging circuit and the second charging circuit are alternately switched on to charge the integrating capacitor to enable the voltage of the integrating capacitor to reach a target voltage showing user requirements. Wherein the voltage input is configured to input a reference voltage that is less than an output userThe required target voltage VDD.
Wherein, as shown in fig. 3, the switch group includes: a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4; wherein the first switch S1 is placed at V of the active capacitor C0ABetween terminal and the voltage input terminal VR, the second switch S2 is placed at V of the active capacitor C0BBetween terminal and ground, the third switch S3 is placed at V of the active capacitor C0ABetween terminal and the integrating capacitor C1, the fourth switch S4 is placed at V of the active capacitor C0BTerminal and output V of the operational amplifier AMPpBetween the ends.
Further preferably, fig. 4 is a circuit diagram of another ramp voltage generator according to the present invention, and fig. 5 adds a control signal generating circuit and a specific structure of a switch group to the circuit diagram of fig. 4, wherein the first switch, the second switch, the third switch and the fourth switch are all composed of PMOS transistors and/or NMOS transistors. As shown in fig. 4, the transistor M1 constitutes a first switch S1; the transistors M2, M3 constitute a second switch S2; the transistors M4, M5 constitute a third switch S3; the transistors M6, M7 constitute a fourth switch S4, and U0 is an operational amplifier AMP. Wherein the control signal generating circuit includes: a clock circuit for generating non-overlapping clock signals and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signals; wherein the clock circuit receives a CLK clock signal and sends the non-overlap clock signal to the first switch S1, the second switch S2, and the timing adjustment circuit sends the timing-adjusted non-overlap clock signal to the third switch S3 and the fourth switch S4.
Fig. 5 is a timing diagram of the control signal generated by the control signal generating circuit. As shown in fig. 6, the first switch S1 and the second switch S2 may be synchronously opened at a high level, the third switch S3 and the fourth switch S4 may be synchronously opened at a high level, and S1 and S2 are alternately opened with S3 and S4.
Fig. 6 is a simulated output waveform illustrating the ramp voltage of the present invention. As shown in fig. 7, the output voltage range of the ramp voltage generator can reach 0V to VDD, which can be adjusted by the input reference voltage VR, and the circuit has good linearity in the output voltage range, and is suitable for many occasions with high requirements on the output voltage range and linearity.
Fig. 7 is a flow chart illustrating a ramp voltage generation method using the ramp voltage generator of fig. 4 or 5 according to the present invention. As shown in fig. 7, the ramp voltage generation method includes:
step1, in one integration period, executing:
the first stage is as follows: controlling a switch set arranged in the first charging circuit to be switched on and a switch set arranged in the second charging circuit to be switched off so that the voltage of the active capacitor reaches a reference voltage reflecting the voltage change rate required by a user; and
and a second stage: and continuously controlling the switch group in the first charging circuit to be switched off and the switch group in the second charging circuit to be switched on based on the reference voltage so as to charge all the charges on the active capacitor to the integrating capacitor.
Step2, repeating a plurality of the integration periods, so that the voltage of the integration capacitor reaches the target voltage generating the user demand. Wherein the target voltage is greater than the reference voltage.
Specifically, in the first stage of operation in Step1, S1 and S2 are closed, S3 and S4 are opened, and V is setAPotential at point is VR，VBThe voltage at the node is GND (0V), and the voltage of the active capacitor C0 is charged to VR(ii) a In the second stage, S1 and S2 are open, S3 and S4 are closed, and the potential at VB is VPI.e. VOUTPotential of (V)AThe potential at the point is (V)OUT+VR) Greater than VOUTAt this time, the charge of the active capacitor C0 flows to the integrating capacitor C1.
In Step2, S1-S4 complete the charging and charge distribution operation for a plurality of cycles under the control of the clock CLK. Terminal voltage V of integrating capacitor C1OUTGradually increases from the initial 0V and finally reaches (V)OUT+VR). In this process, the amount of charge of the active capacitor C0 is fixed,the change process of the charging voltage of the integrating capacitor C1 is close to linear, and the output range can reach the full voltage range, namely 0V-VDD.
In addition, the invention also provides an integrated circuit which comprises the ramp voltage generator described in fig. 3 and fig. 4.
The preferred embodiments of the present invention have been described in detail with reference to the accompanying drawings, however, the present invention is not limited to the specific details of the above embodiments, and various simple modifications can be made to the technical solution of the present invention within the technical idea of the present invention, and these simple modifications are within the protective scope of the present invention.
It should be noted that the various technical features described in the above embodiments can be combined in any suitable manner without contradiction, and the invention is not described in any way for the possible combinations in order to avoid unnecessary repetition.
In addition, any combination of the various embodiments of the present invention is also possible, and the same should be considered as the disclosure of the present invention as long as it does not depart from the spirit of the present invention.
Claims (7)
1. A ramp voltage generator, comprising: the circuit comprises a switch group, an operational Amplifier (AMP), an active capacitor, an integral capacitor and a control signal generating circuit;
wherein V of the active capacitorAEnd connected to voltage input end, V of the active capacitorBThe voltage input end and the active capacitor form a first charging circuit used for charging the active capacitor to a reference voltage;
v of the active capacitorAThe end of the active capacitor is connected with one end of the integrating capacitor for outputting voltage and the positive input end of the operational amplifier AMP in sequence, the other end of the integrating capacitor is grounded, and the V of the active capacitor is connected with the groundBThe end is connected with the output V of the operational amplifier AMP in sequencepA terminal and a negative input terminal of the operational amplifier AMP, the active capacitor and the operational amplifier AMP being formed with a capacitor for providing the integrating capacitorA second charging circuit for distributing electric charge;
the control signal generating circuit is used for generating a control signal, wherein the control signal is configured to control the switch groups arranged in the first charging circuit and the second charging circuit to be switched on or switched off, so that the first charging circuit and the second charging circuit are alternately switched on to charge the integrating capacitor to enable the voltage of the integrating capacitor to reach a target voltage required by an output user.
2. The ramp voltage generator of claim 1, wherein the switch bank comprises: a first switch, a second switch, a third switch and a fourth switch;
wherein the first switch is placed at V of the active capacitorABetween the terminal and the voltage input terminal, the second switch is arranged at V of the active capacitorBThe third switch is arranged between the end and the ground and is arranged at V of the active capacitorABetween the end and the integrating capacitor, the fourth switch is arranged at V of the active capacitorBTerminal and output V of the operational amplifier AMPpBetween the ends.
3. The ramp voltage generator according to claim 1, wherein the control signal generating circuit comprises: a clock circuit for generating non-overlapping clock signals and a timing adjustment circuit for adjusting the timing of the non-overlapping clock signals;
the clock circuit receives a CLK clock signal and sends the non-overlapping clock signal to the first switch, the second switch and the timing adjustment circuit, and the timing adjustment circuit sends the non-overlapping clock signal with the adjusted timing to the third switch and the fourth switch.
4. The ramp voltage generator according to claim 2, wherein at least one of the first switch, the second switch, the third switch, and the fourth switch is comprised of PMOS transistors; or
At least one of the first switch, the second switch, the third switch and the fourth switch is composed of an NMOS tube.
5. The ramp voltage generator of claim 1, wherein the voltage input is configured to input a reference voltage, wherein the reference voltage is less than a target voltage for outputting a user demand.
6. An integrated circuit comprising the ramp voltage generator of any one of claims 1-5.
7. A method for generating a ramp voltage, wherein the ramp voltage generator of any one of claims 1 to 5 is used, and the method for generating a ramp voltage comprises:
in an integration period, controlling a switch set in the first charging circuit to be turned on and a switch set in the second charging circuit to be turned off so that the voltage of the active capacitor reaches a reference voltage reflecting the change rate of the voltage required by a user, and continuously controlling the switch set in the first charging circuit to be turned off and the switch set in the second charging circuit to be turned on based on the reference voltage so as to charge all the charges on the active capacitor to the integration capacitor; and
repeating a plurality of the integration periods to make the voltage of the integration capacitor reach a target voltage of the output user requirement, wherein the target voltage is larger than the reference voltage.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010561158.1A CN111752327A (en) | 2020-06-18 | 2020-06-18 | Ramp voltage generator and ramp voltage generation method |
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| CN202010561158.1A CN111752327A (en) | 2020-06-18 | 2020-06-18 | Ramp voltage generator and ramp voltage generation method |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1017172A1 (en) * | 1998-12-29 | 2000-07-05 | STMicroelectronics S.r.l. | Integrated circuit generating at least a voltage linear ramp having a slow rise |
| US20100085115A1 (en) * | 2008-10-03 | 2010-04-08 | Cambridge Semiconductor Limit St Andrews House St. Andrews Road | Signal generator |
| US20100320993A1 (en) * | 2007-12-14 | 2010-12-23 | Ricoh Company, Ltd. | Constant voltage circuit |
| US20160062375A1 (en) * | 2014-08-27 | 2016-03-03 | Intersil Americans Llc | Current mode control modulator with combined control signals and improved dynamic range |
| CN212675437U (en) * | 2020-06-18 | 2021-03-09 | 安徽赛腾微电子有限公司 | Integrated circuit and ramp voltage generator |
-
2020
- 2020-06-18 CN CN202010561158.1A patent/CN111752327A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1017172A1 (en) * | 1998-12-29 | 2000-07-05 | STMicroelectronics S.r.l. | Integrated circuit generating at least a voltage linear ramp having a slow rise |
| US20100320993A1 (en) * | 2007-12-14 | 2010-12-23 | Ricoh Company, Ltd. | Constant voltage circuit |
| US20100085115A1 (en) * | 2008-10-03 | 2010-04-08 | Cambridge Semiconductor Limit St Andrews House St. Andrews Road | Signal generator |
| US20160062375A1 (en) * | 2014-08-27 | 2016-03-03 | Intersil Americans Llc | Current mode control modulator with combined control signals and improved dynamic range |
| CN212675437U (en) * | 2020-06-18 | 2021-03-09 | 安徽赛腾微电子有限公司 | Integrated circuit and ramp voltage generator |
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