CN111667786B - Output buffer - Google Patents
Output buffer Download PDFInfo
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- CN111667786B CN111667786B CN201910175482.7A CN201910175482A CN111667786B CN 111667786 B CN111667786 B CN 111667786B CN 201910175482 A CN201910175482 A CN 201910175482A CN 111667786 B CN111667786 B CN 111667786B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention provides an output buffer, which comprises an amplifier, a switch transistor and a switching circuit. The first input of the amplifier receives an input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor provides an output voltage to the data line of the display panel. During the driving period, the switching circuit electrically connects the substrate of the switching transistor to the first terminal of the switching transistor or the second terminal of the switching transistor. In the high impedance period, the switching circuit electrically connects the substrate of the switching transistor to the power supply voltage.
Description
Technical Field
The present invention relates to a display device, and more particularly, to an output buffer.
Background
The source driver is used to drive a plurality of data lines (or source lines) of the display panel. The source driver is provided with a plurality of driving channel circuits, each of which drives a corresponding one of the data lines via a different output buffer. In the source driver, the output buffer may gain the analog voltage of the digital-to-analog converter and output the gain to the data line of the display panel. As the resolution and/or frame rate (frame rate) of the display panel increases, the charging time for one scan line decreases. In order to drive (charge or discharge) one pixel (pixel) in a short time, the output buffer needs to have a sufficiently high driving capability. That is, the output buffer needs to have a sufficiently high slew rate (slew rate).
Generally, the output buffer is configured with switching transistors. When the switch transistor is turned on (turn on), the output buffer can output the analog voltage to the data line of the display panel, i.e. the output buffer is in the driving period. When the switch transistor is turned off, the output buffer does not output the analog voltage to the data line of the display panel, i.e., the output buffer is in a high impedance period. The conventional switching transistor of the output buffer has a non-negligible on-resistance (Ron) due to a body effect (body effect). The larger the on-resistance of the output buffer, the smaller the slew rate of the output buffer.
Disclosure of Invention
The present invention provides an output buffer for reducing body effect of a switching transistor.
An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a first switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the first switching circuit is coupled to the substrate of the switching transistor. During the driving period, the first switching circuit electrically connects the substrate of the switching transistor to the first terminal of the switching transistor or the second terminal of the switching transistor. In the high impedance period, the first switching circuit electrically connects the substrate of the switching transistor to the power supply voltage.
An embodiment of the present invention provides an output buffer. The output buffer includes an amplifier, a switching transistor, and a switching circuit. The first input terminal of the amplifier is coupled to the input terminal of the output buffer to receive the input voltage. The control terminal of the switching transistor is controlled by a control signal, wherein the control signal at least defines a driving period and a high impedance period. The first terminal of the switching transistor is coupled to the output terminal of the amplifier. The second terminal of the switching transistor is coupled to the output terminal of the output buffer to provide an output voltage to the data line of the display panel. The common terminal of the switching circuit is coupled to the second input terminal of the amplifier. During the driving period, the switching circuit electrically connects the second input end of the amplifier to the second end of the switching transistor or the output welding pad, wherein the output welding pad is coupled to the second end of the switching transistor through the electrostatic discharge resistor. During the high impedance period, the switching circuit electrically connects the second input terminal of the amplifier to the output terminal of the amplifier.
Based on the above, the output buffer according to the embodiments of the present invention can electrically connect the body of the switching transistor to the power supply voltage during the high impedance period and electrically connect the body of the switching transistor to the first terminal (or the second terminal) of the switching transistor during the driving period. Therefore, the output buffer can reduce the body effect of the switching transistor. As the matrix effect is reduced, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby improving the slew rate (slew rate) of the output buffer.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a schematic diagram illustrating a circuit block (circuit block) of a display device according to an embodiment of the present invention.
FIG. 2 is a circuit block diagram illustrating the drive channel circuit of FIG. 1 according to one embodiment of the present invention.
FIG. 3 is a circuit block diagram illustrating an output buffer according to another embodiment of the present invention.
FIG. 4 is a circuit block diagram illustrating an output buffer according to yet another embodiment of the present invention.
FIG. 5 is a circuit block diagram illustrating an output buffer according to another embodiment of the present invention.
FIG. 6 is a circuit block diagram illustrating an output buffer according to yet another embodiment of the present invention.
FIG. 7 is a circuit block diagram illustrating an output buffer according to a further embodiment of the present invention.
Detailed Description
The term "coupled (or connected"), as used throughout this specification (including the claims), may refer to any direct or indirect connection. For example, if a first device couples (or connects) to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. In addition, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. Elements/components/steps in different embodiments that use the same reference numerals or use the same language may be referred to in relation to each other.
Fig. 1 is a schematic diagram illustrating a circuit block (circuit block) of a display device 100 according to an embodiment of the present invention. The display device 100 shown in fig. 1 includes a gate driver 110, a source driver 120 and a display panel 130. The display panel 130 may be any type of flat panel display, such as a liquid crystal display panel, an organic light emitting diode display panel, or other display panel. The display panel 130 includes a plurality of scan lines (or gate lines), a plurality of data lines (or source lines), and a plurality of pixel circuits. For example, as shown in fig. 1, the plurality of scan lines includes n scan lines sl_1, sl_2, …, sl_n, the plurality of data lines includes m data lines dl_1, dl_2, …, dl_m, and the plurality of pixel circuits includes m×n pixel circuits P (1, 1), …, P (m, 1), …, P (1, n), …, P (m, n), wherein m and n may be any integer determined according to design requirements.
The plurality of output terminals of the gate driver 110 are coupled to different scan lines of the display panel 130 in a one-to-one manner. The gate driver 110 may scan/drive each scan line of the display panel 130. The gate driver 110 may be any type of gate driver. For example, the gate driver 110 may be a conventional gate driver or other gate drivers according to design requirements.
The source driver 120 has a plurality of driving channel circuits, such as m driving channel circuits 121_1, 121_2, …, 121_m shown in fig. 1. The output terminals of the driving channel circuits 121_1 to 121_m are coupled to different data lines of the display panel 130 in a one-to-one manner. The driving channel circuits 121_1 to 121_m can convert digital pixel data into corresponding output voltages (pixel voltages) and output the output voltages to different data lines of the display panel 130. The source driver 120 can write these output voltages into the corresponding pixel circuits of the display panel 130 via the data lines dl_1 to dl_m to display images in accordance with the scanning timing of the gate driver 110.
Fig. 2 is a circuit block diagram illustrating the driving channel circuit 121_1 shown in fig. 1 according to an embodiment of the present invention. The other driving channel circuits 121_2 to 121_m shown in fig. 1 can be analogized with reference to the related description of the driving channel circuit 121_1 shown in fig. 2, and thus are not repeated. The driving channel circuit 121_1 shown in fig. 2 includes a latch 210, a channel circuit 220, and an output buffer 230. The latch 210 may provide the current pixel data to the channel circuit 220. Latch 210 may be any type of latch. For example, the latch 210 may be a conventional wire latch or other latch according to design requirements.
The channel circuit 220 can convert the current pixel data into an analog voltage (hereinafter referred to as an input voltage Vi), and output the input voltage Vi to the output buffer 230. In the embodiment shown in fig. 2, the channel circuit 220 may include a level shifter 221 and a digital-to-analog converter (digital to analog converter, DAC) 222. The level shifter 221 can adjust the voltage swing (voltage swing) of the current pixel data, and the digital-to-analog converter 222 can convert the current pixel data into the input voltage Vi. The digital-to-analog converter 222 may output the input voltage Vi to the output buffer 230. In other embodiments, the level shifter 221 may be omitted due to design requirements, such that the digital-to-analog converter 222 may receive current pixel data directly from the latch 210.
In the embodiment shown in fig. 2, the output buffer 230 includes an amplifier 231, a switching transistor 232, and a switching circuit 233. The amplifier 231 may be any type of buffer circuit, amplifying circuit, or gain circuit. For example, the amplifier 231 may comprise a conventional operational amplifier or other amplifiers according to design requirements. A first input (e.g., a non-inverting input) of the amplifier 231 is coupled to an input of the output buffer 230 (i.e., to an output of the digital-to-analog converter 222) to receive the input voltage Vi. The output of the amplifier 231 may generate the output voltage Vo. The output of the amplifier 231 is coupled to a second input (e.g., an inverting input) of the amplifier 231.
A first terminal (e.g., source or drain) of the switching transistor 232 is coupled to the output terminal of the amplifier 231. The second terminal (e.g., drain or source) of the switch transistor 232 is coupled to the output terminal of the output buffer 230 to provide the output voltage Vo to the data line dl_1 of the display panel 130. The control terminal of the switching transistor 232 is controlled by the control signal Sc1, wherein the control signal Sc1 defines at least one driving period and one high-impedance period. The high impedance period may also be referred to as HI-Z period. During the driving period, the switching transistor 232 is turned on. During the high impedance period, the switching transistor 232 is turned off.
The common terminal of the switching circuit 233 is coupled to the body of the switching transistor 232. The first selection terminal of the switching circuit 233 is coupled to the second terminal of the switching transistor 232. The second selection terminal of the switching circuit 233 is coupled to the power voltage. In the embodiment shown in FIG. 2, the switching transistor 232 is a P-channel transistor, such as a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. When the switching transistor 232 is a P-channel transistor, the power supply voltage may be any voltage (e.g., system voltage VDDA) that is higher than the voltage swing (swing) of the output voltage Vo.
During the driving period (during which the switching transistor 232 is turned on), the switching circuit 233 may electrically connect the substrate of the switching transistor 232 to the second terminal of the switching transistor 232. Therefore, the output buffer 230 can reduce the body effect of the switching transistor 232. Due to the reduced body effect, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate (slew rate) of the output buffer 230. During the high impedance period (the period when the switching transistor 232 is turned off), the switching circuit 233 may electrically connect the substrate of the switching transistor 232 to a power supply voltage (e.g., the system voltage VDDA) to ensure that the switching transistor 232 is turned off.
In the embodiment shown in fig. 2, the switching circuit 233 includes a switch SW1 and a switch SW2. The first terminal of the switch SW1 is coupled to the substrate of the switch transistor 232. A second terminal of the switch SW1 is coupled to a second terminal of the switch transistor 232. A first terminal of the switch SW2 is coupled to the body of the switching transistor 232. A second terminal of the switch SW2 is coupled to a power voltage (e.g., the system voltage VDDA). During the driving period (the period in which the switching transistor 232 is on), the switch SW1 is on and the switch SW2 is off. During the high impedance period (the period when the switching transistor 232 is off), the switch SW1 is off and the switch SW2 is on.
Fig. 3 is a circuit block diagram illustrating an output buffer 330 according to another embodiment of the present invention. The output buffer 330 of fig. 3 may be incorporated into the embodiment of fig. 2 (instead of the output buffer 230 of fig. 2) according to design requirements. In the embodiment shown in fig. 3, the output buffer 330 includes an amplifier 231, a switching transistor 232, and a switching circuit 233. The amplifier 231, the switching transistor 232 and the switching circuit 233 shown in fig. 3 can be analogized with reference to the related descriptions of the amplifier 231, the switching transistor 232 and the switching circuit 233 shown in fig. 2, and thus are not repeated.
In the embodiment shown in fig. 3, the first selection terminal of the switching circuit 233 is coupled to the first terminal of the switching transistor 232. That is, the second terminal of the switch SW1 is coupled to the first terminal of the switch transistor 232. During the driving period (during which the switching transistor 232 is turned on), the switching circuit 233 may electrically connect the substrate of the switching transistor 232 to the first terminal of the switching transistor 232. Therefore, the output buffer 330 can reduce the body effect of the switching transistor 232. Due to the reduced body effect, the on-resistance (Ron) of the switching transistor 232 can be effectively reduced, thereby increasing the slew rate (slew rate) of the output buffer 330. During the high impedance period (the period when the switching transistor 232 is turned off), the switching circuit 233 may electrically connect the substrate of the switching transistor 232 to a power supply voltage (e.g., the system voltage VDDA) to ensure that the switching transistor 232 is turned off.
Fig. 4 is a circuit block diagram illustrating an output buffer 430 according to yet another embodiment of the present invention. The output buffer 430 of fig. 4 may be incorporated into the embodiment of fig. 2 (instead of the output buffer 230 of fig. 2) according to design requirements. In the embodiment shown in fig. 4, the output buffer 430 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switching transistor 234 and the switching circuit 235 shown in fig. 4 can be analogized with reference to the related descriptions of the amplifier 231, the switching transistor 232 and the switching circuit 233 shown in fig. 2.
In the embodiment shown in fig. 4, a first terminal (e.g., drain or source) of the switching transistor 234 is coupled to the output terminal of the amplifier 231. A second terminal (e.g., source or drain) of the switching transistor 234 is coupled to an output terminal of the output buffer 230 for providing the output voltage Vo to the data line DL_1 of the display panel 130. The control terminal of the switching transistor 234 is controlled by the control signal Sc2, wherein the control signal Sc2 defines at least one driving period and one high-impedance period. The high impedance period may also be referred to as HI-Z period. During the driving period, the switching transistor 234 is turned on. During the high impedance period, the switching transistor 234 is turned off.
The common terminal of the switching circuit 235 is coupled to the substrate of the switching transistor 234. The first selection terminal of the switching circuit 235 is coupled to the second terminal of the switching transistor 234. The second selection terminal of the switching circuit 235 is coupled to the power supply voltage. In the embodiment shown in FIG. 4, the switching transistor 234 is an N-channel transistor, such as an N-channel Metal-Oxide-Semiconductor (NMOS) transistor. When the switch transistor 234 is an N-channel transistor, the power supply voltage may be any voltage (e.g., the reference voltage VSSA, or the ground voltage) that is lower than the voltage swing of the output voltage Vo.
During the driving period (during which the switching transistor 234 is turned on), the switching circuit 235 may electrically connect the substrate of the switching transistor 234 to the second terminal of the switching transistor 234. Therefore, the output buffer 430 can reduce the body effect of the switching transistor 234. Due to the reduced body effect, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate (slew rate) of the output buffer 430. During the high impedance period (during which the switching transistor 234 is turned off), the switching circuit 235 may electrically connect the substrate of the switching transistor 234 to a power supply voltage (e.g., the reference voltage VSSA) to ensure that the switching transistor 234 is turned off.
In the embodiment shown in fig. 4, the switching circuit 235 includes a switch SW3 and a switch SW4. A first terminal of the switch SW3 is coupled to the body of the switch transistor 234. A second terminal of the switch SW3 is coupled to a second terminal of the switch transistor 234. A first terminal of the switch SW4 is coupled to the body of the switch transistor 234. A second terminal of the switch SW4 is coupled to a power voltage (e.g., a reference voltage VSSA). During the driving period (the period in which the switching transistor 234 is on), the switch SW3 is on, and the switch SW4 is off. During the high impedance period (the period when the switching transistor 234 is off), the switch SW3 is off and the switch SW4 is on.
Fig. 5 is a circuit block diagram illustrating an output buffer 530 according to another embodiment of the present invention. The output buffer 530 of fig. 5 may be incorporated into the embodiment of fig. 2 (instead of the output buffer 230 of fig. 2) according to design requirements. In the embodiment shown in fig. 5, the output buffer 530 includes an amplifier 231, a switching transistor 234, and a switching circuit 235. The amplifier 231, the switch transistor 234 and the switch circuit 235 shown in fig. 5 can be analogized with reference to the related descriptions of the amplifier 231, the switch transistor 234 and the switch circuit 235 shown in fig. 4, and thus are not repeated.
In the embodiment shown in fig. 5, the first selection terminal of the switching circuit 235 is coupled to the first terminal of the switching transistor 234. That is, the second terminal of the switch SW3 is coupled to the first terminal of the switch transistor 234. During the driving period (during which the switching transistor 234 is turned on), the switching circuit 235 may electrically connect the substrate of the switching transistor 234 to the first terminal of the switching transistor 234. Therefore, the output buffer 530 can reduce the body effect of the switching transistor 234. Due to the reduced body effect, the on-resistance (Ron) of the switching transistor 234 can be effectively reduced, thereby increasing the slew rate (slew rate) of the output buffer 530. During the high impedance period (during which the switching transistor 234 is turned off), the switching circuit 235 may electrically connect the substrate of the switching transistor 234 to a power supply voltage (e.g., the reference voltage VSSA) to ensure that the switching transistor 234 is turned off.
Fig. 6 is a circuit block diagram illustrating an output buffer 630 according to yet another embodiment of the invention. The output buffer 630 of fig. 6 may be incorporated into the embodiment of fig. 2 (instead of the output buffer 230 of fig. 2) according to design requirements. In the embodiment shown in fig. 6, the output buffer 630 includes an amplifier 231, a switching transistor 236, and a switching circuit 237. The amplifier 231 shown in fig. 6 may refer to the related description of the amplifier 231 shown in fig. 2. The switching transistor 236 shown in fig. 6 can be analogized with reference to the related descriptions of the switching transistor 232 and the switching circuit 233 shown in fig. 2 or 3, or the switching transistor 236 shown in fig. 6 can be analogized with reference to the related descriptions of the switching transistor 234 and the switching circuit 235 shown in fig. 4 or 5, so that the descriptions are omitted. In other embodiments, the switching transistor 236 shown in FIG. 6 may be any switching device/circuit, such as a conventional switching transistor or other switching device, depending on the design requirements.
A first terminal of the switching transistor 236 is coupled to the output terminal of the amplifier 231. The second terminal of the switch transistor 236 is coupled to the output pad 240 through the electrostatic discharge resistor ESDR. When the switch transistor 236 is turned on, the output voltage Vo of the amplifier 231 can be transmitted to the data line dl_1 through the switch transistor 236, the electrostatic discharge resistor ESDR, and the output pad 240.
The common terminal of the switching circuit 237 of fig. 6 is coupled to the second input terminal of the amplifier 231. The first selection terminal of the switching circuit 237 is coupled to the second terminal of the switching transistor 236. A second select terminal of the switching circuit 237 is coupled to the output terminal of the amplifier 231. During the driving period (during which the switching transistor 236 is turned on), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the second terminal of the switching transistor 236. During the high impedance period (the period when the switching transistor 236 is turned off), the switching circuit 237 electrically connects the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.
In the embodiment shown in fig. 6, the switching circuit 237 includes a switch SW5 and a switch SW6. A first terminal of the switch SW5 is coupled to a second input terminal of the amplifier 231. A second terminal of the switch SW5 is coupled to a second terminal of the switch transistor 236. A first terminal of the switch SW6 is coupled to a second input terminal of the amplifier 231. A second terminal of the switch SW6 is coupled to the output terminal of the amplifier 231. During the driving period (the period in which the switching transistor 236 is on), the switch SW5 is on, and the switch SW6 is off. During the high impedance period (the period when the switching transistor 236 is off), the switch SW5 is off and the switch SW6 is on.
Fig. 7 is a circuit block diagram illustrating an output buffer 730 according to a further embodiment of the present invention. Output buffer 730 of fig. 7 may be incorporated into the embodiment of fig. 2 (instead of output buffer 230 of fig. 2) according to design requirements. In the embodiment shown in fig. 7, the output buffer 730 includes an amplifier 231, a switching transistor 236, and a switching circuit 237. The amplifier 231, the switch transistor 236 and the switching circuit 237 shown in fig. 7 can be analogized with reference to the related descriptions of the amplifier 231, the switch transistor 236 and the switching circuit 237 shown in fig. 6, and thus are not repeated.
In the embodiment shown in fig. 7, the first selection terminal of the switching circuit 237 is coupled to the output pad 240 via the esd resistor ESDR'. That is, the second terminal of the switch SW5 is coupled to the output pad 240. The output pad 240 is coupled to the second terminal of the switch transistor 236 through the electrostatic discharge resistor ESDR. During the driving period (during which the switching transistor 236 is turned on), the switching circuit 237 may electrically connect the second input terminal of the amplifier 231 to the pad 240. During the high impedance period (during which the switching transistor 236 is turned off), the switching circuit 237 may electrically connect the second input terminal of the amplifier 231 to the output terminal of the amplifier 231.
In summary, the output buffer according to the embodiments of the present invention can electrically connect the substrate of the switching transistor to the power voltage during the high impedance period and electrically connect the substrate of the switching transistor to the first terminal (or the second terminal) of the switching transistor during the driving period. Therefore, the output buffer can reduce the body effect of the switching transistor. As the matrix effect is reduced, the on-resistance (Ron) of the switching transistor can be effectively reduced, thereby improving the slew rate (slew rate) of the output buffer.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be modified and altered somewhat by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the invention is accordingly defined by the appended claims.
List of reference numerals
100: display device
110: gate driver
120: source driver
121_1, 121_2, 121_m: drive channel circuit
130: display panel
210: latch device
220: channel circuit
221: level shifter
222: digital-to-analog converter
230. 330, 430, 530, 630, 730: output buffer
231: amplifier
232. 234, 236: switching transistor
233. 235, 237: switching circuit
240: output welding pad
Dl_1, dl_2, dl_m: data line
ESDR, ESDR': electrostatic discharge resistor
P (1, 1), P (m, 1), P (1, n), P (m, n): pixel circuit
Sc1, sc2: control signal
Sl_1, sl_2, sl_n: scanning line
SW1, SW2, SW3, SW4, SW5, SW6: switch
VDDA: system voltage
Vi: input voltage
Vo: output voltage
VSSA: reference voltage
Claims (7)
1. An output buffer, comprising:
an amplifier having a first input coupled to an input of the output buffer for receiving an input voltage;
a switch transistor having a control terminal controlled by a control signal, wherein the control signal defines at least a driving period and a high impedance period, a first terminal of the switch transistor is coupled to an output terminal of the amplifier, and a second terminal of the switch transistor is coupled to an output terminal of the output buffer to provide an output voltage to a data line of a display panel; and
the first switching circuit is provided with a common terminal coupled to a substrate of the switch transistor, wherein the first switching circuit is used for electrically connecting the substrate of the switch transistor to the first terminal of the switch transistor or the second terminal of the switch transistor in the driving period, and is used for electrically connecting the substrate of the switch transistor to a power voltage in the high-impedance period.
2. The output buffer of claim 1 wherein the switching transistor is on during the driving period and is off during the high impedance period.
3. The output buffer of claim 1,
when the switch transistor is a P-channel transistor, the power supply voltage is a system voltage higher than a voltage swing of the output voltage; and
when the switching transistor is an N-channel transistor, the power supply voltage is a reference voltage lower than the voltage swing of the output voltage.
4. The output buffer of claim 1 wherein the first switching circuit comprises:
a first switch having a first terminal coupled to the substrate of the switching transistor, wherein a second terminal of the first switch is coupled to the first terminal of the switching transistor or the second terminal of the switching transistor, the first switch being turned on during the driving period and turned off during the high impedance period; and
a second switch having a first terminal coupled to the substrate of the switching transistor, wherein a second terminal of the second switch is coupled to the power supply voltage, the second switch being turned off during the driving period and being turned on during the high impedance period.
5. The output buffer of claim 1 wherein the output of the amplifier is coupled to a second input of the amplifier.
6. The output buffer of claim 1, further comprising:
a second switching circuit having a common terminal coupled to a second input terminal of the amplifier, wherein the second switching circuit electrically connects the second input terminal of the amplifier to the second terminal of the switching transistor or an output pad coupled to the second terminal of the switching transistor via an electrostatic discharge resistor during the driving period, and electrically connects the second input terminal of the amplifier to the output terminal of the amplifier during the high impedance period.
7. The output buffer as recited in claim 6, wherein the second switching circuit comprises:
a first switch having a first end coupled to the second input of the amplifier, wherein a second end of the first switch is coupled to the second end of the switching transistor or the output pad, the first switch being turned on during the driving period and turned off during the high impedance period; and
a second switch having a first end coupled to the second input of the amplifier, wherein a second end of the second switch is coupled to the output of the amplifier, the second switch being turned off during the driving period and turned on during the high impedance period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910175482.7A CN111667786B (en) | 2019-03-08 | 2019-03-08 | Output buffer |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910175482.7A CN111667786B (en) | 2019-03-08 | 2019-03-08 | Output buffer |
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| CN111667786A CN111667786A (en) | 2020-09-15 |
| CN111667786B true CN111667786B (en) | 2023-07-21 |
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| CN108682380B (en) * | 2018-07-26 | 2021-01-08 | 京东方科技集团股份有限公司 | Shift register and driving method thereof, grid driving circuit and display device |
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| CN101750815A (en) * | 2008-12-16 | 2010-06-23 | 奇景光电股份有限公司 | Source driver for driving a panel and related method for controlling a display |
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| CN111667786A (en) | 2020-09-15 |
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