CN111666174B

CN111666174B - Data writing method, memory control circuit unit and memory storage device

Info

Publication number: CN111666174B
Application number: CN201910171419.6A
Authority: CN
Inventors: 简嘉宏; 颜孝轩
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2019-03-07
Filing date: 2019-03-07
Publication date: 2023-03-14
Anticipated expiration: 2039-03-07
Also published as: CN111666174A

Abstract

The invention provides a data writing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: receiving a plurality of data from a host system and respectively writing the data into a plurality of first entity programming units; performing multi-frame encoding according to the data to generate encoded data, and writing the encoded data into a second entity programming unit; and writing a plurality of first concatenation information related to the encoded data into the plurality of first entity programming units respectively.

Description

Data writing method, memory control circuit unit and memory storage device

Technical Field

The invention relates to a data writing method, a memory control circuit unit and a memory storage device.

Background

Digital cameras, mobile phones, and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable nonvolatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.

Generally, when reading data in an entity programming unit, the data read from the entity programming unit can be decoded by using the encoded data of the single frame coding for error detection and correction. However, when decoding using the encoded data of the single-frame code fails, the encoded data of the multi-frame code and the plurality of data used to generate the encoded data of the multi-frame code may be read and decoded according to the encoded data of the multi-frame code and the plurality of data used to generate the encoded data of the multi-frame code, so as to attempt to correct errors existing in the data stored in the currently read physical programming unit.

However, the error checking and correcting capability of the encoded data of the multi-frame coding is proportional to the number of bits of the encoded data of the multi-frame coding. When the number of bits of the encoded data of the multi-frame coding is small, the error checking and correcting capability of the encoded data of the multi-frame coding is low. In addition, when the format of the physical programming unit for storing the data written by the host system is different from the format of the physical programming unit for storing the encoded data of the multi-frame code, the complexity of the algorithm design and the cost of the hardware design are increased. In addition, if the encoded data of the multi-frame code is stored in a physically erased cell, and the physically erased cell is different from the physically erased cell in which the data written by the host system is located, time is also increased when the encoded data of the multi-frame code is written and read.

Disclosure of Invention

Therefore, the present invention provides a data writing method, a memory control circuit unit and a memory storage device, which can increase the bit number of the encoded data to improve the error checking and correcting capability of the encoded data, reduce the complexity of the algorithm design and the cost of the hardware design, and reduce the time required for writing and reading the encoded data.

The invention provides a data writing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps: receiving a plurality of data from a host system and respectively writing the data into i first entity programming units in the entity programming units, wherein i is a positive integer greater than zero; performing a multi-frame encoding according to the data to generate encoded data, and writing the encoded data into a second entity programming unit of the entity programming units; and writing a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information are used for recording positions of the plurality of data in the i first physical programming units.

In an embodiment of the invention, the first concatenation information of a kth first physical programming unit of the i first physical programming units is used to record a position of at least one other physical programming unit except the kth first physical programming unit of the i first physical programming units, where k is a positive integer greater than zero and less than i + 1.

In an embodiment of the invention, the locations of the other physical program cells include a location of an nth one of the i first physical program cells, where n is a positive integer greater than zero and less than k.

In an embodiment of the invention, the first concatenation information of the kth first physical programming unit includes at least one first bit and at least one second bit, the first bit is used for recording a position of a (k-1) th first physical programming unit of the i first physical programming units, and the second bit is used for recording a position of a (k-2) th first physical programming unit of the i first physical programming units, and k is greater than 2.

In an embodiment of the invention, the step of performing the multi-frame encoding according to the data to generate the encoded data and writing the encoded data into the second physical programming unit of the physical programming units comprises: writing second concatenation information into the second entity programming unit, wherein the second concatenation information is used for recording the position of the jth first entity programming unit in the i first entity programming units, and j is a positive integer larger than zero and smaller than i + 1.

In an embodiment of the invention, the second concatenation information includes at least one third bit and at least one fourth bit, the third bit is used for recording a position of an i-th first entity programming unit of the i first entity programming units, and the fourth bit is used for recording a position of an i-1-th first entity programming unit of the i first entity programming units, and i is greater than 1.

In an embodiment of the invention, a format for recording data in the second physical programming unit is the same as a format for recording data in each of the i first physical programming units.

In an embodiment of the invention, the i first physically programmed cells and the second physically programmed cells belong to a first physically erased cell among the plurality of physically erased cells.

The invention provides a memory control circuit unit for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit includes: a host interface, a memory interface, and memory management circuitry. The host interface is used for being coupled to a host system. The memory interface is used for being coupled to the rewritable nonvolatile memory module. Memory management circuitry is coupled to the host interface and the memory interface. The memory management circuit is used for executing the following operations: receiving a plurality of data from a host system and respectively writing the data into i first entity programming units in the entity programming units, wherein i is a positive integer greater than zero; performing a multi-frame encoding according to the data to generate encoded data, and writing the encoded data into a second entity programming unit of the entity programming units; and writing a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information are used for recording positions of the plurality of data in the i first physical programming units.

In an embodiment of the invention, the locations of the other physical program cells include a location of an nth first physical program cell of the i first physical program cells, where n is a positive integer greater than zero and less than k.

In an embodiment of the invention, the first concatenation information of the kth first entity programming unit includes at least one first bit and at least one second bit, the first bit is used for recording a position of a (k-1) th first entity programming unit of the i first entity programming units, the second bit is used for recording a position of a (k-2) th first entity programming unit of the i first entity programming units, and k is greater than 2.

In an embodiment of the invention, in the operation of performing the multi-frame coding according to the data to generate the coded data and writing the coded data into the second physical programming unit of the physical programming units, the memory management circuit is further configured to write a second concatenation information into the second physical programming unit, wherein the second concatenation information is used to record a position of a jth first physical programming unit of the i first physical programming units, where j is a positive integer greater than zero and less than i + 1.

The invention provides a memory storage device, which comprises a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The connection interface unit is used for being coupled to a host system. The rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units. The memory control circuit unit is coupled to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: receiving a plurality of data from a host system and respectively writing the data into i first entity programming units in the entity programming units, wherein i is a positive integer greater than zero; performing multi-frame encoding according to the data to generate encoded data, and writing the encoded data into a second entity programming unit in the entity programming units; and writing a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information are used for recording positions of the plurality of data in the i first physical programming units.

In an embodiment of the invention, in the operation of performing the multi-frame coding according to the data to generate the coded data and writing the coded data into the second physical programming unit of the physical programming units, the memory control circuit unit is further configured to write a second concatenation information into the second physical programming unit, wherein the second concatenation information is used to record a position of a jth first physical programming unit of the i first physical programming units, where j is a positive integer greater than zero and less than i + 1.

Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the invention can increase the bit number of the encoded data to improve the error checking and correcting capability of the encoded data. In addition, in the data writing method of the present invention, since the format of the physical programming unit for recording the data written by the host system is the same as the format of the physical programming unit for recording the encoded data, the complexity of algorithm design and the cost of hardware design can be reduced. In addition, in the data writing method of the present invention, since the encoded data is stored in the same physical erasure unit as the data used to generate the encoded data, the time required for writing and reading the encoded data can be reduced.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention.

FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.

FIG. 3 is a diagram illustrating a host system and a memory storage device according to another exemplary embodiment of the invention.

Fig. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the invention.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment.

FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

FIG. 7 is a graph illustrating a statistical distribution of gate voltages corresponding to write data stored in an array of memory cells, according to an example embodiment.

FIG. 8 is a diagram illustrating reading data from a memory cell according to an example embodiment.

FIG. 9 is a diagram illustrating reading data from a memory cell according to another example embodiment.

FIG. 10 is a diagram illustrating an example of a physically erased cell according to the present example embodiment.

FIG. 11 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Fig. 12 is a diagram illustrating multi-frame coding according to an exemplary embodiment of the present invention.

FIG. 13A is a diagram of a plurality of data in a plurality of discrete physical programming units for generating encoded data of a multi-frame code.

Fig. 13B is a schematic diagram illustrating a data writing method according to an exemplary embodiment of the invention.

Fig. 14 is a flowchart illustrating a data writing method according to an exemplary embodiment of the present invention.

[ notation ] to show

10: memory storage device

11: host system

110: system bus

111: processor with a memory for storing a plurality of data

112: random access memory

113: read-only memory

114: data transmission interface

12: input/output (I/O) device

20: motherboard with a memory card

201: portable disk

202: memory card

203: solid state disk

204: wireless memory storage device

205: global positioning system module

206: network interface card

207: wireless transmission device

208: keyboard with a keyboard body

209: screen

210: horn type loudspeaker

32: SD card

33: CF card

34: embedded memory device

341: embedded multimedia card

342: embedded multi-chip packaging storage device

402: connection interface unit

404: memory control circuit unit

406: rewritable nonvolatile memory module

2202: memory cell array

2204: word line control circuit

2206: bit line control circuit

2208: row decoder

2210: data input/output buffer

2212: control circuit

502: memory cell

504: bit line

506: word line

508: common source line

512: select gate drain transistor

514: selective gate source transistor

VA, VB, VC, VD, VE, VF, VG: read voltage

702: memory management circuit

704: host interface

706: memory interface

708: error checking and correcting circuit

710: buffer memory

712: power management circuit

801 (1) to 801 (r): position of

820: encoding data

810 (0) to 810 (E), 825 (1) to 825 (8), 830 (1) to 830 (8): physical programming unit

825. 830: physical erase unit

DATA1 to DATA5: data of

ECC1, ECC2: encoding data

E _ Info: encoding information

A1, A2: column position

S1401: a step of receiving a plurality of data from a host system and respectively writing the data into i first entity programming units, wherein i is a positive integer larger than zero

S1403: performing multi-frame encoding according to the data to generate encoded data, and writing the encoded data into the second physical programming unit

S1405: writing a plurality of first concatenation information related to the encoded data into the i first physical programming units respectively, wherein the first concatenation information of a kth first physical programming unit of the i first physical programming units is used for recording the position of at least one other physical programming unit except the kth first physical programming unit of the i first physical programming units, wherein k is a positive integer greater than zero and less than i +1

S1407: writing second concatenation information into a second entity programming unit, wherein the second concatenation information is used for recording the position of a jth first entity programming unit in the i first entity programming units, and j is a positive integer larger than zero and smaller than i +1

Detailed Description

Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.

FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention.

Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all coupled to a system bus (system bus) 110.

In the present exemplary embodiment, the host system 11 is coupled to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is coupled to the I/O devices 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.

In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 can be coupled to the memory storage device 10 via a wired or wireless manner through the data transmission interface 114. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be coupled to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of the host system and the memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-media cards (eMMC) 341 and/or embedded Multi-Chip Package memory (eMCP) 342, which directly couple the memory module to the embedded memory device on the substrate of the host system.

Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.

In the present exemplary embodiment, connection interface unit 402 is compatible with the Serial Advanced Technology Attachment (SATA) standard. However, it should be understood that the connection interface unit 402 is not limited thereto, and may also be compliant with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the High Speed Peripheral Component connection interface (PCI Express) standard, the Universal Serial Bus (USB) standard, the Secure Digital (SD) interface standard, the Ultra High Speed (UHS-I) interface standard, the Ultra High Speed (Ultra High Speed-II, UHS-II) interface standard, the Memory Stick (Memory Stick, MS) interface standard, the Multi-Chip Package (Multi-Package) interface standard, the Multimedia Memory Card (Multi-Embedded Device, flash (CF) interface, the Embedded Multimedia Memory (mc) standard, the Embedded Multimedia Card (mcm) interface standard, the Embedded Multimedia Memory Card (mc) standard, the Embedded Multimedia Card (CF) interface standard, the Embedded Multimedia Card (Flash) interface standard, or the Embedded Multimedia Card (Flash) interface (mc) standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.

The rewritable nonvolatile memory module 406 is coupled to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable non-volatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a multiple Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules with the same characteristics.

The memory cells in the rewritable nonvolatile memory module 406 are arranged in an array. The memory cell array is described below as a two-dimensional array. However, it should be noted that the following exemplary embodiment is only an example of the memory cell array, and in other exemplary embodiments, the configuration of the memory cell array may be adjusted to meet practical requirements.

FIG. 5 is a schematic block diagram of a rewritable non-volatile memory module according to an example embodiment. FIG. 6 is a schematic diagram of an array of memory cells according to an example embodiment.

Referring to fig. 5 and fig. 6, the rewritable nonvolatile memory module 406 includes a memory cell array 2202, a word line control circuit 2204, a bit line control circuit 2206, a column decoder 2208, a data input/output buffer 2210 and a control circuit 2212.

In the present exemplary embodiment, the memory cell array 2202 may include a plurality of memory cells 502 for storing data, a plurality of Select Gate Drain (SGD) transistors 512 and a plurality of Select Gate Source (SGS) transistors 514, and a plurality of bit lines 504, a plurality of word lines 506, and a common source line 508 (fig. 6) connecting the memory cells. The memory cells 502 are arranged in an array (or stacked) at the intersections of bit lines 504 and word lines 506. When a write command or a read command is received from the memory control circuit unit 404, the control circuit 2212 controls the word line control circuit 2204, the bit line control circuit 2206, the row decoder 2208 and the data input/output buffer 2210 to write data into the memory cell array 2202 or read data from the memory cell array 2202, wherein the word line control circuit 2204 controls the voltage applied to the word line 506, the bit line control circuit 2206 controls the voltage applied to the bit line 504, the row decoder 2208 selects the corresponding bit line according to the row address in the command, and the data input/output buffer 2210 is used for temporarily storing the data.

The memory cells in the rewritable nonvolatile memory module 406 store bits (bits) with a change in threshold voltage. Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby changing the threshold voltage of the memory cell. This process of changing the threshold voltage is also referred to as "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell of the memory cell array 2202 has multiple memory states. And the reading voltage can judge which storage state the memory cell belongs to, thereby obtaining the bit stored by the memory cell.

Referring to fig. 7, taking MLC NAND flash as an example, each memory cell has 4 memory states with different threshold voltages, and the memory states represent bits "11", "10", "00" and "01", respectively. In other words, each memory state includes the Least Significant Bit (LSB) and the Most Significant Bit (MSB). In the present exemplary embodiment, the 1 st bit from the left side in the memory states (i.e., "11", "10", "00", and "01") is the LSB, and the 2 nd bit from the left side is the MSB. Thus, in this example embodiment, each memory cell can store 2 bits. It should be understood that the threshold voltages and their corresponding memory states shown in FIG. 7 are only exemplary. In another exemplary embodiment of the present invention, the correspondence between the threshold voltage and the memory state may be arranged in "11", "10", "01" and "00" or other arrangements as the threshold voltage is larger. In addition, in another exemplary embodiment, it is also possible to define the 1 st bit from the left side as the MSB and the 2 nd bit from the left side as the LSB.

In an example embodiment where a memory cell can store multiple bits (e.g., MLC or TLC NAND flash memory module), physical program cells belonging to the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, in an MLC NAND flash memory module, the Least Significant Bit (LSB) of a cell belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of the cell belongs to the upper physical programming unit. In an example embodiment, the lower physical program unit is also referred to as a fast page (fast page), and the upper physical program unit is also referred to as a slow page (slow page). In addition, in the TLC NAND flash memory module, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical programming unit, the middle Significant Bit (CSB) of the memory cell belongs to the middle physical programming unit, and the Most Significant Bit (MSB) of the memory cell belongs to the upper physical programming unit.

FIG. 8 is a diagram illustrating reading data from a memory cell, such as an MLC NAND flash memory, according to an example embodiment.

Referring to FIG. 8, a read operation of the memory cells of the memory cell array 2202 is performed by applying read voltages VA-VC to the control gates to identify data stored in the memory cells by the conductive states of the memory cell channels. A verify bit (VA) is used to indicate whether the memory cell channel is turned on when the read voltage VA is applied; the verification bit (VC) is used for indicating whether the memory cell channel is conducted or not when the reading voltage VC is applied; the Verify Bit (VB) is used to indicate whether the memory cell channel is turned on when the read voltage VB is applied. It is assumed herein that the verify bit is "1" indicating that the corresponding memory cell channel is turned on, and the verify bit is "0" indicating that the corresponding memory cell channel is not turned on. As shown in fig. 8, it is possible to determine which memory state the memory cell is in by verifying the bits (VA) to (VC), and to acquire the stored bit.

FIG. 9 is a schematic diagram illustrating reading data from a memory cell according to another example embodiment.

Referring to fig. 9, in a TLC NAND type flash memory as an example, each memory state includes a least Significant Bit LSB of a1 st Bit from the left side, a middle Significant Bit (CSB) of a2 nd Bit from the left side, and a most Significant Bit MSB of a3 rd Bit from the left side. In this example, the memory cell has 8 memory states (i.e., "111", "110", "100", "101", "001", "000", "010", and "011") according to different threshold voltages. The bit stored in the memory cell can be identified by applying the read voltages VA-VG to the control gates.

It should be noted that the arrangement order of the 8 memory states in fig. 9 may be determined by the design of the manufacturer, and is not limited to the arrangement manner of the present example.

In addition, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming units, and the physical programming units form a plurality of physical erasing units. Specifically, the memory cells on the same word line in FIG. 6 constitute one or more physical program cells. For example, if the rewritable nonvolatile memory module 406 is an MLC NAND flash memory module, the memory cells at the intersections of the same word line and multiple bit lines constitute 2 physical program cells, i.e. an upper physical program cell and a lower physical program cell. And an upper physical programming unit and a lower physical programming unit can be collectively referred to as a physical programming unit group. In particular, if the data to be read is located in a lower physical program cell of a physical program cell group, the value of each bit in the lower physical program cell can be identified by using the read voltage VA shown in fig. 8. If the data to be read is located in an upper physical programming cell of a physical programming cell group, the reading voltage VB and the reading voltage VC as shown in fig. 8 can be used to identify the value of each bit in the upper physical programming cell.

Alternatively, if the rewritable nonvolatile memory module 406 is a TLC NAND flash memory module, the memory cells at the intersections of the same word line and the bit lines constitute 3 physical program cells, i.e., an upper physical program cell, a middle physical program cell, and a lower physical program cell. And an upper entity programming unit, a middle entity programming unit and a lower entity programming unit can be collectively called as an entity programming unit group. In particular, if the data to be read is located in a lower physical program cell of a physical program cell group, the value of each bit in the lower physical program cell can be identified by using the read voltage VA in fig. 9. If the data to be read is located in one of the physical program cells of one of the physical program cell groups, the read voltage VB and the read voltage VC as shown in fig. 9 can be used to identify the value of each bit in the physical program cell. If the data to be read is located in an upper physical programming unit of a physical programming unit set, the reading voltage VD, the reading voltage VE, the reading voltage VF, and the reading voltage VG shown in fig. 9 can be used to identify the value of each bit in the upper physical programming unit.

In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the smallest number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).

Referring to fig. 10, in the present exemplary embodiment, it is assumed that one physically erased cell is composed of a plurality of physically programmed cell groups, wherein each of the physically programmed cell groups includes a lower physically programmed cell, a middle physically programmed cell and an upper physically programmed cell composed of a plurality of memory cells arranged on the same word line. For example, in the solid erase cell, the 0 th solid program cell belonging to the lower solid program cell, the 1 st solid program cell belonging to the middle solid program cell, and the 2 nd solid program cell belonging to the upper solid program cell are regarded as one solid program cell group. Similarly, the 3 rd, 4 th, and 5 th physical programming cells are regarded as a physical programming cell group, and the other physical programming cells are divided into a plurality of physical programming cell groups according to the manner.

Referring to FIG. 11, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.

The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to write, read, and erase data during operation of the memory storage device 10. When the operation of the memory management circuit 702 or any circuit element included in the memory control circuit unit 404 is described below, the operation of the memory control circuit unit 404 is equivalently described.

In the exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

In another example embodiment, the control instructions of the memory management circuit 702 may also be stored in a program code type in a specific area of the rewritable non-volatile memory module 406 (e.g. a system area dedicated to storing system data in the memory module). Further, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.

In another exemplary embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware format. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are coupled to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding write, read, and erase operations. In an example embodiment, the memory management circuit 702 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.

The host interface 704 is coupled to the memory management circuit 702 and is used for receiving and identifying commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may be compatible with the PATA standard, the IEEE 1394 standard, the PCI Express standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.

The memory interface 706 is coupled to the memory management circuit 702 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written into the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 wants to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions are generated by, for example, the memory management circuit 702 and transferred to the rewritable non-volatile memory module 406 via the memory interface 706. The sequence of instructions may include one or more signals, or data, on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes information such as the identification code and the memory address of the read command.

The ECC circuit 708 is coupled to the memory management circuit 702 and is configured to perform an ECC process to ensure data correctness. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 708 performs an error checking and correcting process on the read data according to the error correction code and/or the error check code.

In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.

The buffer memory 710 is coupled to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is coupled to the memory management circuit 702 and is used to control the power of the memory storage device 10.

In the exemplary embodiment, the error checking and correcting circuit 708 can perform single-frame (single-frame) encoding on data stored in the same physical program unit, or perform multi-frame (multi-frame) encoding on data stored in multiple physical program units. The single frame coding and the multi-frame coding may respectively use at least one of low density parity check code (LDPC), BCH, convolutional code (turbo code), and turbo code. Alternatively, in an example embodiment, the multi-frame coding may also employ Reed-solomon (RS) codes or exclusive or (XOR) algorithms. In addition, in another exemplary embodiment, more unlisted coding algorithms may be used, and are not described herein. Depending on the encoding algorithm employed, the ECC circuitry 708 may encode the data to be protected to generate corresponding ECC and/or ECC codes. For convenience of explanation, the error correction code and/or the error check code generated through encoding will be collectively referred to as encoded data hereinafter.

Referring to fig. 12, taking the example of encoding the data stored in the entity programming units 810 (0) to 810 (E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the entity programming units 810 (0) to 810 (E) can be regarded as a frame. In the multi-frame coding, data in the physical programming units 810 (0) to 810 (E) is coded according to the position of each bit (or byte). For example, bit b at position 801 (1) ₁₁ 、b ₂₁ 、…、b _p1 Will be encoded as bit b in the encoded data 820 _o1 Bit b at position 801 (2) ₁₂ 、b ₂₂ 、…、b _p2 Will be encoded as bit b in the encoded data 820 _o2 (ii) a By analogy, bit b at position 801 (r) _1r 、b _2r 、…、b _pr Will be encoded into a coded numberAccording to bit b in 820 _or . Thereafter, the data read from the physical programming units 810 (0) to 810 (E) may be decoded based on the encoded data 820 in an attempt to correct errors that may exist in the read data.

In addition, in another exemplary embodiment of fig. 12, the data for generating the encoded data 820 may also include redundancy bits (redundancy bits) corresponding to data bits (data bits) in the data stored in the physical programming units 810 (0) -810 (E). Take the data stored in the physical programming unit 810 (0) as an example, wherein the redundancy bits are generated by performing single frame coding on the data bits stored in the physical programming unit 810 (0), for example. In the present exemplary embodiment, it is assumed that when reading data in the physical programming unit 810 (0), the data read from the physical programming unit 810 (0) can be decoded first using redundant bits (e.g., single frame coded (unicode) encoded data) in the physical programming unit 810 (0) for error detection and correction. However, when the decoding using the redundant bits in the physical programming unit 810 (0) fails (e.g., the number of error bits of the data stored in the decoded physical programming unit 810 (0) is greater than a threshold), the encoded data 820 and the data of the physical programming units 810 (1) -810 (E) can be read, and the decoding can be performed according to the encoded data 820 and the data of the physical programming units 810 (1) -810 (E) to attempt to correct errors in the data stored in the physical programming unit 810 (0). That is, in the present exemplary embodiment, when a failure occurs in decoding using encoded data generated by single-frame encoding, the encoded data generated by multi-frame encoding is used instead for decoding.

It should be noted, however, that in general, a plurality of data for generating multi-frame encoded data may be respectively located in a plurality of discrete physical programming units. For example, fig. 13A is a schematic diagram of a plurality of data respectively located in a plurality of discrete physical programming units for generating encoded data of a multi-frame code in the prior art.

Referring to FIG. 13A, for convenience of illustration, in the example of FIG. 13A, it is assumed that the rewritable nonvolatile memory module 406 has a physical erase unit 825. The physical erase unit 825 has physical program units 825 (1) -825 (8). When the memory management circuit 702 receives the DATA1 to DATA5 from the host system 11, the memory management circuit 702 may write the DATA1 to DATA5 into the physical programming units 825 (1) to 825 (2), 825 (4) to 825 (5), 825 (7), respectively. It should be noted that, although not shown in fig. 13A, each of the physical programming units 825 (1) -825 (2), 825 (4) -825 (5), 825 (7) further includes a redundant bit region, and the redundant bit region is used for storing encoded data of single frame coding. In addition, in this embodiment, the redundant bit area further includes a plurality of bits that are reserved in advance and are not used.

In this embodiment, it is assumed that entity programming unit 825 (3) and entity programming unit 825 (6) do not store data due to a program fail relationship. Thereafter, the memory management circuit 702 may perform multi-frame encoding according to the DATA1 to DATA5 to generate encoded DATA ECC1, and write the encoded DATA ECC1 into the physical programming unit 825 (8). It should be noted that, in the prior art, the physical programming unit 825 (8) for storing the encoded DATA ECC1 of the multi-frame code also needs to record an encoding information E _ Info to record the positions of the DATA DATA 1-DATA 5 for generating the encoded DATA ECC 1. More specifically, in the embodiment, since the physical programming units 825 (1) -825 (8) are located in the same physical erasing unit 825, the memory management circuit 702 can use a bitmap (bitmap) to represent the encoding information E _ Info. In the exemplary embodiment of fig. 13A, the value of the encoding information E _ Info is "1101101". Wherein, from the leftmost bit in the value of the encoded information E _ Info, the first bit corresponds to the physical programming unit 825 (1), the second bit corresponds to the physical programming unit 825 (2), the third bit corresponds to the physical programming unit 825 (3), and so on. In the encoded information E _ Info, when a bit value is "1", it indicates that the physical programming unit corresponding to the bit stores data for generating the encoded information ECC1, and when a bit value is "0", it indicates that the physical programming unit corresponding to the bit does not store data for generating the encoded information ECC 1.

For example, since the bit value of the first bit from the leftmost bit in the encoded information E _ Info is "1", it represents that the physical programming unit 825 (1) stores the data for generating the encoded data ECC 1. For another example, since the bit value of the third bit from the leftmost bit in the encoded information E _ Info is "0", it represents that the physical programming unit 825 (3) does not store the data for generating the encoded data ECC 1.

Based on the above, it is assumed that when reading the data in the physical programming unit 825 (1), the data read from the physical programming unit 825 (1) can be decoded by using the redundant bits (not shown, for example, the encoded data of the single frame coding) in the physical programming unit 825 (1) for error detection and correction. However, when the decoding using the redundant bits in the physical programming unit 825 (1) fails, the memory management circuit 702 can read the encoded data ECC1 and know that the data used for generating the encoded data ECC1 is stored in the physical programming units 825 (2), 825 (4) -825 (5), 825 (7) according to the encoding information E _ Info. Therefore, the memory management circuit 702 can read the encoded DATA ECC1 and the DATA2 to DATA5 stored in the physical programming units 825 (2), 825 (4) -825 (5), 825 (7), and decode according to the encoded DATA ECC1 and the DATA2 to DATA5 to attempt to correct errors in the DATA stored in the physical programming unit 825 (1).

It should be noted that the error checking and correcting capability of the encoded data ECC1 is proportional to the number of bits of the encoded data ECC 1. In the storage method of fig. 13A, the physical programming unit 825 (8) for storing the encoded data ECC1 needs to use more bits to store the encoded information E _ Info, which results in less bits for the encoded data ECC1, and further causes a problem of lower error checking and correcting capability for the encoded data ECC 1. In addition, as is clear from fig. 13A, the format of the entity programming units 825 (1) -825 (2), 825 (4) -825 (5), 825 (7) for recording the DATA 1-DATA 5 written by the host system 11 is different from the format of the entity programming unit 825 (8) for recording the encoded DATA ECC1, which results in complexity of algorithm design and cost increase in hardware design. In addition, if the encoded DATA ECC1 is stored in a physically erased cell, which is different from the physically erased cells in which the DATA DATA 1-DATA 5 are located, the time for writing and reading the encoded DATA ECC1 is also increased.

Therefore, the present invention provides a data writing method, which can increase the bit number of the encoded data to improve the error checking and correcting capability of the encoded data. In addition, in the data writing method of the present invention, since the format of the physical programming unit for recording the data written by the host system is the same as the format of the physical programming unit for recording the encoded data, the complexity of algorithm design and the cost of hardware design can be reduced. In addition, in the data writing method of the present invention, since the encoded data is stored in the same physical erasure unit as the data used to generate the encoded data, the time required for writing and reading the encoded data can be reduced.

In more detail, fig. 13B is a schematic diagram illustrating a data writing method according to an exemplary embodiment of the invention.

Referring to FIG. 13B, for convenience of illustration, in the example of FIG. 13B, it is assumed that the rewritable nonvolatile memory module 406 has a physically erased cell 830 therein. The physical erase unit 830 has physical program units 830 (1) -830 (8). In the data writing method of the present invention, when the memory management circuit 702 receives a plurality of data from the host system 11, the memory management circuit 702 writes the data into i first physical programming units respectively, wherein i is a positive integer greater than zero.

Taking fig. 13B as an example, when the memory management circuit 702 receives the DATA1 to DATA5 from the host system 11, the memory management circuit 702 may write the DATA1 to DATA5 into the physical programming units 830 (1) to 830 (2), 830 (4) to 830 (5), and 830 (7), respectively (i.e., the "first physical programming unit" described above). In the embodiment of fig. 13B, i has a value of 5. However, the present invention is not limited to the value of i. In addition, in the embodiment of fig. 13B, it is assumed that entity program unit 830 (3) and entity program unit 830 (6) do not store data due to a program fail relationship.

Thereafter, the memory management circuit 702 may perform multi-frame encoding according to the DATA1 to DATA5 to generate encoded DATA ECC2, and write the encoded DATA ECC2 into the physical programming unit 830 (8) (also referred to as a second physical programming unit).

In this embodiment, each of the physical programming units 830 (1) -830 (2), 830 (4) -830 (5), and 830 (7) further needs to store the first serial information related to the encoded data ECC2. The memory management circuit 702 writes a plurality of first series information into the i first physical programming units, respectively. In particular, the first concatenation information of the kth first entity programming unit of the i first entity programming units is used for recording the position of at least one other entity programming unit except the kth first entity programming unit of the i first entity programming units. In this exemplary embodiment, the locations of the other physical program cells include the location of the nth one of the i first physical program cells, where n is a positive integer greater than zero and less than k. In other words, in the present embodiment, the position of the nth first physical programming unit is located before the position of the kth first physical programming unit. However, the invention is not limited thereto, and in other embodiments, the position of the nth first physical programming unit may be located after the position of the kth first physical programming unit.

In particular, taking the example that the position of the nth first entity programming unit is located before the position of the kth first entity programming unit, please refer to the example of fig. 13B, assuming that the entity programming unit 830 (5) of fig. 13B is the kth first entity programming unit, the entity programming unit 830 (5) is the 4 th entity programming unit in the 5 (i.e., i = 5) entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7) for storing DATA 1-DATA 5, so the value of k is 4 in this example. In addition, each of the physical programming units 830 (1) -830 (2), 830 (4) -830 (5), and 830 (7) includes a field A1-A2. It should be noted that, although not shown in fig. 13B, each of the physical programming units 825 (1) -825 (2), 825 (4) -825 (5), 825 (7) further includes a redundant bit region, and the redundant bit region is used for storing encoded data of single frame coding. In particular, in the present embodiment, some or all of the bits of the previously reserved and unused bits in the redundant bit area of fig. 13A may be configured as the fields A1 to A2.

The bit (also referred to as the first bit) in the field A1 is used to record the position of the (k-1) th first physical program cell in the i first physical program cells. Therefore, the field A1 of the entity programming unit 830 (5) is used to record the position of the 3 rd entity programming unit (i.e., the entity programming unit 830 (4)) in the entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). In this embodiment, since the physical programming unit 830 (4) is the first physical erase unit from the physical programming unit 830 (5), the memory management circuit 702 records "1" to the field A1 of the physical programming unit 830 (5).

In addition, the bit (also called as the second bit) in the field A2 is used to record the position of the (k-2) th first physical program unit in the i first physical program units. Therefore, the field A2 of the physical programming unit 830 (5) is used to record the position of the 2 nd physical programming unit (i.e., the physical programming unit 830 (2)) in the physical programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). In this embodiment, since the physical program unit 830 (2) is the third physical erase unit before the physical program unit 830 (5), the memory management circuit 702 records "3" to the field A2 of the physical program unit 830 (5).

Again illustrated as physical programming unit 830 (7). The entity programming unit 830 (7) is the 5 th entity programming unit among the 5 entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7) for storing DATA 1-DATA 5, and the bit in the field A1 of the entity programming unit 830 (7) is used to record the position of the 4 th entity programming unit (i.e., the entity programming unit 830 (5)) among the entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). Since the physical program cell 830 (5) is the second physically erased cell from the physical program cell 830 (7), the memory management circuit 702 records "2" to the field A1 of the physical program cell 830 (7).

In addition, the field A2 of the entity programming unit 830 (7) is used to record the position of the 3 rd entity programming unit (i.e., the entity programming unit 830 (4)) in the entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). In this embodiment, since the physical program unit 830 (4) is the third physical erase unit before the physical program unit 830 (7), the memory management circuit 702 records "3" to the field A2 of the physical program unit 830 (7).

Based on the above, the recording manner of the fields A1 to A2 of the entity programming units 830 (1) -830 (2), 830 (4) may be similar to the recording manner of the fields A1 to A2 of the entity programming unit 830 (5) (or the entity programming unit 830 (7)), and thus will not be described herein again. In particular, since there is no first physical program cell and no second physical program cell located in front of the physical program cell 830 (1) from the physical program cell 830 (1), the fields A1 and A2 of the physical program cell 830 (1) are filled with "0" respectively. In addition, since there is no second physical program cell located in front of the physical program cell 830 (2) from the physical program cell 830 (2), the field A2 of the physical program cell 830 (2) is filled with "0".

It should be noted that, in the foregoing example, the first concatenation information of a physical program unit is used to record the positions of the first and second physical program units located in front of the physical program unit from the physical program unit. However, the present invention is not limited thereto, and in practice, the number of positions of the physical program unit located in front of the physical program unit from the physical program unit to be recorded in the first concatenation information may be determined according to the algorithm of the multi-frame coding used.

In the example of fig. 13B, the memory management circuit 702 also writes a concatenation information (also referred to as a second concatenation information) into the physical programming unit 830 (8) of the encoded data ECC2. In particular, the second concatenation information is used for recording the position of the jth first entity programming unit in the i first entity programming units. Wherein j is a positive integer greater than zero and less than i + 1. In other words, in the present embodiment, the second concatenation information is used for recording the position of one (or some) of the i first physical program units.

Referring to the example of fig. 13B, the physical programming unit 830 (8) of fig. 13B is used for storing the encoded data ECC2. The physical programming unit 830 (8) includes fields A1-A2. In the present embodiment, the bit (also referred to as the third bit) in the field A1 of the physical program unit for storing the encoded data is used to record the position of the ith first physical program unit in the i first physical program units. Therefore, the field A1 of the entity programming unit 830 (8) is used to record the position of the 5 th entity programming unit (i.e., the entity programming unit 830 (7)) in the entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). In this embodiment, since the physical program cell 830 (7) is the first physical erase cell before the physical program cell 830 (8), the memory management circuit 702 records "1" to the field A1 of the physical program cell 830 (8).

In addition, the bit (also called as the fourth bit) in the field A2 of the physical program unit for storing the encoded data is used to record the position of the i-1 th first physical program unit in the i first physical program units. Therefore, the field A2 of the entity programming unit 830 (8) is used to record the position of the 4 th entity programming unit (i.e., the entity programming unit 830 (5)) in the entity programming units 830 (1) -830 (2), 830 (4) -830 (5), 830 (7). In this embodiment, since the physical program cell 830 (5) is the third physical erase cell before the physical program cell 830 (8), the memory management circuit 702 records "3" to the field A2 of the physical program cell 830 (8).

Based on the above, it is assumed that when reading the data in the physical programming unit 830 (1), the data read from the physical programming unit 830 (1) can be decoded first by using the redundant bits (not shown, for example, the encoded data of the single frame coding) in the physical programming unit 830 (1) for error detection and correction. However, when the decoding using the redundancy bits in the physical program unit 830 (1) fails, the memory management circuit 702 can read the fields A1-A2 of the physical program unit 830 (8) to know that the DATA DATA5 is stored in the physical program unit 830 (7), the DATA DATA4 is stored in the entity program unit 830 (5) by reading the fields A1-A2 of the entity program unit 830 (7), the DATA DATA3 is stored in the entity program unit 830 (4) by reading the fields A1-A2 of the entity program unit 830 (5), and the DATA DATA2 is stored in the entity program unit 830 (2) by reading the fields A1-A2 of the entity program unit 830 (4).

Thereafter, the memory management circuit 702 may read the encoded DATA ECC2 and the DATA2 to DATA5 stored in the physical programming units 830 (2), 830 (4) -830 (5), and 830 (7), and decode the encoded DATA ECC2 and the DATA2 to DATA5 to attempt to correct errors in the DATA stored in the physical programming unit 830 (1).

It should be noted that the format for recording data in the physical programming unit 830 (8) (i.e., the second physical programming unit) is the same as the format for recording data in each of the physical programming units 830 (1) -830 (2), 830 (4) -830 (5), and 830 (7). In this way, the complexity of algorithm design and the cost of hardware design can be reduced.

In addition, since the physical programming unit 830 (8) and the physical programming units 830 (1) -830 (2), 830 (4) -830 (5), and 830 (7) all belong to the same physical erase unit 830 (also referred to as the first physical erase unit), the time required for writing and reading the encoded data ECC2 can be reduced.

Referring to fig. 14, in step S1401, the memory management circuit 702 receives a plurality of data from the host system 11 and writes the data into the i first physical programming units, respectively. Where i is a positive integer greater than zero. In step S1403, the memory management circuit 702 performs multi-frame coding according to the data to generate coded data, and writes the coded data into the second physical programming unit. In step S1405, the memory management circuit 702 writes a plurality of first concatenation information associated with the encoded data into the i first physical programming units, respectively. The first concatenation information of the kth first entity programming unit of the i first entity programming units is used for recording the position of at least one other entity programming unit except the kth first entity programming unit of the i first entity programming units, wherein k is a positive integer greater than zero and less than i + 1. In step S1407, the memory management circuit 702 writes a second concatenation information into the second physical programming unit, wherein the second concatenation information is used to record the position of the jth first physical programming unit of the i first physical programming units. Wherein j is a positive integer greater than zero and less than i + 1.

In summary, the data writing method, the memory control circuit unit and the memory storage device of the invention can increase the bit number of the encoded data to improve the error checking and correcting capability of the encoded data. In addition, in the data writing method of the present invention, since the format of the physical programming unit for recording the data written by the host system is the same as the format of the physical programming unit for recording the encoded data, the complexity of algorithm design and the cost of hardware design can be reduced. In addition, in the data writing method of the present invention, since the encoded data is stored in the same physical erasure unit as the data used to generate the encoded data, the time required for writing and reading the encoded data can be reduced.

Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A data writing method is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps:

receiving a plurality of data from a host system and respectively writing the data into i first entity programming units in the entity programming units, wherein i is a positive integer greater than zero;

performing multi-frame encoding according to the plurality of data to generate encoded data, and writing the encoded data into a second entity programming unit of the plurality of entity programming units; and

writing a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information is used for recording positions of the plurality of data in the i first physical programming units.

2. The data writing method according to claim 1, wherein the first concatenation information of a kth first physical programming unit of the i first physical programming units is used to record a position of at least one other physical programming unit of the i first physical programming units except the kth first physical programming unit, where k is a positive integer greater than zero and less than i + 1.

3. The data writing method according to claim 2, wherein the locations of the other physical program cells include a location of an nth one of the i first physical program cells, where n is a positive integer greater than zero and less than k.

4. The data writing method according to claim 2, wherein the first concatenation information of the kth first physical programming unit includes at least one first bit and at least one second bit, the first bit is used for recording a position of a (k-1) th first physical programming unit of the i first physical programming units, the second bit is used for recording a position of a (k-2) th first physical programming unit of the i first physical programming units, and k is greater than 2.

5. The data writing method according to claim 1, wherein the step of performing the multi-frame encoding according to the plurality of data to generate the encoded data and writing the encoded data into the second physical program cell of the plurality of physical program cells comprises:

and writing second concatenation information into the second entity programming unit, wherein the second concatenation information is used for recording the position of a jth first entity programming unit in the i first entity programming units, and j is a positive integer larger than zero and smaller than i + 1.

6. The data writing method according to claim 5, wherein the second concatenation information includes at least a third bit and at least a fourth bit, the third bit is used for recording a position of an i-th first physical programming unit of the i first physical programming units, and the fourth bit is used for recording a position of an i-1-th first physical programming unit of the i first physical programming units, and i is greater than 1.

7. The data writing method according to claim 1, wherein a format for recording data in the second physical programming unit is the same as a format for recording data in each of the i first physical programming units.

8. The data writing method according to claim 1, wherein the i first physically programmed cells and the second physically programmed cells belong to a first physically erased cell of the plurality of physically erased cells.

9. A memory control circuit unit is used for a rewritable nonvolatile memory module, the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, and the memory control circuit unit comprises:

a host interface for coupling to a host system;

a memory interface for coupling to the rewritable non-volatile memory module; and

memory management circuitry coupled to the host interface and the memory interface,

wherein the memory management circuit is configured to receive a plurality of data from a host system and write the plurality of data into i first physical programming units of the plurality of physical programming units, respectively, wherein i is a positive integer greater than zero,

wherein the memory management circuit is further configured to perform multi-frame encoding according to the plurality of data to generate encoded data, and write the encoded data into a second physical programming unit of the plurality of physical programming units,

the memory management circuit is further configured to write a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information is used to record locations of the plurality of data in the i first physical programming units.

10. The memory control circuit unit of claim 9, wherein the first concatenation information of a kth first physical programming unit of the i first physical programming units is used to record a position of at least one other physical programming unit of the i first physical programming units except the kth first physical programming unit, wherein k is a positive integer greater than zero and less than i + 1.

11. The memory control circuit unit of claim 10, wherein the locations of the other physical program cells include a location of an nth first physical program cell of the i first physical program cells, where n is a positive integer greater than zero and less than k.

12. The memory control circuit unit of claim 10, wherein the first concatenation information of the k-th first physical program unit comprises at least one first bit and at least one second bit, the first bit is used for recording the position of a (k-1) -th first physical program unit of the i first physical program units and the second bit is used for recording the position of a (k-2) -th first physical program unit of the i first physical program units, and k is greater than 2.

13. The memory control circuit unit of claim 9, wherein in the operation of performing the multi-frame encoding according to the plurality of data to generate the encoded data and writing the encoded data into the second physical program unit of the plurality of physical program units,

the memory management circuit is further configured to write second concatenation information into the second entity programming unit, where the second concatenation information is used to record a position of a jth first entity programming unit of the i first entity programming units, where j is a positive integer greater than zero and less than i + 1.

14. The memory control circuit unit of claim 13, wherein the second concatenation information includes at least a third bit and at least a fourth bit, the third bit is used for recording a position of an i-th first physical programming unit of the i first physical programming units and the fourth bit is used for recording a position of an i-1-th first physical programming unit of the i first physical programming units, and i is greater than 1.

15. The memory control circuit unit of claim 9, wherein a format for recording data in the second physical programming unit is the same as a format for recording data in each of the i first physical programming units.

16. The memory control circuit unit of claim 9, wherein the i first physically programmed cells and the second physically programmed cells belong to a first physically erased cell of the plurality of physically erased cells.

17. A memory storage device, comprising:

a connection interface unit for coupling to a host system;

the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the entity erasing units is provided with a plurality of entity programming units; and

a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module,

wherein the memory control circuit unit is used for receiving a plurality of data from a host system and respectively writing the data into i first entity programming units in the entity programming units, wherein i is a positive integer larger than zero,

wherein the memory control circuit unit is further configured to perform multi-frame coding according to the plurality of data to generate coded data, and write the coded data into a second physical programming unit of the plurality of physical programming units,

the memory control circuit unit is further configured to write a plurality of first concatenation information related to the encoded data into the i first physical programming units, respectively, wherein the plurality of first concatenation information is used to record positions of the plurality of data in the i first physical programming units.

18. The memory storage device of claim 17, wherein the first concatenation information of a kth first physical program unit of the i first physical program units is used to record a position of at least one other physical program unit of the i first physical program units except the kth first physical program unit, wherein k is a positive integer greater than zero and less than i + 1.

19. The memory storage device of claim 18, wherein the locations of the other physical program cells include a location of an nth first physical program cell of the i first physical program cells, where n is a positive integer greater than zero and less than k.

20. The memory storage device of claim 18, wherein the first concatenation information of the kth first physical program unit comprises at least one first bit and at least one second bit, the first bit is used for recording the position of the (k-1) th first physical program unit of the i first physical program units, the second bit is used for recording the position of the (k-2) th first physical program unit of the i first physical program units, and k is greater than 2.

21. The memory storage device of claim 17, wherein in the operation of performing the multi-frame encoding according to the plurality of data to generate the encoded data and writing the encoded data to the second physical program cell of the plurality of physical program cells,

the memory control circuit unit is further configured to write second concatenation information into the second physical programming unit, where the second concatenation information is used to record a position of a jth first physical programming unit of the i first physical programming units, where j is a positive integer greater than zero and less than i + 1.

22. The memory storage device of claim 21, wherein the second concatenation information comprises at least one third bit and at least one fourth bit, the third bit is used for recording a position of an i-th one of the i first physical program units and the fourth bit is used for recording a position of an i-1-th one of the i first physical program units, and i is greater than 1.

23. The memory storage device of claim 17, wherein a format for recording data in the second physical programming unit is the same as a format for recording data in each of the i first physical programming units.

24. The memory storage device of claim 17, wherein the i first physically programmed cells and the second physically programmed cells belong to a first physically erased cell of the plurality of physically erased cells.