CN111653623A - Fin type transistor structure - Google Patents
Fin type transistor structure Download PDFInfo
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- CN111653623A CN111653623A CN202010563660.6A CN202010563660A CN111653623A CN 111653623 A CN111653623 A CN 111653623A CN 202010563660 A CN202010563660 A CN 202010563660A CN 111653623 A CN111653623 A CN 111653623A
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- layer
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- 239000004065 semiconductor Substances 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 6
- 239000010703 silicon Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 79
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 239000011229 interlayer Substances 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 229910003468 tantalcarbide Inorganic materials 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 2
- OQPDWFJSZHWILH-UHFFFAOYSA-N [Al].[Al].[Al].[Ti] Chemical compound [Al].[Al].[Al].[Ti] OQPDWFJSZHWILH-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910021324 titanium aluminide Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a fin type transistor structure, which comprises: the semiconductor device comprises a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; the side walls are formed on two sides of the grid structure; the top interface layer is formed at the top of the grid structure; the contact etching stop layer is arranged on the silicon substrate and the grid structure; and the stress layer is arranged on the contact etching stop layer. The invention is used for providing tensile stress for the channel region of the device, and improves the electron mobility, thereby improving the performance of the electronic device.
Description
Technical Field
The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a transistor structure and a method for fabricating the same.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. Technological advances in IC design and materials have resulted in several generations of ICs, each with smaller and more complex circuitry than the previous generation. In the course of IC development, functional density generally increases, while geometry decreases.
A transistor is a circuit element or component that is typically formed as part of semiconductor fabrication. A Field Effect Transistor (FET) is one type of transistor. Typically, a transistor includes a gate stack formed between a source region and a drain region.
Three-dimensional transistors with fin-shaped active regions generally require enhanced device performance as transistor scaling decreases. The three-dimensional FETs formed on the fin active region are also referred to as finfets. Finfets are designed with narrow widths for short channel control and reduced gate length to meet desired scaling. The fabrication of such finfets, such as the implementation of negative capacitance devices, to provide adequate performance is becoming increasingly challenging.
Meanwhile, in the FinFET, in the current process, a contact hole (CT) technology is a challenging difficulty in each technology node of a semiconductor integrated circuit, and is a key step for connecting a front-stage device and a back-stage metal connection line. The method needs low resistance similar to a back-end connecting line, ensures good connection with a front-end device, can not only not be etched enough to cause open circuit, but also controls the loss (loss) amount of metal silicide such as NiSi to prevent the metal silicide from being etched through (ETCH through) and further causing resistance increase and Junction leakage; NiSi is commonly used as a metal silicide in processes below the 45nm technology node. To solve this problem, the existing mature process in the CT process loop (loop) uses a Contact ETCH Stop Layer (CESL) as a transition layer.
However, with current devices, the stress in the channel region is insufficient, resulting in insufficient electron mobility and affecting the performance of the electronic device.
Disclosure of Invention
The invention aims to solve the technical problem that the stress of a device in a channel region is insufficient, so that the electron mobility is insufficient.
In order to solve the above technical problem, the present invention discloses a fin transistor structure, including: the semiconductor device comprises a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate; the side walls are formed on two sides of the grid structure; the top interface layer is formed at the top of the grid structure; the contact etching stop layer is arranged on the silicon substrate and the grid structure; and the stress layer is arranged on the contact etching stop layer.
Preferably, the gate structure includes a gate dielectric layer and a metal gate layer.
Preferably, the gate dielectric layer is a high dielectric constant gate insulator layer.
Preferably, the metal gate comprises one or more work function layers.
Preferably, an interlayer film is further formed between the gate structures.
The invention is used for providing tensile stress for the channel region of the device, and improves the electron mobility, thereby improving the performance of the electronic device.
Drawings
Fig. 1 is a schematic structural diagram of a fin transistor structure according to the present invention.
Description of the reference numerals
1 semiconductor substrate 2 sidewall
3 top interfacial layer 4 contact etch stop layer
5 stress layer 6 gate structure
61 gate dielectric layer 62 metal gate layer
621 first metal layer 622 second metal layer
623 third Metal layer 624 fourth Metal layer
625 fifth metal layer 63 cover layer
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment shown in fig. 1 discloses a fin-type transistor structure, which includes a semiconductor substrate 1, and a gate structure 6 formed on the semiconductor substrate 1. The side walls 2 are formed on two sides of the grid structure; a top interfacial layer 3 formed on top of the gate structure; the contact etching stop layer 4 is arranged on the silicon substrate and the grid structure; and the stress layer 5 is arranged on the contact etching stop layer.
The semiconductor substrate 1 may be a compound semiconductor of silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide and/or indium antimonide, or a combination thereof. The substrate 1 may comprise a buried layer, and/or an epitaxial semiconductor layer grown on top of it. The substrate 1 may also include doped regions, such as N-wells and P-wells, depending on the properties of the desired device. Doping the substrate 1 may be achieved by an ion implantation process, a diffusion process, an in-situ doping process, or a combination thereof.
The stress layer 5 is an oxide material based stress layer. Preferably, the stress layer is made of ZnS-SiO 2. The stress layer can provide tensile stress for a channel region of the device, so that the electron mobility is improved, and the performance of the electronic device is improved.
The gate structure 6 includes a gate dielectric layer 61 and a metal gate layer. The gate dielectric layer 61 is a high dielectric constant gate insulator layer. A capping layer 63 is disposed between the gate dielectric layer 61 and the plurality of metal gate layers, as shown, a first metal layer 621 is formed, and a gate electrode is formed by the second metal layer 622, the third metal layer 623, and the fourth metal layer 624. One or more deposition methods may be used to form the U-shaped gate dielectric layer 61, capping layer 63, and metal layer 62.
The metal gate layer may be a Work Function Metal (WFM) layer. The work function metal layer may be a p-type or n-type work function layer depending on the type of device (PMOS or NMOS) desired. The P-type workfunction metal layer comprises a metal having a sufficiently large effective workfunction and may comprise one or more of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), other suitable metals, or combinations thereof. The N-type work function metal layer comprises a metal having a sufficiently low effective work function and may comprise one or more of tantalum (Ta), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), other suitable metals, or combinations thereof.
Meanwhile, the first metal layer 621, the second metal layer 622, the third metal layer 623 and the fourth metal layer 624 may be four different work function metal layers (N-type or P-type) of the same type. Alternatively, the first metal layer 621, the second metal layer 622, and the third metal layer 623 may be three different work function metal layers, and the fourth metal layer 624 may be a bulk conductive layer. In some embodiments, the gate electrode may include additional work function metal layers and a bulk conductive layer.
A top interfacial layer 3 is formed on top of the gate structure. The top interfacial layer 3 may be selectively formed on and self-aligned to the upper surface of the gate electrode by an ALD deposition process.
The contact etch stop layer 4 is disposed on the silicon substrate and the gate structure, and the contact etch stop layer 4 is typically made of silicon nitride (SiN).
An interlayer film 7 is also formed between the gate structures. The interlayer film 7 may be formed using a deposition process such as spin coating, CVD process. The interlayer film 7 is generally formed of an oxide layer (oxide).
The present invention has been described in detail with reference to the specific embodiments, which are merely the preferred embodiments of the present invention, and the present invention is not limited to the embodiments discussed above. Obvious modifications or alterations based on the teachings of the present invention should also be considered to fall within the technical scope of the present invention. The foregoing detailed description is provided to disclose the best mode of practicing the invention, and also to enable a person skilled in the art to utilize the invention in various embodiments and with various alternatives for carrying out the invention.
Claims (5)
1. A fin-type transistor structure, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a grid structure is formed on the semiconductor substrate;
the side walls are formed on two sides of the grid structure;
the top interface layer is formed at the top of the grid structure;
the contact etching stop layer is arranged on the silicon substrate and the grid structure;
and the stress layer is arranged on the contact etching stop layer.
2. The fin-transistor structure of claim 1, wherein the gate structure comprises a gate dielectric layer and a metal gate layer.
3. The fin-transistor structure of claim 2, wherein the gate dielectric layer is a high-k gate insulator layer.
4. The fin-transistor structure of claim 2, wherein the metal gate includes one or more work function layers.
5. The fin-transistor structure of claim 1, wherein an interlayer film is further formed between the gate structures.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010563660.6A CN111653623A (en) | 2020-06-19 | 2020-06-19 | Fin type transistor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010563660.6A CN111653623A (en) | 2020-06-19 | 2020-06-19 | Fin type transistor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111653623A true CN111653623A (en) | 2020-09-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010563660.6A Pending CN111653623A (en) | 2020-06-19 | 2020-06-19 | Fin type transistor structure |
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| Country | Link |
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| CN (1) | CN111653623A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446761A (en) * | 2010-09-30 | 2012-05-09 | 中国科学院微电子研究所 | Method for manufacturing semiconductor structure |
| CN104900528A (en) * | 2015-04-13 | 2015-09-09 | 上海华力微电子有限公司 | Method for manufacturing FinFET structure by stress memorization technique |
| US20160056268A1 (en) * | 2014-08-21 | 2016-02-25 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device improving the process speed |
-
2020
- 2020-06-19 CN CN202010563660.6A patent/CN111653623A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446761A (en) * | 2010-09-30 | 2012-05-09 | 中国科学院微电子研究所 | Method for manufacturing semiconductor structure |
| US20160056268A1 (en) * | 2014-08-21 | 2016-02-25 | Samsung Electronics Co., Ltd. | Method for fabricating semiconductor device improving the process speed |
| CN104900528A (en) * | 2015-04-13 | 2015-09-09 | 上海华力微电子有限公司 | Method for manufacturing FinFET structure by stress memorization technique |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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| RJ01 | Rejection of invention patent application after publication | ||
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Application publication date: 20200911 |