CN111599879B - Pin感光器件及其制作方法、及显示面板 - Google Patents
Pin感光器件及其制作方法、及显示面板 Download PDFInfo
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Abstract
一种PIN感光器件,通过使用钼氧化物等具有价带能级介于本征半导体层和上层电极的价带能级之间的P型半导体层来取代传统的PIN光电二极体中的P型半导体层,使得不需要使用硼烷气体即可制备PIN光电二极体,并且利用P型半导体层与本征半导体层之间的价带能级差来运输位于价带中的电洞,进而不需要使用到薄膜晶体管中的有源层,使得PIN感光器件得以堆叠至薄膜晶体管上,降低显示面板开口率的损失。
Description
技术领域
本发明涉及感光技术领域,尤其涉及一种降低显示面板开口率的损失和无需通入硼烷气体的PIN感光器件及其制作方法、及显示面板。
背景技术
指纹识别技术已广泛应用于中小尺寸的面板中,尤其是屏下光学指纹识别技术由于具有低成本与结构相对简单的优势,各大厂商皆在积极开发。然而,屏下光学指纹识别模块包括有多个PIN感光器件,目前只能通过离子布 值并且搭配准分子激光退火以及快速热退火等高温制程的方式进行其中的N型半导体层和P型半导体层的制备,但是此种做法通常会使用到显示区域中的薄膜晶体管的有源层,使得所述多个PIN感光器件无法堆叠至薄膜晶体管上,造成了显示面板开口率的损失。并且,在制作P型半导体层时也会涉及到改造机台与增加硼烷气体管路和腔室等问题。因此,有必要提供一种降低显示面板开口率的损失和无需通入硼烷气体的PIN感光器件及其制作方法,以解决现有技术存在的问题。
发明内容
本发明的目的在于提供一种降低显示面板开口率的损失和无需通入硼烷气体的PIN感光器件及其制作方法、及显示面板,以解决现有技术存在的问题。
为实现上述目的,本发明第一方面提供一种PIN感光器件,其至少包括:
依序设置的下层电极、PIN光电二极体、以及上层电极,其中,所述PIN 光电二极体包括N型半导体层、本征半导体层、以及P型半导体层,并且所述 P型半导体层的价带能级介于所述本征半导体层和所述上层电极的价带能级之间。
可选地,所述P型半导体层的材料为钼氧化物(MoOx)、一氧化镍(NiO)、氧化石墨烯、以及PEDOT:PSS中的任一种。
本发明第二方面一种PIN感光器件的制作方法,其包括以下步骤:
在衬底基板上形成图案化的下层电极;
形成第一绝缘层覆盖于所述衬底基板和所述下层电极,并在所述第一绝缘层对应部份的所述下层电极处形成第一开孔;
对应所述第一开孔处依序形成图案化的N型半导体层与本征半导体层于所述下层电极上;
形成钝化层覆盖于上述结构,并在所述钝化层对应所述本征半导体层处形成第二开孔;
对应所述第二开孔处形成图案化的P型半导体层于所述本征半导体层上;以及
形成图案化的上层电极覆盖于所述P型半导体层,并且所述P型半导体层的价带能级介于所述本征半导体层和所述上层电极的价带能级之间。
可选地,所述第二开孔与所述第一开孔使用相同的光罩进行图案化。
可选地,对所述P型半导体层进行图案化的光罩与对所述N型半导体层与所述本征半导体层进行图案化的光罩相同。
进一步地,在所述形成图案化的上层电极覆盖于所述P型半导体层之前还包括:
形成第二绝缘层覆盖于上述结构,并在所述第二绝缘层对应所述P型半导体层处形成第三开孔。
可选地,所述第三开孔与所述第一开孔使用相同的光罩进行图案化。
进一步地,所述制作方法还包括:
形成所述第一开孔的同时,在所述第一绝缘层对应另一部份的所述下层电极处形成第一子开孔;
形成所述第二开孔的同时,在所述钝化层对应所述第一子开孔处形成第二子开孔;
形成所述第三开孔的同时,在所述第二绝缘层对应所述第一子开孔与所述第二子开孔处形成第三子开孔;以及
形成所述上层电极的同时,形成所述上层电极的材料形成所述PIN感光器件的阴极,并且所述阴极通过所述第一子开孔、所述第二子开孔、以及所述第三子开孔与所述下层极连接。
进一步地,所述对应所述第二开孔处形成图案化的P型半导体层于所述本征半导体层上之后还包括:
在所述第一绝缘层以及所述钝化层对应另一部份的所述下层电极处形成开孔;以及
形成所述上层电极的同时,形成所述上层电极的材料形成所述PIN感光器件的阴极,并且所述阴极通过所述开孔与所述下层极连接。
本发明第三方面提供一种显示面板,其包括具有多个薄膜晶体管的薄膜晶体管阵列基板以及多个所述PIN感光器件,所述多个PIN感光器件堆叠设置在所述薄膜晶体管上。
本发明通过使用钼氧化物等具有价带能级介于本征半导体层和上层电极的价带能级之间的P型半导体层来取代传统的PIN光电二极体中的P型半导体层,使得不需要使用硼烷气体即可制备PIN光电二极体,并且利用P型半导体层与本征半导体层之间的价带能级差来运输位于价带中的电洞,进而不需要使用到薄膜晶体管中的有源层,使得本发明的PIN感光器件得以堆叠至薄膜晶体管上,降低显示面板开口率的损失。再者,本发明所提供的两种PIN感光器件的制作方法有利于降低光罩数量以及材料的使用,进而减少制备成本。可见,本发明具有十足的利用性。
附图说明
图1为根据本发明第一实施例的PIN感光器件的示意图。
图2为根据本发明的PIN感光器件的原理示意图。
图3为根据本发明第一实施例的PIN感光器件的制作方法步骤示意图。
图4A-4G为根据本发明第一实施例的PIN感光器件的制作方法流程图。
图5为根据本发明第二实施例的PIN感光器件的制作方法步骤示意图。
图6A-6F为根据本发明第二实施例的PIN感光器件的制作方法的流程图。
具体实施方式
为使本发明的目的、技术方案及效果更加清楚、明确,以下参照附图并对本发明作进一步地详细说明。应当理解,此处所描述的具体实施例仅用以解释本发明,并不用于限定本发明。
以下各实施例的说明是参考附加的图示,用以例示本发明可用以实施的实施例。本发明所提到的方向用语仅是参考附加图式的方向。因此,使用的方向用语是用以说明及理解本发明,而非用以限制本发明。
请参照图1,图1为根据本发明第一实施例的PIN感光器件的示意图。所述 PIN感光器件包括衬底基板11以及依序设置于所述衬底基板11上的下层电极 12、PIN光电二极体14、以及上层电极17,其中所述PIN光电二极体14沿远离所述衬底基板11的方向依序包括有N型半导体层141、本征半导体层142、以及P型半导体层143,并且所述P型半导体层143的价带能级(valence band energy)介于所述本征半导体层142和所述上层电极17的价带能级之间。
在本实施例中,所述下层电极12优选地为非透光电极,其可以在形成薄膜晶体管(未图示)的栅极时同时形成,因此其材料可以选择钼(Mo)、钛(Ti)、钼铝合金(Mo/Al)、钛铝合金(Ti/Al)、或是钼铜合金(Mo/Cu)等导电性良好的材料。并且,所述下层电极12同时也具有防止来自背光源(未图示) 的光线对所述PIN光电二极体14产生漏电流的功效,因此其也作为遮光层使用。
在本实施例中,由于硅具有稳定的性质与取得容易等诸多优点,因此传统的PIN光电二极体中的P型半导体层、本征半导体层、以及N型半导体层的材料皆为硅(Silicon)。然而,传统的PIN光电二极体在制程上通常会采用多晶硅作为P型半导体层和/或N型半导体层的材料,以利光电流的传输,因此其会结合显示区域中的薄膜晶体管中经过准分子激光退火以及快速热退火等高温制程的有源层使用来形成多晶硅的P型半导体层或是N型半导体层,但这却使得传统的PIN感光器件无法堆叠至薄膜晶体管上,造成显示面板开口率的损失。再者,在制作P型半导体层时也会涉及到机台改造与增加硼烷气体管路和腔室等问题,除了增加制备器件的成本外,更有安全的疑虑。因此,本发明以硅作为N型半导体层141与本征半导体层142的材料,并且通过使用钼氧化物 (MoOx)取代传统的PIN光电二极体中的P型半导体层来达到降低显示面板开口率的损失和无需通入硼烷气体的功效。于一实施例中,可以根据不同的光电器件来选用PIN光电二极体的材料,例如锗(Germanium)具有对红外光强吸收的特性,因此其适用于如ToF(time-of-flight)等器件。
结合图2所示,图2为根据本发明的PIN感光器件的原理示意图。当光线照射到PIN光电二极体14时,其中的本征半导体层142的空乏区中产生多个电子/电洞对,并且电洞会经由P型半导体层143往上层电极17(在本实施例中作为PIN感光器件的阳极)的方向传输,电子则会经由N型半导体层141往下层电极12的方向传输,进而产生光电流。具体地,本发明优选地选用价带能级介于所述本征半导体层142和所述上层电极17的价带能级之间的P型半导体层143,使得电洞得以利用所述P型半导体层143与本征半导体142之间的价带能级差来输运,无需使用到由高温制程所形成的多晶硅来进行输运。进一步地,所述本征半导体层142可以为具有价带能级为-5.5电子伏特(eV)的非晶硅,所述上层电极17可以为具有价带能级约为-5eV的铟锡氧化物(ITO),因此本发明优选地采用价带能级为-5.2eV的钼氧化物,利用钼氧化物与非晶硅之间的价带能级差来运输位于价带中的电洞,如图2所示。可以理解的是,仅要是价带能级介于所述本征半导体层142和所述上层电极17的价带能级之间的材料皆可作为P型半导体层143,例如一氧化镍(NiO)、氧化石墨烯、PEDOT:PSS 等,而所述上层电极17优选地为透光电极,使得光线照射时可以穿透所述上层电极17达到所述PIN光电二极体14。
基于上述,PIN光电二极体14得以不需要使用硼烷气体来制备其中的P型半导体层143,并且由于不需要使用到薄膜晶体管中的有源层,因此本发明的 PIN感光器件得以弹性地堆叠至薄膜晶体管上。由此可知,本发明可以应用于一种显示面板(例如有机发光二极管显示面板或是液晶显示面板等),并且所述显示面板包括具有多个薄膜晶体管(thin-filmtransistor,TFT)的薄膜晶体管阵列基板以及多个所述PIN感光器件,所述多个PIN感光器件可以堆叠设置在所述薄膜晶体管上。
衬底基板11可以为薄膜晶体管阵列基板。
结合上述与图3和图4A-4G所示,图3为根据本发明第一实施例的PIN感光器件的制作方法步骤示意图,图4A-4G为根据本发明第一实施例的PIN感光器件的制作方法流程图。所述制作方法包括以下步骤:
步骤S11(如图4A):在衬底基板11上形成图案化的下层电极12。
步骤S12(如图4B):形成第一绝缘层13覆盖于所述衬底基板11和所述下层电极12,并在所述第一绝缘层13对应部份的所述下层电极12处形成第一开孔131。
在该步骤中,所述第一绝缘层13可以与薄膜晶体管的栅极绝缘层同时形成,并且其材料可以为氧化硅(SiOx)、氧化氮(SiNx)、氮氧化硅(SiOxNy)、以及氧化硅/氧化氮(SiOx/SiNx)等。
在该步骤中,形成所述第一过孔131的同时,在所述第一绝缘层13对应另一部份的所述下层电极12处形成第一子开孔(未标示)。
步骤S13(如图4C):对应所述第一开孔131处依序形成图案化的N型半导体层141与本征半导体层142于所述下层电极12上。
在该步骤中,优选地以原地的(in-situ)方式连续地先形成整面的(blanket) N型半导体层与本征半导体层后,再通过黄光与蚀刻制程在对应所述第一开孔 131处形成图案化的所述N型半导体层141与所述本征半导体层142。
步骤S14(如图4D):形成钝化层15覆盖于上述结构,并在所述钝化层15 对应所述本征半导体层142处形成第二开孔151。
在该步骤中,所述钝化层15的材料可以为氧化硅(SiOx)、氧化氮(SiNx)、氮氧化硅(SiOxNy)、以及氧化硅/氧化氮(SiOx/SiNx)等。
在该步骤中,所述第二开孔151与所述第一开孔131使用相同的光罩进行黄光与蚀刻制程。
在该步骤中,形成所述第二开孔151的同时,在所述钝化层15对应所述第一子开孔处形成第二子过孔(未标示)。
步骤S15(如图4E):对应所述第二开孔151处形成图案化的P型半导体层 143于所述本征半导体层142上。
在该步骤中,对所述P型半导体层143进行图案化的光罩与对所述N型半导体层141与所述本征半导体层142进行图案化的光罩相同。
步骤S16(如图4F):形成第二绝缘层16覆盖于上述结构,并在所述第二绝缘层16对应所述P型半导体层处形成第三开孔161。
在该步骤中,所述第二绝缘层16的材料可以为氧化硅(SiOx)、氧化氮(SiNx)、氮氧化硅(SiOxNy)、以及氧化硅/氧化氮(SiOx/SiNx)等。
在该步骤中,所述第三开孔161与所述第一开孔131使用相同的光罩进行曝光与蚀刻制程。
在该步骤中,形成所述第三开孔161的同时,在所述第二绝缘层16对应所述第一子开孔与所述第二子开孔处形成第三子开孔(未标示)。
步骤S17(如图4G):形成图案化的上层电极17覆盖于所述P型半导体层 143。
在该步骤中,覆盖于所述P型半导体层143的所述上层电极17作为PIN感光器件的阳极,用以接收电洞。在形成所述上层电极17的同时,形成所述上层电极17的材料形成所述PIN感光器件的阴极(未标示),并且所述阴极通过所述第一子开孔、所述第二子开孔、以及所述第三子开孔与所述下层极12连接,使电子得以经由N型半导体层141与所述下层电极12往所述阴极的方向传输。
结合上述与图5和图6A-6F所示,图5为根据本发明第二实施例的PIN感光器件的制作方法步骤示意图,图6A-6F为根据本发明第二实施例的PIN感光器件的制作方法的流程图。所述制作方法包括以下步骤:
步骤S21(如图6A):在衬底基板21上形成图案化的下层电极22。
步骤S22(如图6B):形成第一绝缘层23覆盖于所述衬底基板21和所述下层电极22,并在所述第一绝缘层23对应部份的所述下层电极22处形成第一开孔231。
步骤S23(如图6C):对应所述第一开孔231处依序形成图案化的N型半导体层241与本征半导体层242于所述下层电极22上。
步骤S24(如图6D):形成钝化层25覆盖于上述结构,并在所述钝化层25 对应所述本征半导体层242处形成第二开孔251。
步骤S25(如图6E):对应所述第二开孔251处形成图案化的P型半导体层 242于所述本征半导体层241上。
在该步骤中,在形成所述P型半导体层242于所述本征半导体层241上之后,在所述第一绝缘层23以及所述钝化层25对应另一部份的所述下层电极22 处形成开孔。
步骤S26(如图6F):形成图案化的上层电极27覆盖于所述P型半导体层 243。
在该步骤中,覆盖于所述P型半导体层243的所述上层电极27作为PIN感光器件的阳极,用以接收电洞。在形成所述上层电极27的同时,形成所述上层电极27的材料形成所述PIN感光器件的阴极(未标示),并且所述阴极通过所述开孔与所述下层极22连接,使电子得以经由N型半导体层241与所述下层电极22往所述阴极的方向传输。
在本实施例中,其与本发明的第一实施例的制作方法的差别在于步骤S21 到步骤S26所使用的光罩皆不同,并且省去沉积与图案化第二绝缘层的步骤。
本发明通过使用钼氧化物等具有价带能级介于本征半导体层和上层电极的价带能级之间的P型半导体层来取代传统的PIN光电二极体中的P型半导体层,使得不需要使用硼烷气体即可制备PIN光电二极体,并且利用P型半导体层与本征半导体层之间的价带能级差来运输位于价带中的电洞,进而不需要使用到薄膜晶体管中的有源层,使得本发明的PIN感光器件得以堆叠至薄膜晶体管上,降低显示面板开口率的损失。再者,本发明所提供的两种PIN感光器件的制作方法有利于降低光罩数量以及材料的使用,进而减少制备成本。可见,本发明具有十足的利用性。
虽然本发明已以优选实施例揭露如上,但上述优选实施例并非用以限制本发明,本领域的普通技术人员,在不脱离本申请的范围内,均可作各种更动与润饰,因此本申请的保护范围以权利要求界定的范围为准。
Claims (9)
1.一种PIN感光器件,其特征在于,其至少包括:
依序设置的下层电极、PIN光电二极体、以及上层电极,其中,所述PIN光电二极体包括N型半导体层、本征半导体层、以及P型半导体层,并且所述P型半导体层的价带能级介于所述本征半导体层和所述上层电极的价带能级之间,
其中所述N型半导体层与所述本征半导体层的材料为硅,而所述P型半导体层的材料为钼氧化物。
2.一种PIN感光器件的制作方法,其特征在于,其包括以下步骤: 在衬底基板上形成图案化的下层电极;
形成第一绝缘层覆盖于所述衬底基板和所述下层电极,并在所述第一绝缘层对应部份的所述下层电极处形成第一开孔;
对应所述第一开孔处依序形成图案化的N型半导体层与本征半导体层于所述下层电极上;
形成钝化层覆盖于上述结构,并在所述钝化层对应所述本征半导体层处形成第二开孔;
对应所述第二开孔处形成图案化的P型半导体层于所述本征半导体层上;以及
形成图案化的上层电极覆盖于所述P型半导体层,并且所述P型半导体层的价带能级介于所述本征半导体层和所述上层电极的价带能级之间,
其中所述N型半导体层与所述本征半导体层的材料为硅,而所述P型半导体层的材料为钼氧化物。
3.根据权利要求2所述的制作方法,其特征在于:所述第二开孔与所述第一开孔使用相同的光罩进行图案化。
4.根据权利要求2所述的制作方法,其特征在于:对所述P型半导体层进行图案化的光罩与对所述N型半导体层与所述本征半导体层进行图案化的光罩相同。
5.根据权利要求2所述的制作方法,其特征在于,在所述形成图案化的上层电极覆盖于所述P型半导体层之前还包括:
形成第二绝缘层覆盖于上述结构,并在所述第二绝缘层对应所述P型半导体层处形成第三开孔。
6.根据权利要求5所述的制作方法,其特征在于:所述第三开孔与所述第一开孔使用相同的光罩进行图案化。
7.根据权利要求5所述的制作方法,其特征在于,其还包括:
形成所述第一开孔的同时,在所述第一绝缘层对应另一部份的所述下层电极处形成第一子开孔;
形成所述第二开孔的同时,在所述钝化层对应所述第一子开孔处形成第二子开孔;
形成所述第三开孔的同时,在所述第二绝缘层对应所述第一子开孔与所述第二子开孔处形成第三子开孔;以及
形成所述上层电极的同时,形成所述上层电极的材料形成所述PIN感光器件的阴极,并且所述阴极通过所述第一子开孔、所述第二子开孔、以及所述第三子开孔与所述下层极连接。
8.根据权利要求2所述的制作方法,其特征在于,所述对应所述第二开孔处形成图案化的P型半导体层于所述本征半导体层上之后还包括:
在所述第一绝缘层以及所述钝化层对应另一部份的所述下层电极处形成开孔;以及
形成所述上层电极的同时,形成所述上层电极的材料形成所述PIN感光器件的阴极,并且所述阴极通过所述开孔与所述下层电极连接。
9.一种显示面板,其包括具有多个薄膜晶体管的薄膜晶体管阵列基板以及多个根据权利要求1所述的PIN感光器件,所述多个PIN感光器件堆叠设置在所述薄膜晶体管上。
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