CN111555416B - Battery charge-discharge control circuit - Google Patents
Battery charge-discharge control circuit Download PDFInfo
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- CN111555416B CN111555416B CN202010655846.4A CN202010655846A CN111555416B CN 111555416 B CN111555416 B CN 111555416B CN 202010655846 A CN202010655846 A CN 202010655846A CN 111555416 B CN111555416 B CN 111555416B
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- 238000007600 charging Methods 0.000 claims abstract description 125
- 238000007599 discharging Methods 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 14
- 238000001514 detection method Methods 0.000 claims description 28
- 238000005070 sampling Methods 0.000 claims description 20
- 230000000630 rising effect Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 238000010277 constant-current charging Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 12
- 238000000034 method Methods 0.000 description 10
- 238000010280 constant potential charging Methods 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 2
- 229910052744 lithium Inorganic materials 0.000 description 2
- 238000010281 constant-current constant-voltage charging Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000003912 environmental pollution Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0063—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries with circuits adapted for supplying loads from the battery
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Abstract
The invention relates to the technical field of electronics, and provides a battery charging and discharging control circuit, which comprises a charging control module, a capacitor, a first power transistor, a second power transistor, an inductor, a third power transistor, a fourth power transistor and a discharging control module, wherein the capacitor is connected with the first power transistor; the charging control module is used for detecting and controlling the on and off of the first power transistor and the second power transistor according to the charging current when the adapter is connected so as to charge the battery at a constant current; detecting and controlling the on and off of the first power transistor and the second power transistor according to the voltage of the battery so as to charge the battery at a constant voltage; the discharge control module is used for detecting and controlling the on and off of the third power transistor and the fourth power transistor according to the discharge voltage when the electric equipment is connected or the electric equipment is floated so as to keep the discharge voltage stable. The invention solves the problems of low battery charging efficiency and easy heating when the prior art adopts a wire control mode for charging.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a battery charging and discharging control circuit.
Background
In the field of 1.5V power supply, the prior art mainly uses disposable batteries. The disposable battery has a serious problem of environmental pollution and cannot be reused. In order to solve the problem, a method of using a rechargeable, energy-saving and environment-friendly battery to replace a disposable battery is urgent and is also in force.
Fig. 1 is a block diagram showing a basic structure of a conventional battery charge/discharge control circuit. As shown in fig. 1, the battery charging/discharging control circuit includes a rechargeable battery B0, a power transistor M0, a power transistor M1, a power transistor M2, an energy storage inductor L0, a filter capacitor C0, an input/output interface VAP, a charging control module 01, and a discharging control module 02. When the VAP is connected to the 5V adapter, the charging control module 01 works to charge the rechargeable battery B0, which is a charging process of replacing a disposable battery with the rechargeable battery. When the VAP is floated or connected to an application device, the discharge control module 02 operates to make the VAP output 1.5V voltage, which is a discharge process in which a rechargeable battery replaces a disposable battery.
Fig. 2 is a schematic structural diagram of the charging control module 01. As shown in fig. 2, the charging control module 01 includes a charging current sampling module 11, a bandgap reference module 12, a first operational transconductance amplifier 13, a second operational transconductance amplifier 14, and a third operational transconductance amplifier 15. The output of the third operational transconductance amplifier 15 is connected to the gate of the power transistor M0 in fig. 1.
In fig. 1, the charging control module 01 is divided into two stages, a constant current charging stage and a constant voltage charging stage, according to the battery voltage. Corresponding to fig. 2, the charging current sampling module 11, the first operational transconductance amplifier 13, and the third operational transconductance amplifier 15 form a constant current charging loop; the second operational transconductance amplifier 14 and the third operational transconductance amplifier 15 constitute a constant-voltage charging loop.
During the charging process, when the charging current decreases, the output signal vsense of the charging current sampling module 11 decreases proportionally, the output signal otaout1 of the first operational transconductance amplifier 13 decreases, and the output signal Pgate of the third operational transconductance amplifier 15 decreases, thereby causing the current of the power transistor M0 in fig. 1 to increase, and maintaining the output signal vsense of the charging current sampling module 11 equal to the threshold voltage vref 1. By setting the threshold voltage vref1, a constant charging current can be obtained, and constant current charging control is realized.
When the BAT voltage of the rechargeable battery B0 rises, the BAT voltage feedback signal BAT _ fb rises proportionally, the output signal otaout2 of the second operational transconductance amplifier 14 rises, and the output signal Pgate of the third operational transconductance amplifier 15 rises, so that the charging current of the power transistor M0 in fig. 1 drops. When the feedback signal BAT _ fb of the BAT voltage of the rechargeable battery B0 is equal to the threshold voltage vref2, the charging current drops to 0, the charging is turned off, and the constant-voltage charging control is realized.
As can be seen, the conventional charging control module 01 adopts a linear control manner to implement constant-current charging and constant-voltage charging. During the charging process, the discharging control module 02 stops working, and the power transistor M1 and the power transistor M2 are completely turned off; the charging control module 01 operates to control the gate terminal of the power transistor M0 according to the magnitude of the BAT voltage, so that the power transistor M0 operates in three states, namely, a turn-off region, a sub-threshold region and a saturation region. The efficiency formula is as follows:
in the formula,
which represents the current of the positive electrode of the battery,
which is representative of the adapter current flow,
and
are substantially equal.
Representing the adapter voltage, typically 5V.
Represents the battery voltage when
At 3V, the charging efficiency is only 60%. The chip is easy to generate heat due to low-efficiency charging, the performance of the chip is influenced, and potential safety hazards exist.
Disclosure of Invention
The invention provides a battery charging and discharging control circuit, which aims to solve the problems of low battery charging efficiency and easiness in heating when charging is carried out in a wire control mode in the prior art.
The invention is realized in this way, a battery charge and discharge control circuit includes:
the power supply comprises a charging control module, a capacitor, a first power transistor, a second power transistor, an inductor, a third power transistor, a fourth power transistor and a discharging control module;
the first input end of the charging control module, the first end of the first power transistor, the first end of the capacitor and the input end of the discharging control module are connected to an input/output interface of the battery charging and discharging control circuit in common, and the second end of the capacitor is grounded;
the second input end of the charging control module is connected with the positive electrode of the battery;
a first output end of the charging control module is connected with a second end of the first power transistor, and a second output end of the charging control module is connected with a first end of the second power transistor;
a first output end of the discharge control module is connected with a first end of the third power transistor, and a second output end of the discharge control module is connected with a first end of the fourth power transistor;
a common joint point between the third end of the first power transistor and the second end of the second power transistor is connected with the first end of the inductor;
a common junction point between the second end of the third power transistor and the second end of the fourth power transistor is connected with the second end of the inductor;
the third end of the third power transistor is connected with the positive electrode of the battery;
the third end of the second power transistor, the third end of the fourth power transistor and the third output end of the charging control module are connected to the negative electrode of the battery in common, and the negative electrode of the battery is grounded;
the discharge control module is used for controlling the third power transistor to be completely turned on and the fourth power transistor to be completely turned off when an input/output interface of the battery charge/discharge control circuit is connected with an adapter; the charging control module is used for detecting charging current when an input/output interface of the battery charging/discharging control circuit is connected with an adapter, and controlling the conduction and the disconnection of the first power transistor and the second power transistor according to the charging current so as to charge a battery at a constant current; detecting battery voltage, and controlling the on and off of the first power transistor and the second power transistor according to the battery voltage so as to charge the battery at a constant voltage;
the charging control module is used for controlling the first power transistor to be completely switched on and the second power transistor to be completely switched off when an input/output interface of the battery charging and discharging control circuit is connected with an electric device or floated; the discharge control module is used for detecting a discharge voltage when an input/output interface of the battery charge/discharge control circuit is connected with an electric device or is floated, and controlling the connection and disconnection of the third power transistor and the fourth power transistor according to the discharge voltage so as to keep the discharge voltage stable.
Optionally, the second power transistor and the fourth power transistor are N-channel power transistors, and the first power transistor and the third power transistor are P-channel power transistors.
Optionally, the first power transistor, the second power transistor, the third power transistor, and the fourth power transistor are all N-channel power transistors.
Optionally, the charging control module comprises:
a signal detection circuit and a logic control circuit;
the first input end of the signal detection circuit is connected with the input and output interface of the battery charge and discharge control circuit, the second input end of the signal detection circuit is connected with the anode of the battery, and the output end of the signal detection circuit is connected with the input end of the logic control circuit;
a first output end of the logic control circuit is connected with a second end of the first power transistor, and a second output end of the logic control circuit is connected with a first end of the second power transistor;
the signal detection circuit is used for detecting charging current through a first input end/battery voltage through a second input end, generating a first carrier signal according to a difference value between the charging current/battery voltage and a preset threshold value, and sending the first carrier signal to the logic control circuit;
the logic control circuit is used for generating a pulse width modulation signal according to the first carrier signal and outputting a low level to the first power transistor and outputting a high level to the second power transistor when the pulse width modulation signal is at a high level;
the logic control circuit is further used for generating a clock signal and outputting a high level to the first power transistor and outputting a low level to the second power transistor according to the rising edge of the clock signal.
Optionally, the signal detection circuit comprises:
the band-gap reference circuit comprises a sampling circuit, a first transconductance amplifier, a first band-gap reference circuit and a second transconductance amplifier;
the input end of the sampling circuit is connected with the input and output interface of the battery charge and discharge control circuit, and the output end of the sampling circuit is connected with the positive phase input end of the first transconductance amplifier;
a first reference voltage output end of the first bandgap reference circuit is connected with an inverting input end of the first transconductance amplifier, and a second reference voltage output end of the first bandgap reference circuit is connected with an inverting input end of the second transconductance amplifier;
the positive phase input end of the second transconductance amplifier is connected with the positive electrode of the battery;
a common junction point between the output end of the first transconductance amplifier and the output end of the second transconductance amplifier is used as the output end of the signal detection circuit;
the first bandgap reference circuit is used for providing a first reference voltage for the first transconductance amplifier and providing a second reference voltage for the second transconductance amplifier;
the sampling circuit is used for detecting a charging current and outputting a voltage signal proportional to the charging current to the first transconductance amplifier, and the first transconductance amplifier is used for amplifying a deviation between the voltage signal and a first reference voltage to obtain a first carrier signal;
the second transconductance amplifier is used for detecting the battery voltage and amplifying the deviation between the battery voltage and a second reference voltage to obtain a first carrier signal.
Optionally, the logic control circuit comprises:
the first logic controller comprises a first operational amplifier, a first comparator, a first oscillator and a first capacitor;
the positive phase input end of the first operational amplifier is connected with a third reference voltage, and the negative phase input end of the first operational amplifier is connected with the output end of the signal detection circuit;
the inverting input end of the first comparator is connected with the output end of the first operational amplifier, and the non-inverting input end of the first comparator is connected with the first output end of the first oscillator;
the output end of the first comparator is connected with the first input end of the first logic controller;
a second output end of the first oscillator is connected with a second input end of the first logic controller;
a first output end of the first logic controller is connected with a second end of the first power transistor, and a second output end of the first logic controller is connected with a first end of the second power transistor;
the first operational amplifier is used for amplifying a difference value between the first carrier signal and a third reference voltage to obtain a second carrier signal; the first oscillator outputs a first ramp modulation signal through a first output end; the first comparator is used for comparing the second carrier signal with the first ramp modulation signal and generating a pulse width modulation signal according to the comparison result and supplying the pulse width modulation signal to the first logic controller; the first oscillator is further used for generating a clock signal and providing the clock signal to the first logic controller; the first logic controller is used for generating a first control signal and a second control signal which are opposite to each other according to the pulse width modulation signal and the clock signal;
wherein the first control signal is provided to the first power transistor, the first power transistor is turned on when the first control signal is at a high level, and the first power transistor is turned off when the first control signal is at a low level; the second control signal is provided to the second power transistor, the second power transistor is turned on when the second control signal is at a high level, and the second power transistor is turned off when the second control signal is at a low level.
Optionally, the discharge control module includes:
the second band-gap reference module, the second operational amplifier, the second comparator, the second oscillator and the second logic controller;
the positive phase input end of the second operational amplifier is connected with the output end of the second band-gap reference module, and the negative phase input end of the second operational amplifier is connected with the input/output interface of the battery charge/discharge control circuit;
the inverting input end of the second comparator is connected with the output end of the second operational amplifier, and the non-inverting input end of the second comparator is connected with the first output end of the second oscillator;
the output end of the second comparator is connected with the first input end of the second logic controller;
a second output end of the second oscillator is connected with a second input end of the second logic controller;
a first output end of the second logic controller is connected with a first end of the third power transistor, and a second output end of the second logic controller is connected with a first end of the fourth power transistor;
the second operational amplifier is used for detecting a discharge voltage and amplifying a difference value between the discharge voltage and a fourth reference voltage to obtain a third carrier signal; the second oscillator is used for outputting a second ramp modulation signal through a first output end, and the second comparator is used for comparing the third carrier signal with the second ramp modulation signal and generating a pulse width modulation signal according to the comparison result to be supplied to the second logic controller; the second oscillator is further used for generating a clock signal and providing the clock signal to the second logic controller; the second logic controller is used for generating a third control signal and a fourth control signal which are opposite to each other according to the pulse width modulation signal and the clock signal;
wherein the third control signal is provided to the third power transistor, the third power transistor is turned on when the third control signal is at a high level, and the third power transistor is turned off when the third control signal is at a low level; the fourth control signal is provided to the fourth power transistor, the fourth power transistor is turned on when the fourth control signal is at a high level, and the fourth power transistor is turned off when the fourth control signal is at a low level.
The battery charging and discharging control circuit provided by the invention is additionally provided with a power transistor on the basis of the prior art and combines a switch type charging and discharging mode. When an input/output interface of the battery charge/discharge control circuit is connected with an adapter, a third power transistor is completely switched on, a fourth power transistor is completely switched off, the charge control module controls the switching on and off of the first power transistor and the second power transistor according to a charge current so as to perform constant-current charging on a battery, and controls the switching on and off of the first power transistor and the second power transistor according to the voltage of the battery so as to perform constant-voltage charging on the battery; when the input/output interface of the battery charge/discharge control circuit is connected with an electric device or is floated, the first power transistor is completely switched on, the second power transistor is completely switched off, and the discharge control module controls the third power transistor and the fourth power transistor to be switched on and off according to the discharge voltage so as to keep the discharge voltage stable; therefore, the energy loss in the whole charging process is mainly the switching loss and the conduction loss of the power tube, and the charging efficiency of the battery is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a circuit diagram of a conventional battery charging/discharging control circuit;
FIG. 2 is a schematic circuit diagram of a prior art charge control module;
fig. 3 is a schematic circuit diagram of a battery charging/discharging control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a charge control module according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a signal detection circuit and a logic control circuit according to an embodiment of the present invention;
fig. 6 is a timing diagram of current waveforms of the clock signal clk, the second carrier signal eaout1, the first ramp modulation signal vramp1, the pulse width modulation signal pwm1, the first control signal Hgate1, the second control signal Lgate1, and the inductor L according to another embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a discharge control module according to an embodiment of the present invention;
fig. 8 is a timing diagram of current waveforms of the clock signal clk, the second carrier signal eaout2, the first ramp modulation signal vramp2, the pulse width modulation signal pwm2, the first control signal Hgate2, the second control signal Lgate2, and the inductor L according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The battery charging and discharging control circuit provided by the invention is additionally provided with a power transistor on the basis of the prior art and combines a switch type charging and discharging mode. When an input/output interface of the battery charge/discharge control circuit is connected with an adapter, the charge control module controls the on/off of the first power transistor and the second power transistor according to a charge current so as to charge a battery at a constant current, and controls the on/off of the first power transistor and the second power transistor according to the voltage of the battery so as to charge the battery at a constant voltage; when the input/output interface of the battery charge/discharge control circuit is connected with an electric device or is floated, the discharge control module controls the third power transistor and the fourth power transistor to be switched on and off according to the discharge voltage so as to keep the discharge voltage stable; therefore, the energy loss in the whole charging and discharging process is mainly the switching loss and the conduction loss of the power tube, and the charging efficiency of the battery is greatly improved.
Fig. 3 is a schematic structural diagram of a battery charge and discharge control circuit according to an embodiment of the present invention. As shown in fig. 3, the battery charging and discharging control circuit includes a charging control module 10, a capacitor C, a first power transistor M1, a second power transistor M2, an inductor L, a third power transistor M3, a fourth power transistor M4, and a discharging control module 20;
a first input end of the charging control module 10, a first end of the first power transistor M1, a first end of the capacitor C, and an input end of the discharging control module 20 are commonly connected to an input/output interface VAP of the battery charging/discharging control circuit, and a second end of the capacitor C is grounded;
a second input end of the charging control module 10 is connected with a battery anode;
a first output terminal of the charging control module 10 is connected to the second terminal of the first power transistor M1, and a second output terminal is connected to the first terminal of the second power transistor M2;
a first output terminal of the discharge control module 20 is connected to a first terminal of the third power transistor M3, and a second output terminal is connected to a first terminal of the fourth power transistor M4;
a common junction point between the third terminal of the first power transistor M1 and the second terminal of the second power transistor M2 is connected to the first terminal of the inductor L;
a common junction point between the second terminal of the third power transistor M3 and the second terminal of the fourth power transistor M4 is connected to the second terminal of the inductor L;
the third end of the third power transistor M3 is connected with the positive electrode of the battery;
the third terminal of the second power transistor M2, the third terminal of the fourth power transistor M4 and the third output terminal of the charging control module 10 are connected to the negative electrode of the battery in common, and the negative electrode of the battery is grounded;
the discharge control module 20 is configured to control the third power transistor M3 to be fully turned on and the fourth power transistor M4 to be fully turned off when the input/output interface of the battery charge/discharge control circuit is connected to an adapter; the charging control module 10 is configured to detect a charging current when an input/output interface of the battery charging/discharging control circuit is connected to an adapter, and control the first power transistor M1 and the second power transistor M2 to be turned on and off according to the charging current, so as to perform constant-current charging on a battery; and detecting a battery voltage, controlling the on and off of the first power transistor M1 and the second power transistor M2 according to the battery voltage, so as to charge the battery with a constant voltage;
the charging control module 10 is configured to control the first power transistor M1 to be fully turned on and the second power transistor M2 to be fully turned off when the input/output interface of the battery charging/discharging control circuit is connected to an electric device or is floated; the discharge control module 20 is configured to detect a discharge voltage when the input/output interface of the battery charge/discharge control circuit is connected to an electrical device or is floating, and control the third power transistor M3 and the fourth power transistor M4 to be turned on and off according to the discharge voltage, so that the discharge voltage is kept stable.
Here, as a preferred example of the present invention, the first power transistor M1 and the third power transistor M3 may be P-channel power transistors, and the second power transistor M2 and the fourth power transistor M4 may be N-channel power transistors. At this time, the first terminal of the first power transistor M1 is a source, the second terminal is a gate, and the third terminal is a drain; the first end of the third power transistor M3 is a grid electrode, the second end is a drain electrode, and the third end is a source electrode; the first end of the second power transistor M2 is a grid electrode, the second end is a drain electrode, and the third end is a source electrode; the first terminal of the fourth power transistor M4 is a gate, the second terminal is a drain, and the third terminal is a source.
As another preferred example of the present invention, the first power transistor M1, the second power transistor M2, the third power transistor M3 and the fourth power transistor M4 are all N-channel power transistors. At this time, the first terminal of the first power transistor M1 is a drain, the second terminal is a gate, and the third terminal is a source; the first end of the third power transistor M3 is a grid electrode, the second end is a source electrode, and the third end is a drain electrode; the first end of the second power transistor M2 is a grid electrode, the second end is a drain electrode, and the third end is a source electrode; the first terminal of the fourth power transistor M4 is a gate, the second terminal is a drain, and the third terminal is a source.
When the input/output interface VAP of the battery charge/discharge control circuit is connected to the 5V adapter, the discharge control module 20 controls the third power transistor M3 to be completely turned on and the fourth power transistor M4 to be completely turned off, and the charge control module 10 operates. The charging control module 10 is configured to charge the rechargeable battery by continuously controlling the first power transistor M1 and the second power transistor M2 to be alternately turned on and off.
When the input/output interface VAP of the battery charge/discharge control circuit is floated or connected to an electric device, the charge control module 10 controls the first power transistor M1 to be completely turned on and the second power transistor M2 to be completely turned off, and the discharge control module 20 operates. The discharge control module 20 controls the third power transistor M3 and the fourth power transistor M4 to alternately turn on and off, so that the input/output interface VAP outputs a stable voltage, such as 1.5V.
When the power transistor is completely conducted, the power transistor works in a deep linear region, and the conducting resistance is small. The energy loss in the whole charging and discharging process is mainly the switching loss and the conduction loss of the power transistor. The switching loss formula is:
. Wherein,
representing the voltage detected from the input output port VAP,
represents the average value of the current of the inductor L,
indicating the time required for the state changes of the first and second power transistors M1 and M2 or the third and fourth power transistors M3 and M4,
representing the switching frequency. The conduction loss formula is:
. Wherein,
represents the effective value of the current waveform of the first power transistor M1 and the second power transistor M2 or the third power transistor M3 and the fourth power transistor M4,
representing the resistance of the power transistor. To sum up, the efficiency formula is:
. Due to the fact that
Typically in the order of milliohms,
the charge efficiency can be more than 90%, so that the charge efficiency and the discharge efficiency of the battery are greatly improved.
Specifically, as an embodiment, as shown in fig. 4, the charging control module 10 includes:
a signal detection circuit 101 and a logic control circuit 102;
a first input end of the signal detection circuit 101 is connected with an input/output interface of the battery charge/discharge control circuit, a second input end of the signal detection circuit is connected with a battery anode, and an output end of the signal detection circuit is connected with an input end of the logic control circuit 102;
a first output terminal of the logic control circuit 102 is connected to the second terminal of the first power transistor M1, and a second output terminal is connected to the first terminal of the second power transistor M2;
the signal detection circuit 101 is configured to detect a charging current through a first input terminal/detect a battery voltage through a second input terminal, generate a first carrier signal according to a difference between the charging current/the battery voltage and a preset threshold, and send the first carrier signal to the logic control circuit 102;
the logic control circuit 102 is configured to generate a pulse width modulation signal according to the first carrier signal, and output a low level to the first power transistor M1 and a high level to the second power transistor M2 when the pulse width modulation signal is at a high level;
the logic control circuit 102 is also configured to generate a clock signal and output a high level to the first power transistor M1 and a low level to the second power transistor M2 according to a rising edge of the clock signal.
When the input/output interface VAP is connected to the adapter, the third power transistor M3 is fully turned on, the fourth power transistor M4 is fully turned off, and the charging control module 10 operates. The power supplied by the adapter is transmitted to the battery through the first power transistor M1, and the battery voltage or charging current rises. The preset threshold comprises a current threshold and a voltage threshold, wherein the current threshold corresponds to constant-current charging, and the voltage threshold corresponds to constant-voltage charging.
The signal detection circuit 101 detects a charging current through a first input terminal, generates a first carrier signal according to a difference between the charging current and a current threshold, and sends the first carrier signal to the logic control circuit 102. The logic control circuit 102 generates a varying pwm signal according to the first carrier signal, and outputs a low level to the first power transistor M1 and a high level to the second power transistor M2 according to a high level of the pwm signal, so that the first power transistor M1 is completely turned off and the second power transistor M2 is completely turned on. The logic control circuit 102 also generates a clock signal and outputs a high level to the first power transistor M1 and a low level to the second power transistor M2 according to a rising edge of the clock signal, so that the first power transistor M1 is fully turned on and the second power transistor M2 is fully turned off again. This is repeated, and the logic control circuit 102 forces the charging current to be equal to the current threshold. When the charging current is equal to the current threshold value, the conduction time of the first power transistor M1 is fixed and does not change any more, and constant-current charging of the battery is realized.
The constant current charging can keep the charging current at the current threshold value to charge the battery, the voltage of the battery can gradually rise, when the voltage of the battery rises to a certain value, the signal detection circuit 101 can close the constant current charging, detect the voltage of the battery through the second input end and start the constant voltage charging.
Specifically, the signal detection circuit 101 detects a battery voltage through a second input terminal, generates a first carrier signal according to a difference between the battery voltage and a voltage threshold, and sends the first carrier signal to the logic control circuit 102. The logic control circuit 102 generates a varying pwm signal according to the first carrier signal, and outputs a low level to the first power transistor M1 and a high level to the second power transistor M2 according to a high level of the pwm signal, so that the first power transistor M1 is completely turned off and the second power transistor M2 is completely turned on. The logic control circuit 102 also generates a clock signal and outputs a high level to the first power transistor M1 and a low level to the second power transistor M2 according to a rising edge of the clock signal, so that the first power transistor M1 is fully turned on and the second power transistor M2 is fully turned off again. This is repeated until the battery voltage reaches the voltage threshold, the first transistor M1 is turned off and is no longer turned on, and the charging is turned off, so that the battery voltage is kept stable.
Optionally, as an embodiment, as shown in fig. 5, the signal detection circuit 101 includes:
a sampling circuit 51, a first transconductance amplifier 52, a first bandgap reference circuit 53, and a second transconductance amplifier 54;
the input end of the sampling circuit 51 is connected with the input/output interface of the battery charge/discharge control circuit, and the output end is connected with the positive input end of the first transconductance amplifier 52;
a first reference voltage output terminal of the first bandgap reference circuit 53 is connected to an inverting input terminal of the first transconductance amplifier 52, and a second reference voltage output terminal is connected to an inverting input terminal of the second transconductance amplifier 54;
the non-inverting input end of the second transconductance amplifier 54 is connected to the positive electrode of the battery;
a common junction point between the output terminal of the first transconductance amplifier 52 and the output terminal of the second transconductance amplifier 54 is used as the output terminal of the signal detection circuit 101;
the first bandgap reference circuit 53 is configured to provide a first reference voltage to the first transconductance amplifier 52 and a second reference voltage to the second transconductance amplifier 54;
the sampling circuit 51 is configured to detect a charging current and output a voltage signal proportional to the charging current to the first transconductance amplifier 52, and the first transconductance amplifier 52 is configured to amplify a deviation between the voltage signal and a first reference voltage to obtain a first carrier signal;
the second transconductance amplifier 54 is configured to detect a battery voltage, and amplify a deviation between the battery voltage and a second reference voltage to obtain a first carrier signal.
The logic control circuit 102 includes:
a first operational amplifier 55, a first comparator 56, a first oscillator 57, and a first logic controller 58;
a non-inverting input terminal of the first operational amplifier 55 is connected to a third reference voltage, and an inverting input terminal thereof is connected to an output terminal of the signal detection circuit 101;
an inverting input terminal of the first comparator 56 is connected to the output terminal of the first operational amplifier 55, and a non-inverting input terminal thereof is connected to a first output terminal of the first oscillator 57;
an output of the first comparator 56 is connected to a first input of the first logic controller 58;
a second output of the first oscillator 57 is connected to a second input of the first logic controller 58;
a first output terminal of the first logic controller 58 is connected to the second terminal of the first power transistor M1, and a second output terminal is connected to the first terminal of the second power transistor M2;
the first operational amplifier 55 is configured to amplify a difference between the first carrier signal and a third reference voltage to obtain a second carrier signal; the first oscillator 57 outputs a first ramp modulation signal through a first output terminal; the first comparator 56 is configured to compare the second carrier signal with the first ramp modulation signal, and generate a pulse width modulation signal according to the comparison result, and provide the pulse width modulation signal to the first logic controller 58; the first oscillator 57 is further configured to generate a clock signal and provide the clock signal to the first logic controller 58; the first logic controller 58 is configured to generate a first control signal and a second control signal that are opposite to each other according to the pwm signal and the clock signal;
wherein the first control signal is provided to the first power transistor M1, the first power transistor M1 is turned on when the first control signal is high, and the first power transistor M1 is turned off when the first control signal is low; the second control signal is provided to the second power transistor M2, the second power transistor M2 is turned on when the second control signal is high, and the second power transistor M2 is turned off when the second control signal is low.
In fig. 5, the sampling circuit 51, the first transconductance amplifier 52, the first bandgap reference circuit 53, the first operational amplifier 55, the first comparator 56, the first oscillator 57, and the first logic controller 58 form a constant current charging loop. The first bandgap reference circuit 53, the second transconductance amplifier 54, the first operational amplifier 55, the first comparator 56, the first oscillator 57, and the first logic controller 58 form a constant voltage charging loop.
For convenience of understanding, fig. 6 is a timing diagram of the current waveforms of the clock signal clk, the second carrier signal eaout1, the first ramp modulation signal vramp1, the pulse width modulation signal pwm1, the first control signal Hgate1, the second control signal Lgate1, and the inductor L provided in this embodiment.
In a constant current charging loop, the first bandgap reference circuit 53 provides a first reference voltage vref1 to the inverting input of the first transconductance amplifier 52 and a second reference voltage vref2 to the inverting input of the second transconductance amplifier 54. The sampling circuit 51 detects a charging current from the input-output interface VAP and outputs a voltage signal vsense1 proportional to the charging current to the non-inverting input of the first transconductance amplifier 52. When the charging current is small, the voltage signal vsense1 output by the sampling circuit 51 is small compared with the first reference voltage vref1, and the first carrier signal otaout1 output by the first transconductance amplifier 52 is low; if the first carrier signal otaout1 is lower than the third reference voltage vref3, the first operational amplifier 55 outputs a second carrier signal eaout1 that is relatively high, compared with the first ramp modulation signal vramp 1. In the present embodiment, the first harmonic modulation signal vramp1 is generated by the first oscillator 57 according to a preset period. The first comparator 56 generates the pwm signal pwm1 if and only if the first ramp modulation signal vramp1 is equal to the second carrier signal eaout1, so that the first logic controller 58 generates a set of opposite control signals, i.e., a first control signal Hgate1 and a second control signal Lgate1, for turning off the first power transistor M1 and turning on the second power transistor M2. When the first oscillator 57 generates the clock signal clk according to a preset period, the first logic controller 58 changes the first control signal Hgate1 to a high level and the second control signal Lgate1 to a low level to restart the first power transistor M1 and to turn off the second power transistor M2 again.
As can be seen from fig. 6, when the charging current is small, the first comparator 56 generates a pwm signal pwm1 that arrives later, so that the on time of the first power transistor M1 is long. The current of the inductor L is increased by the period of the current flowing through the first power transistor M1, which is longer than the on-time of the first power transistor M1, thereby increasing the charging current of the battery. When the charging current rises, the voltage signal vsense1 output by the sampling circuit 51 also rises proportionally, the corresponding first carrier signal otaout1 rises, the second carrier signal eaout1 falls until crossing the valley of the first ramp modulation signal vramp1, the first power transistor M1 is turned off, the charging current becomes 0, the voltage signal vsense1 output by the sampling circuit 51 is smaller than the first reference voltage vref1, and the first carrier signal otaout1 output by the first transconductance amplifier 52 is lower; if the first carrier signal otaout1 is lower than the third reference voltage vref3, the first operational amplifier 55 outputs a second carrier signal eaout1 that is relatively high, and the comparison … … with the first ramp modulation signal vramp1 is repeated, in this embodiment, the first operational amplifier 55 forces the charging current to be equal to the current threshold, i.e., the voltage signal vsense1 is equal to the first reference voltage vref 1. When the voltage signal vsense1 is equal to the first reference voltage vref1, the on-time of the first power transistor M1 is fixed and does not change any more, thereby realizing constant-current charging.
In the constant current charging process, the battery voltage gradually rises, and after the battery voltage rises to a certain value, the second transconductance amplifier 54 is triggered to start up the constant voltage loop, and the first transconductance amplifier 52 is closed to close the constant current loop. Illustratively, for a 3.7V nominal lithium battery, the constant current loop operates when the battery voltage is less than 4.1V, and the constant current loop is closed and the constant voltage loop operates when the battery voltage is greater than 4.1V. The constant voltage loop forces the battery voltage to be equal to the voltage threshold, similar to the constant current loop would force the charging current to be equal to the current threshold.
The second transconductance amplifier 52 detects the battery voltage V through the non-inverting input terminalBAT. When the battery voltage VBATWhen the first carrier signal otaout1 is gradually increased, the second transconductance amplifier 52 outputs the first carrier signal otaout1, and the third carrier signal otaout1 is gradually increasedThe difference between the reference voltages vref3 gradually decreases, and the second carrier signal eaout1 output by the first operational amplifier 55 gradually decreases. In the present embodiment, the first harmonic modulation signal vramp1 is generated by the first oscillator 57 according to a preset period. The first comparator 56 generates the pwm signal pwm1 if and only if the first ramp modulation signal vramp1 is equal to the second carrier signal eaout1, so that the first logic controller 58 generates a set of opposite control signals, i.e., a first control signal Hgate1 and a second control signal Hgate2, for turning off the first power transistor M1 and turning on the second power transistor M2. When the first oscillator 57 generates the clock signal clk according to a preset period, the first logic controller 58 changes the first control signal Hgate1 to a high level and the second control signal Lgate1 to a low level to restart the first power transistor M1 and to turn off the second power transistor M2 again.
Therefore, at the battery voltage VBATWhen gradually increasing, the first comparator 56 generates an earlier pulse width modulation signal pwm1, so that the on-time of the first power transistor M1 is gradually shortened. The current of the inductor L decreases in the period of the current flowing through the first power transistor M1 due to the shortened on-time of the first power transistor M1, thereby reducing the charging current of the battery. When the battery voltage is equal to the second reference voltage vref2, the first power transistor M1 is turned off, the charging current drops to 0, and the charging is turned off. As can be seen, by setting the second reference voltage vref2, the present embodiment can keep the battery voltage stable, and realize constant-voltage charging.
Taking the above example, for a 3.7V nominal lithium battery, assuming that the second reference voltage vref2 is 4.2V, when the battery voltage rises to 4.2V, the first power transistor M1 is turned off, the charging current gradually drops to 0, and the charging is turned off.
Alternatively, as an embodiment, as shown in fig. 7, the discharge control module 20 includes:
a second bandgap reference module 71, a second operational amplifier 72, a second comparator 73, a second oscillator 74 and a second logic controller 75;
the positive phase input end of the second operational amplifier 72 is connected with the output end of the second band-gap reference module 71, and the negative phase input end is connected with the input/output interface of the battery charge/discharge control circuit;
an inverting input terminal of the second comparator 73 is connected to the output terminal of the second operational amplifier 72, and a non-inverting input terminal thereof is connected to a first output terminal of the second oscillator 74;
an output of the second comparator 73 is connected to a first input of the second logic controller 75;
a second output of the second oscillator 74 is connected to a second input of the second logic controller 75;
a first output terminal of the second logic controller 75 is connected to a first terminal of the third power transistor M3, and a second output terminal is connected to a first terminal of the fourth power transistor M4;
the second operational amplifier 72 is configured to detect a discharge voltage, and amplify a difference between the discharge voltage and a fourth reference voltage to obtain a third carrier signal; the second oscillator 74 is configured to output a second ramp modulation signal through a first output terminal, and the second comparator 73 is configured to compare the third carrier signal with the second ramp modulation signal and generate a pulse width modulation signal according to the comparison result, and provide the pulse width modulation signal to the second logic controller 75; the second oscillator 74 is further configured to generate a clock signal and provide the clock signal to the second logic controller 75; the second logic controller 75 is configured to generate a third control signal and a fourth control signal that are opposite to each other according to the pulse width modulation signal and the clock signal;
wherein the third control signal is provided to the third power transistor M3, the third power transistor M3 is turned on when the third control signal is high, and the third power transistor M3 is turned off when the third control signal is low; the fourth control signal is provided to the fourth power transistor M4, the fourth power transistor M4 is turned on when the fourth control signal is high, and the fourth power transistor M4 is turned off when the fourth control signal is low.
For ease of understanding, the following description will be given taking the timing chart shown in fig. 8 as an example.
Here, the second bandgap reference block 71 outputs a fourth reference voltage vref4, which is provided to the non-inverting input of the second operational amplifier 72. The second operational amplifier 72 detects a discharge voltage from the input-output interface VAP through an inverting input terminal. When the discharge voltage V isVAPWhen smaller, the third carrier signal eaout2 output by the second operational amplifier 72 is higher, and the third carrier signal eaout2 is compared with the second ramp modulation signal vramp 2. In the present embodiment, the second harmonic modulation signal vramp2 is generated by the second oscillator 74 according to a preset period. The second comparator 73 generates the pwm signal pwm2 to cause the second logic controller 75 to generate a set of opposite control signals, i.e., a third control signal and a fourth control signal, to turn off the third power transistor M3 and turn on the fourth power transistor M4, if and only if the second ramp modulation signal Vramp2 is equal to the third carrier signal eaout 2. When the second oscillator 74 generates the clock signal clk according to a preset period, the second logic controller 75 changes the third control signal Hgate2 to a high level and the fourth control signal Lgate2 to a low level to restart the third power transistor M3 and to turn off the fourth power transistor M4 again.
Therefore, at the discharge voltage VVAPWhen the voltage is smaller, the second comparator 73 generates a pwm signal pwm2 that arrives later, so that the third power transistor M3 has a longer on-time, and supplies more power to the input/output interface VAP, and the discharge voltage rises. When discharge voltage VVAPWhen the reference voltage vref4 is equal to the fourth reference voltage vref4, since the third power transistor M3 is switched and not linear, when the battery charging and discharging control circuit is not loaded, the third power transistor M3 is not turned on any more, when the battery charging and discharging control circuit is loaded, the on-time of the third power transistor M3 is fixed to the on-time at the steady state, and the duty ratio returns to the V at the steady stateVAP/VBAT. It can be seen that by providing the fourthThe present embodiment can stabilize the discharge voltage by the reference voltage vref 4.
The battery charging and discharging control circuit provided by the invention is additionally provided with a power transistor on the basis of the prior art and combines a switch type charging and discharging mode. When an input/output interface of the battery charge/discharge control circuit is connected with an adapter, the charge control module controls the on/off of the first power transistor and the second power transistor according to a charge current so as to charge a battery at a constant current, and controls the on/off of the first power transistor and the second power transistor according to the voltage of the battery so as to charge the battery at a constant voltage; when the input/output interface of the battery charge/discharge control circuit is connected with an electric device or is floated, the discharge control module controls the third power transistor and the fourth power transistor to be switched on and off according to the discharge voltage so as to keep the discharge voltage stable; therefore, the energy loss in the whole charging process is mainly the switching loss and the conduction loss of the power tube, the charging efficiency of the battery is greatly improved, the heating frequency of the chip is reduced, and the influence on the performance of the chip is reduced.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (7)
1. A battery charge and discharge control circuit, comprising:
the power supply comprises a charging control module, a capacitor, a first power transistor, a second power transistor, an inductor, a third power transistor, a fourth power transistor and a discharging control module;
the first input end of the charging control module, the first end of the first power transistor, the first end of the capacitor and the input end of the discharging control module are connected to an input/output interface of the battery charging and discharging control circuit in common, and the second end of the capacitor is grounded;
the second input end of the charging control module is connected with the positive electrode of the battery;
a first output end of the charging control module is connected with a second end of the first power transistor, and a second output end of the charging control module is connected with a first end of the second power transistor;
a first output end of the discharge control module is connected with a first end of the third power transistor, and a second output end of the discharge control module is connected with a first end of the fourth power transistor;
a common joint point between the third end of the first power transistor and the second end of the second power transistor is connected with the first end of the inductor;
a common junction point between the second end of the third power transistor and the second end of the fourth power transistor is connected with the second end of the inductor;
the third end of the third power transistor is connected with the positive electrode of the battery;
the third end of the second power transistor, the third end of the fourth power transistor and the third output end of the charging control module are connected to the negative electrode of the battery in common, and the negative electrode of the battery is grounded;
when the input/output interface of the battery charge/discharge control circuit is connected with an adapter, the discharge control module is used for controlling the third power transistor to be completely turned on and the fourth power transistor to be completely turned off; the charging control module is used for detecting charging current, controlling the first power transistor and the second power transistor to be alternately switched on and off according to the charging current, enabling the current period of the inductor to be raised, enabling the charging current to rise, and enabling the first power transistor to be switched on for a fixed time when the charging current is equal to a current threshold value so as to charge a battery at a constant current; detecting battery voltage, controlling the first power transistor and the second power transistor to be alternately switched on and off according to the battery voltage, reducing the current period of the inductor, reducing the charging current, and switching off the first power transistor when the battery voltage is equal to a voltage threshold value so as to charge the battery at a constant voltage;
when the input/output interface of the battery charge/discharge control circuit is connected with an electric device or floats, the charge control module is used for controlling the first power transistor to be completely switched on and the second power transistor to be completely switched off; the discharge control module is used for detecting a discharge voltage and controlling the third power transistor and the fourth power transistor to be alternately switched on and off according to the discharge voltage so as to keep the discharge voltage stable.
2. The battery charge and discharge control circuit of claim 1 wherein the second and fourth power transistors are N-channel power transistors and the first and third power transistors are P-channel power transistors.
3. The battery charge and discharge control circuit of claim 1 wherein the first, second, third and fourth power transistors are N-channel power transistors.
4. The battery charge and discharge control circuit of claim 2 or 3, wherein the charge control module comprises:
a signal detection circuit and a logic control circuit;
the first input end of the signal detection circuit is connected with the input and output interface of the battery charge and discharge control circuit, the second input end of the signal detection circuit is connected with the anode of the battery, and the output end of the signal detection circuit is connected with the input end of the logic control circuit;
a first output end of the logic control circuit is connected with a second end of the first power transistor, and a second output end of the logic control circuit is connected with a first end of the second power transistor;
the signal detection circuit is used for detecting charging current through a first input end/battery voltage through a second input end, generating a first carrier signal according to a difference value between the charging current/battery voltage and a preset threshold value, and sending the first carrier signal to the logic control circuit;
the logic control circuit is used for generating a pulse width modulation signal according to the first carrier signal and outputting a low level to the first power transistor and outputting a high level to the second power transistor when the pulse width modulation signal is at a high level;
the logic control circuit is further used for generating a clock signal and outputting a high level to the first power transistor and outputting a low level to the second power transistor according to the rising edge of the clock signal.
5. The battery charge and discharge control circuit of claim 4, wherein the signal detection circuit comprises:
the band-gap reference circuit comprises a sampling circuit, a first transconductance amplifier, a first band-gap reference circuit and a second transconductance amplifier;
the input end of the sampling circuit is connected with the input and output interface of the battery charge and discharge control circuit, and the output end of the sampling circuit is connected with the positive phase input end of the first transconductance amplifier;
a first reference voltage output end of the first bandgap reference circuit is connected with an inverting input end of the first transconductance amplifier, and a second reference voltage output end of the first bandgap reference circuit is connected with an inverting input end of the second transconductance amplifier;
the positive phase input end of the second transconductance amplifier is connected with the positive electrode of the battery;
a common junction point between the output end of the first transconductance amplifier and the output end of the second transconductance amplifier is used as the output end of the signal detection circuit;
the first bandgap reference circuit is used for providing a first reference voltage for the first transconductance amplifier and providing a second reference voltage for the second transconductance amplifier;
the sampling circuit is used for detecting a charging current and outputting a voltage signal proportional to the charging current to the first transconductance amplifier, and the first transconductance amplifier is used for amplifying a deviation between the voltage signal and a first reference voltage to obtain a first carrier signal;
the second transconductance amplifier is used for detecting the battery voltage and amplifying the deviation between the battery voltage and a second reference voltage to obtain a first carrier signal.
6. The battery charge and discharge control circuit of claim 5, wherein the logic control circuit comprises:
the first logic controller comprises a first operational amplifier, a first comparator, a first oscillator and a first capacitor;
the positive phase input end of the first operational amplifier is connected with a third reference voltage, and the negative phase input end of the first operational amplifier is connected with the output end of the signal detection circuit;
the inverting input end of the first comparator is connected with the output end of the first operational amplifier, and the non-inverting input end of the first comparator is connected with the first output end of the first oscillator;
the output end of the first comparator is connected with the first input end of the first logic controller;
a second output end of the first oscillator is connected with a second input end of the first logic controller;
a first output end of the first logic controller is connected with a second end of the first power transistor, and a second output end of the first logic controller is connected with a first end of the second power transistor;
the first operational amplifier is used for amplifying a difference value between the first carrier signal and a third reference voltage to obtain a second carrier signal; the first oscillator outputs a first ramp modulation signal through a first output end; the first comparator is used for comparing the second carrier signal with the first ramp modulation signal and generating a pulse width modulation signal according to the comparison result and supplying the pulse width modulation signal to the first logic controller; the first oscillator is further used for generating a clock signal and providing the clock signal to the first logic controller; the first logic controller is used for generating a first control signal and a second control signal which are opposite to each other according to the pulse width modulation signal and the clock signal;
wherein the first control signal is provided to the first power transistor, the first power transistor is turned on when the first control signal is at a high level, and the first power transistor is turned off when the first control signal is at a low level; the second control signal is provided to the second power transistor, the second power transistor is turned on when the second control signal is at a high level, and the second power transistor is turned off when the second control signal is at a low level.
7. The battery charge and discharge control circuit of claim 4, wherein the discharge control module comprises:
the second band-gap reference module, the second operational amplifier, the second comparator, the second oscillator and the second logic controller;
the positive phase input end of the second operational amplifier is connected with the output end of the second band-gap reference module, and the negative phase input end of the second operational amplifier is connected with the input/output interface of the battery charge/discharge control circuit;
the inverting input end of the second comparator is connected with the output end of the second operational amplifier, and the non-inverting input end of the second comparator is connected with the first output end of the second oscillator;
the output end of the second comparator is connected with the first input end of the second logic controller;
a second output end of the second oscillator is connected with a second input end of the second logic controller;
a first output end of the second logic controller is connected with a first end of the third power transistor, and a second output end of the second logic controller is connected with a first end of the fourth power transistor;
the second operational amplifier is used for detecting a discharge voltage and amplifying a difference value between the discharge voltage and a fourth reference voltage to obtain a third carrier signal; the second oscillator is used for outputting a second ramp modulation signal through a first output end, and the second comparator is used for comparing the third carrier signal with the second ramp modulation signal and generating a pulse width modulation signal according to the comparison result to be supplied to the second logic controller; the second oscillator is further used for generating a clock signal and providing the clock signal to the second logic controller; the second logic controller is used for generating a third control signal and a fourth control signal which are opposite to each other according to the pulse width modulation signal and the clock signal;
wherein the third control signal is provided to the third power transistor, the third power transistor is turned on when the third control signal is at a high level, and the third power transistor is turned off when the third control signal is at a low level; the fourth control signal is provided to the fourth power transistor, the fourth power transistor is turned on when the fourth control signal is at a high level, and the fourth power transistor is turned off when the fourth control signal is at a low level.
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| CN202010655846.4A CN111555416B (en) | 2020-07-09 | 2020-07-09 | Battery charge-discharge control circuit |
| PCT/CN2021/095642 WO2022007524A1 (en) | 2020-07-09 | 2021-05-25 | Battery charging and discharging control circuit |
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| CN115037031A (en) * | 2022-06-30 | 2022-09-09 | 杭州海康消防科技有限公司 | Power supply circuit and electronic equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104065119A (en) * | 2014-06-04 | 2014-09-24 | 南京矽力杰半导体技术有限公司 | Battery power supply circuit and method |
| CN105867575A (en) * | 2016-05-05 | 2016-08-17 | 浪潮电子信息产业股份有限公司 | Charging and discharging chip architecture applied to server backup battery |
| CN110098742A (en) * | 2019-06-01 | 2019-08-06 | 深圳市永航新能源技术有限公司 | The application of synchronous rectification DC/DC converter |
| CN111149274A (en) * | 2017-08-07 | 2020-05-12 | Thx有限公司 | Power management system for battery-powered audio devices |
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| US9077198B2 (en) * | 2011-12-30 | 2015-07-07 | Thomas Szepesi | Battery charging method and circuit |
| CN111555416B (en) * | 2020-07-09 | 2020-11-17 | 深圳市创芯微微电子有限公司 | Battery charge-discharge control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065119A (en) * | 2014-06-04 | 2014-09-24 | 南京矽力杰半导体技术有限公司 | Battery power supply circuit and method |
| CN105867575A (en) * | 2016-05-05 | 2016-08-17 | 浪潮电子信息产业股份有限公司 | Charging and discharging chip architecture applied to server backup battery |
| CN111149274A (en) * | 2017-08-07 | 2020-05-12 | Thx有限公司 | Power management system for battery-powered audio devices |
| CN110098742A (en) * | 2019-06-01 | 2019-08-06 | 深圳市永航新能源技术有限公司 | The application of synchronous rectification DC/DC converter |
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Address after: Building 3A28, Smart Home Phase II, No. 76 Baohe Avenue, Baolong Community, Baolong Street, Longgang District, Shenzhen City, Guangdong Province, 518000 Patentee after: Shenzhen Chuangxin Microelectronics Co.,Ltd. Address before: 518000 Room 401, block a, Longgang smart home, 76 Baohe Avenue, Baolong community, Baolong street, Longgang District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN CHUANGXINWEI MICROELECTRONICS Co.,Ltd. |
|
| CP03 | Change of name, title or address |
Address after: Building 3A28, Smart Home Phase II, No. 76 Baohe Avenue, Baolong Community, Baolong Street, Longgang District, Shenzhen City, Guangdong Province, 518000 Patentee after: SHENZHEN CHUANGXINWEI MICROELECTRONICS Co.,Ltd. Country or region after: China Address before: 28th Floor, 3A2, Smart Home Phase II, 76 Baohe Avenue, Baolong Community, Baolong Street, Longgang District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Chuangxin Microelectronics Co.,Ltd. Country or region before: China |