CN111540327A

CN111540327A - GOA circuit and display panel

Info

Publication number: CN111540327A
Application number: CN202010436062.2A
Authority: CN
Inventors: 周永祥
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-05-21
Filing date: 2020-05-21
Publication date: 2020-08-14
Anticipated expiration: 2040-05-21
Also published as: CN111540327B

Abstract

The embodiment of the application provides a GOA circuit and a display panel, wherein a pull-down maintaining module of the GOA circuit comprises two independent sets of first pull-down maintaining circuits and second pull-down maintaining circuits which are connected in a mirror image mode, and the first pull-down maintaining circuits and the second pull-down maintaining circuits respectively work alternately under the action of a first low-frequency clock signal LC1 and a second low-frequency clock signal LC 2. On one hand, the working mode can enhance the stability of the GOA circuit and prevent the thin film transistors electrically connected with the pull-down node P from being influenced by stress when the pull-down node P keeps a high potential for a long time, so that the threshold voltage Vth of the thin film transistors is drifted to cause the abnormal grid signals output to a scanning line, namely a grid line, and the abnormal picture display is caused; this mode of operation can on the other hand be kept operational by one of the pull-down holding circuits when the other one fails, thereby increasing the reliability of the GOA circuit.

Description

GOA circuit and display panel

Technical Field

The embodiment of the application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

The goa (gate Driver On array) technology integrates a gate driving circuit of a display panel On a glass substrate to form a scanning drive for the display panel. The GOA technology can reduce binding (binding) procedures of an external IC, can reduce product cost, and is more suitable for manufacturing narrow-frame or frameless display products.

The conventional GOA circuit comprises a plurality of cascaded GOA units, wherein each GOA unit correspondingly drives one level of horizontal scanning lines. Each GOA unit mainly comprises a pull-up circuit, a pull-up control circuit, a pull-down circuit and a pull-down maintaining circuit. The pull-up circuit is mainly responsible for outputting a clock signal as a grid signal, namely a Gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit and is generally connected with a download signal or a Gate signal transmitted by the previous GOA unit; the pull-down circuit is responsible for pulling down the Gate signal to a low potential at the first time, namely closing the Gate signal; the pull-down maintaining circuit is responsible for maintaining the Gate signal and the Gate signal (commonly referred to as the Q-point) of the pull-up circuit in an off state.

Referring to fig. 1, fig. 1 is a schematic diagram of a conventional GOA circuit with a 14T2C structure, where the GOA circuit includes only one pull-down holding module, and a pull-down node P maintains a high potential for a long time in a pull-down holding stage, so that NT5 and NT10 having gates connected to the pull-down node P are stressed for a long time, and thus threshold voltages Vth of NT5 and NT10 are severely shifted, which causes characteristics of NT5 and NT10 to degrade, and thus the GOA circuit fails; in addition, if only one pull-down sustain circuit fails, the GOA circuit will also fail.

Therefore, a new GOA circuit is needed to solve the problem of unstable circuit during the pull-down sustain phase.

Disclosure of Invention

In order to solve the problem that the current GOA circuit is unstable in the pull-down maintaining stage, an embodiment of the present application provides a GOA circuit, where the GOA circuit includes a plurality of cascaded GOA units, and each of the GOA units includes: a forward and reverse scan module 100, a pull-up module 200, a pull-down module 300, and a pull-down sustain module.

The forward-reverse scanning module 100 is electrically connected to the first node Q and the nth-stage gate signal output terminal g (N), respectively; the pull-up module 200 is electrically connected to the nth stage gate signal output terminal g (N); the pull-down module 300 is electrically connected to the first node Q, the nth gate signal output terminal g (N), and the first potential, respectively; the pull-down maintaining module comprises a first pull-down maintaining circuit 401 and a second pull-down maintaining circuit 402 which are connected in a mirror image mode, the first pull-down maintaining circuit 401 is connected to a first low-frequency clock signal LC1, the second pull-down maintaining circuit 402 is connected to a second low-frequency clock signal LC2, and phases of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite; the first pull-down maintaining circuit 401 and the second pull-down maintaining circuit 402 alternately operate to maintain the nth stage gate signal output terminal g (N) and the first node Q at the first potential.

In some embodiments, the first pull-down sustain circuit 401 includes a second first transistor T21, a second transistor T22, a second third transistor T23, and a second capacitor C2. The sources of the second transistor T21 and the second three transistor T23 are both connected to the first potential, and the drains of the second transistor T21 and the second transistor T22 are both electrically connected to a second node P1; the gate of the second transistor T21 is electrically connected to the first node Q; the grid electrode of the second transistor T22 is connected to the first low-frequency clock signal LC1, and the source electrode is connected to a second potential; a gate of the second third transistor T23 is electrically connected to the second node P1, and a drain thereof is electrically connected to the first node Q; one end of the second capacitor C2 is connected to the first potential, and the other end is electrically connected to the second node P1; also, the width-to-length ratio of the second transistor T21 is greater than the width-to-length ratio of the second transistor T22.

The second pull-down maintaining circuit 402 includes a third transistor T31, a third transistor T32, a third transistor T33, and a third capacitor C3. The sources of the third transistor T31 and the third transistor T33 are both connected to the first potential, the drains of the third transistor T31 and the third transistor T32 are both electrically connected to the second node P1, and the gate of the third transistor T31 is electrically connected to the first node Q; the gate of the third transistor T32 is connected to the second low-frequency clock signal LC2, and the source is connected to a second potential; a gate of the third transistor T33 is electrically connected to a third node P2, and a drain thereof is electrically connected to the first node Q; one end of the third capacitor C3 is connected to the first potential, and the other end is electrically connected to a third node P2; also, the width-to-length ratio of the third transistor T31 is greater than the width-to-length ratio of the third transistor T32.

In some embodiments, all transistors of the GOA circuit are N-type thin film transistors, the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.

When the first pull-down maintaining circuit 401 is operated, the first node Q and the first low frequency clock signal LC1 are both high, so that the second node P1 is switched to low potential, so that the third transistor T23 is turned off, at this time, the first node Q is switched to low potential and the second node P1 is switched to high potential, so that the third transistor T23 is turned on and the second capacitor C2 is charged, so that the first node Q is maintained at the constant voltage low potential VGL.

When the second pull-down maintaining circuit 402 is operated, the first node Q and the second low frequency clock signal LC2 are both high, so that the third node P2 is switched to low potential, so that the third transistor T33 is turned off, at this time, the first node Q is switched to low potential and the third node P2 is switched to high potential, so that the third transistor T33 is turned on and the third capacitor C3 is charged, so that the first node Q is maintained at the constant voltage low potential VGL.

In some embodiments, the pull-down module 300 includes a fourth transistor T41 and a fourth transistor T42. The sources of the fourth transistor T41 and the fourth transistor T42 are both connected to a first potential; the gate of the fourth transistor T41 is electrically connected to the (N +2) th-stage gate signal output terminal G (N +2), and the drain is electrically connected to the first node Q; the gate of the fourth transistor T42 is connected to the (N +1) th clock signal CK (N +1), and the drain is electrically connected to the nth stage gate signal output terminal g (N).

In some embodiments, the forward and reverse scan module 100 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is connected to the N-2 th gate signal output terminal G (N-2), the source is connected to the forward scan signal U2D, and the drain is electrically connected to the first node Q; the gate of the second transistor T2 is connected to the (N +2) th stage gate signal output terminal G, the source is connected to the inverse scan signal D2U, and the drain is electrically connected to the first node Q; one of the forward direction scan signal U2D and the reverse direction scan signal D2U is high and the other is low.

In some embodiments, the GOA circuit further comprises a leakage prevention module 500 comprising a seventh transistor; the seventh transistor has a gate connected to a second potential, a source electrically connected to the first node Q, and a drain electrically connected to the pull-up node W.

In some embodiments, the pull-up module 200 includes a ninth transistor T9, a gate of the ninth transistor T9 is electrically connected to the pull-up node W, a source of the ninth transistor is connected to the nth clock signal ck (N), and a drain of the ninth transistor is electrically connected to the nth gate signal output terminal g (N).

In some embodiments, the GOA circuit further includes a voltage regulator module 600, where the voltage regulator module 600 includes a first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q, and the other end is connected to the first potential.

In some embodiments, the GOA circuit further includes a global control module 700, wherein the global control module 700 includes a thirteenth transistor T13, a gate of the thirteenth transistor T13 is connected to the global control signal GAS, a source of the thirteenth transistor is connected to the first potential, and a drain of the thirteenth transistor is electrically connected to the nth stage gate signal output g (N).

In addition, the embodiment of the application also provides a liquid crystal display panel, and the liquid crystal display panel comprises the GOA circuit.

The pull-down maintaining module of the GOA circuit provided by the embodiment of the application comprises two independent pull-down maintaining circuits, namely a first pull-down maintaining circuit and a second pull-down maintaining circuit. The first pull-down maintaining circuit and the second pull-down maintaining circuit respectively and alternately work under the action of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2, the working mode can enhance the stability of the GOA circuit on one hand, and prevent the thin film transistor electrically connected with the second node P1 or the third node P2 from being influenced by stress when the second node P1 or the third node P2 of the pull-down node keeps high potential for a long time, so that abnormal picture display is caused, and the working mode can keep working by the other pull-down maintaining circuit when one pull-down maintaining circuit fails, so that the reliability of the GOA circuit is improved.

Drawings

The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.

FIG. 1 is a schematic diagram of a GOA circuit of a conventional 14T2C structure;

fig. 2 is a circuit diagram of an nth level GOA unit according to an embodiment of the present application;

fig. 3 is a timing diagram of driving signals of an nth level GOA unit according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Referring to fig. 2, fig. 2 is a circuit diagram of a nth-level GOA unit according to an embodiment of the present application, and generally, a GOA circuit includes a plurality of cascaded GOA units shown in fig. 2. Each level of GOA unit comprises: a forward and reverse scan module 100, a pull-up module 200, a pull-down module 300, and a pull-down sustain module.

The positive and negative scanning module 100 is electrically connected to the first node Q and the nth stage gate signal output terminal g (N), respectively; the pull-up module 200 is electrically connected to the nth stage gate signal output terminal g (N); the pull-down module 300 is electrically connected to the first node Q, the nth gate signal output terminal g (N), and the first potential, respectively; the pull-down maintaining module comprises a first pull-down maintaining circuit 401 and a second pull-down maintaining circuit 402 which are connected in a mirror image mode, wherein the first pull-down maintaining circuit 401 and the second pull-down maintaining circuit 402 are respectively electrically connected with a first potential, the first pull-down maintaining circuit is connected to a first low-frequency clock signal LC1, the second pull-down maintaining circuit 402 is connected to a second low-frequency clock signal LC2, and the phases of the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are opposite; the first pull-down holding circuit 401 and the second pull-down holding circuit 402 alternately operate to hold the nth stage gate signal output terminal g (N) and the first node Q at the first potential.

It should be noted that the first low-frequency clock signal LC1 and the second low-frequency clock signal LC2 are inverted, that is, one of the signals is at a low level, and the other signal is at a high level, so that the first pull-down holding circuit 401 and the second pull-down holding circuit 402 are controlled to alternately operate. The switching period of the first and second low frequency clock signals LC1 and LC2 may be several tens of microseconds to several tens of minutes, determined according to the electrical characteristics of the thin film transistor TFT.

The pull-down maintaining module of the GOA circuit provided by the embodiment of the application comprises two independent sets of pull-down maintaining circuits in mirror image connection, namely a first pull-down maintaining circuit and a second pull-down maintaining circuit, wherein the first pull-down maintaining circuit and the second pull-down maintaining circuit respectively work alternately under the action of a first low-frequency clock signal LC1 and a second low-frequency clock signal LC 2. On one hand, the working mode can enhance the stability of the GOA circuit, and prevent the thin film transistors electrically connected with the second node P1 or the third node P2 from being influenced by stress when the second node P1 or the third node P2 keeps a high potential for a long time, so that the threshold voltage Vth of the thin film transistors is shifted, and gate signals output to scanning lines (or gate lines) are abnormal, and abnormal picture display is caused; this mode of operation can on the other hand be kept operational by one of the pull-down holding circuits when the other one fails, thereby increasing the reliability of the GOA circuit.

Referring to fig. 2, the first pull-down sustain circuit 401 includes a second first transistor T21, a second transistor T22, a second third transistor T23, and a second capacitor C2.

The sources of the second transistor T21 and the second third transistor T23 are both connected to the first potential, and the drains of the second transistor T21 and the second transistor T22 are both electrically connected to the second node P1; the gate of the second transistor T21 is electrically connected to the first node Q; the grid electrode of the second transistor T22 is connected to the first low-frequency clock signal LC1, and the source electrode is connected to the second potential; the gate and the drain of the second third transistor T23 are electrically connected to the second node P1 and the first node Q, respectively; one end of the second capacitor C2 is connected to the first potential, and the other end is electrically connected to the second node P1; the width-to-length ratio W/L of the second transistor T21 is greater than the width-to-length ratio W/L of the second transistor T22.

The second pull-down maintaining circuit 402 includes a third transistor T31, a third transistor T32, a third transistor T33, and a third capacitor C3; the sources of the third transistor T31 and the third transistor T33 are both connected to the first potential, the drains of the third transistor T31 and the third transistor T32 are both electrically connected to the second node P1, and the gate of the third transistor T31 is electrically connected to the first node Q; the gate of the third transistor T32 is connected to the second low-frequency clock signal LC2, and the source is connected to the second potential; the gate and the drain of the third transistor T33 are electrically connected to the node P1 and the first node Q, respectively; one end of the third capacitor C3 is connected to the first potential, and the other end is electrically connected to the third node P2; the width-to-length ratio W/L of the third transistor T31 is greater than the width-to-length ratio W/L of the third transistor T32.

Further, fig. 3 is a timing diagram of driving signals of the nth stage GOA unit according to the embodiment of the present application, where CK1 and CK2 refer to the nth clock signal CK (N) and the N +1 th clock signal CK (N +1), respectively, and Gate1 and Gate2 refer to the nth stage Gate signal output terminal G (N) and the N +1 th stage Gate signal output terminal G (N +1), respectively. Referring to fig. 2 and 3, all transistors of the GOA circuit are N-type thin film transistors, and the first potential is a constant voltage low potential VGL, and the second potential is a constant voltage high potential VGH.

When the first pull-down maintaining circuit 402 is operated, the first node Q and the first low frequency clock signal LC1 are both high, so that the second node P1 is switched to low potential, so that the second third transistor T23 is turned off, at this time, the first node Q is switched to low potential and the second node P1 is switched to high potential, so that the second third transistor T23 is turned on and the second capacitor C2 is charged, so that the first node Q is maintained at the constant voltage low potential VGL.

Specifically, when the first low frequency clock signal LC1 maintains a high level and the second low frequency clock signal LC2 maintains a low level, the first pull-down holding circuit 401 operates and the second pull-down holding circuit 402 does not operate.

When the nth row is turned on for charging before the pull-down sustain period, the first node Q is at a high level, the second transistor T21 is turned on to pull the second node P1 low, and the LC1 is kept at a high level at this time, and the second transistor T22 is turned on to pull the second node P1 high, so there is competition between the effects of the second transistor T21 and the second transistor T22 on the second node P1, but since the second transistor T21 has a larger width-to-length ratio than the second transistor T22, the driving capability is stronger, the driving current is larger, so the effect of the second transistor T21 on the second node P1 is greater than the effect of the second transistor T22 on the second node P1, and the second node P1 is pulled low. Next, the second third transistor NT23 is turned off, the first node Q point keeps high, after the charging of the current row is finished, the N +2 th stage gate signal output terminal G (N +2) is pulled high, the fourth transistor T41 is turned on to pull the first node Q low, at this time, the second transistor T22 pulls the second node P1 high and the second capacitor C2 is charged, so that the second third transistor NT23 is turned on, since one end of the second capacitor C2 is low and the other end is high, the second capacitor C2 and the second node P1 act together to further keep the second third transistor NT23 on, so that the first node Q keeps low.

When the second pull-down maintaining circuit operates, the first node Q and the second low frequency clock signal LC2 are both high, so that the third node P2 is switched to low potential, so that the third transistor T33 is turned off, at this time, the first node Q is switched to low potential and the third node P2 is switched to high potential, so that the third transistor T33 is turned on and the third capacitor C3 is charged, so that the first node Q is maintained at the constant voltage low potential VGL.

Since the specific work flow of the second pull-down maintaining circuit 402 is the same as that of the first pull-down maintaining circuit 401, it is not described herein again.

It should be noted that, if all the transistors of the GOA circuit are P-type thin film transistors, the working flows of the first pull-down holding circuit 401 and the second pull-down holding circuit 402 are the same as the working flows when all the transistors are N-type thin film transistors, and only the potentials and the timings of the related control signals are changed, which is not described herein again.

Referring to fig. 2, the GOA pull-up module includes a ninth transistor T9, a gate of the ninth transistor T9 is electrically connected to a pull-up node W, a source is connected to an nth clock signal ck (N), and a drain is electrically connected to an nth gate signal output terminal g (N).

Further, the pull-down module includes a fourth transistor T41 and a fourth transistor T42; the sources of the fourth transistor T41 and the fourth transistor T42 are both connected to the first potential; the gate of the fourth transistor T41 is electrically connected to the (N +1) th stage gate signal output terminal G (N +1), and the drain is electrically connected to the first node Q; the gate of the fourth transistor T42 is connected to the (N +1) th clock signal CK (N +1), and the drain is electrically connected to the nth stage gate signal output terminal g (N).

It should be noted that, when the charging of the current row is finished, since there is a clock interval between the nth clock signal CK (N) and the (N +1) th clock signal CK (N +1) to prevent the mis-charging, the Q point is not pulled down immediately, but the ninth transistor T9 is turned off by the N clock signal CK (N) going low, so that the nth gate signal output terminal G (N) is pulled down, and when the (N +2) th gate signal output terminal G (N +2) is pulled high, the fourth transistor T41 is turned on to pull the first node Q down.

Referring to fig. 2, the forward and reverse scan module includes a first transistor T1 and a second transistor T2; the grid of the first transistor T1 is connected to the N-2 th stage grid signal output end G (N-2), the source is connected to the forward scanning signal U2D, and the drain is electrically connected to the first node Q; the gate of the second transistor T2 is connected to the (N +2) th stage gate signal output terminal G, the source is connected to the inverse scan signal D2U, and the drain is electrically connected to the first node Q; one of the forward direction scan signal U2D and the reverse direction scan signal D2U is high and the other is low.

It should be noted that the GOA circuit has two clock signals: the clock signal generating circuit comprises a first clock signal CK (1) and a second clock signal CK (2), wherein when an Nth clock signal CK (N) is the first clock signal, an (N +1) th clock signal CK (N) is the second clock signal, the pulse periods of the first clock signal CK (1) and the second clock signal CK (2) are the same, and the pulse signal of the former clock signal is generated at the same time when the pulse signal of the former clock signal is ended.

During forward scanning, the first transistor T1 of the first two-stage GOA unit receives the start signal STV, and from the third stage, the first transistor T1 receives the gate signal output signal G (N-2) of the last two-stage GOA unit; in the reverse scan, the second transistor T2 of the two terminal GOA cells receives the start signal STV, and the second transistor T2 receives the gate signal output signal G (N +2) of the next two GOA cells from the third last stage.

Referring to fig. 2, the GOA circuit further includes a leakage prevention module 500, the leakage prevention module 500 including a seventh transistor T7; the gate of the seventh transistor T7 is connected to the second potential, the source is electrically connected to the first node Q, and the drain is electrically connected to the pull-up node W.

Specifically, if the parasitic capacitance of the ninth transistor T9 is large enough, the pull-up node W is bootstrapped by the parasitic capacitance of the ninth transistor T9 when the ninth transistor T9 is turned on and the gate signal output signal g (N) transitions to a high potential, in order to prevent the high potential of the pull-up node W from being inversely sunk to the first node Q when the pull-up node W is bootstrapped to the high potential, the seventh transistor T7 is provided between the first node Q and the pull-up node W, the gate of the seventh transistor T7 is connected to the second level (the constant voltage high potential VGH when the seventh transistor T7 is an N-type transistor) to keep the seventh transistor T7 in an open state, the seventh transistor T7 is equivalent to a diode turned on by the first node Q in the direction of pulling up the node W when the potential of the first node Q is the constant voltage high potential VGH, the potential of the pull-up node W is prevented from being inversely sunk to the first node Q when the high potential of the pull-up node W is higher than the high potential of the first node Q, thereby maintaining the high potential bootstrapped by the pull-up node W.

Referring to fig. 2, the GOA circuit further includes a voltage stabilizing module 700, where the voltage stabilizing module 700 includes a first capacitor C1, one end of the first capacitor C1 is electrically connected to the first node Q, and the other end is connected to the first potential. The first capacitor C1 can maintain the high voltage level at the first node Q during the precharge phase and the low voltage level at the first node Q during the pull-down maintaining phase.

Referring to fig. 2, the GOA circuit further includes a global control module 600, wherein the global control module 600 includes a thirteenth transistor T13, a gate of the thirteenth transistor T13 is connected to the global control signal GAS, a source is connected to the first potential, and a drain is electrically connected to the nth gate signal output terminal g (N).

The module is to control the output ends g (n) of All the levels of GOA units to be converted into a first potential through the global control signal GAS, which is an All gate off function, and the function is to turn off the output ends g (n) of All the levels of GOA units when the touch scanning stage between the normal display stages arrives, so as to prevent the scan driving signal and the touch signal from generating interference.

It can be understood that, if each transistor in the GOA circuit is an N-type thin film transistor, that is, the thirteenth transistor T8 is an N-type thin film transistor, the global control signal GAS is at a high level when the touch scan stage arrives.

It should be noted that, referring to fig. 1, besides the level-pass function, the current GOA circuit often has an APO mode for Abnormal Power Off repair, which can control the NT12 to pull down the pull-down node P through the APO module composed of NT11 and NT12, and control the NT11 to pull up g (n) at the same time through the global control signal GAS1 when the Abnormal Power Off occurs, so as to open All the rows and send black pictures to avoid the display ghost, i.e. the All Gate on function. However, in practical use, the display panel rarely has an abnormal power failure, and even if the abnormal power failure occurs, the display screen can be restored to normal by starting up again, so that the function is not necessary, and referring to fig. 2, the GOA circuit provided by the present application removes the module, so that the structure of the GOA circuit is more simplified.

On the other hand, embodiments of the present application further provide a display panel including the GOA circuit as described above, and the display panel has the same structure and beneficial effects as the GOA circuit provided in the foregoing embodiments. Since the foregoing embodiments have described the structure and beneficial effects of the GOA circuit in detail, no further description is provided herein.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A GOA circuit comprising a plurality of cascaded GOA units, each of said GOA units comprising: the device comprises a positive and negative scanning module (100), an upward-pulling module (200), a downward-pulling module (300) and a downward-pulling maintaining module;

the positive and negative scanning module (100) is respectively electrically connected with a first node (Q) and an Nth-stage grid signal output end (G (N));

the pull-up module (200) is electrically connected with the nth stage gate signal output end (g (N));

the pull-down module (300) is electrically connected to the first node (Q), the nth gate signal output terminal (g (N)), and a first potential, respectively;

the pull-down maintaining module comprises a first pull-down maintaining circuit (401) and a second pull-down maintaining circuit (402) which are connected in a mirror image mode, the first pull-down maintaining circuit (401) and the second pull-down maintaining circuit (402) are respectively electrically connected with the first potential, the first pull-down maintaining circuit (401) is connected to a first low-frequency clock signal (LC1), the second pull-down maintaining circuit (402) is connected to a second low-frequency clock signal (LC2), and the phases of the first low-frequency clock signal (LC1) and the second low-frequency clock signal (LC2) are opposite; the first pull-down maintaining circuit (401) and the second pull-down maintaining circuit (402) alternately operate to maintain the nth stage gate signal output terminal (g (N)) and the first node (Q) at a first potential.

2. The GOA circuit of claim 1, wherein the first pull-down sustain circuit (401) comprises a second first transistor (T21), a second transistor (T22), a third transistor (T23), and a second capacitor (C2);

the sources of the second first transistor (T21) and the second third transistor (T23) are both connected to the first potential, and the drains of the second first transistor (T21) and the second transistor (T22) are both electrically connected to a second node (P1); the gate of the second transistor (T21) is electrically connected to the first node (Q); the gate of the second transistor (T22) is connected to the first low-frequency clock signal (LC1), and the source is connected to a second potential; a gate and a drain of the second third transistor (T23) are electrically connected to the second node (P1) and the first node (Q); one end of the second capacitor (C2) is connected to the first potential, and the other end is electrically connected to the second node (P1);

wherein the width-to-length ratio of the second first transistor (T21) is greater than the width-to-length ratio of the second transistor (T22);

the second pull-down sustain circuit 402 includes a third first transistor (T31), a third second transistor (T32), a third transistor (T33), and a third capacitor (C3);

the sources of the third transistor (T31) and the third transistor (T33) are both connected to the first potential, the drains of the third transistor (T31) and the third transistor (T32) are both electrically connected to the second node (P1), and the gate of the third transistor (T31) is electrically connected to the first node (Q); the gate of the third transistor (T32) is connected to the second low-frequency clock signal (LC2), and the source is connected to a second potential; a gate electrode of the third transistor (T33) is electrically connected to a third node (P2), and a drain electrode of the third transistor (T33) is electrically connected to the first node (Q); one end of the third capacitor (C3) is connected to the first potential, and the other end is electrically connected to a third node (P2);

wherein the width-to-length ratio of the third first transistor (T31) is greater than the width-to-length ratio of the third second transistor (T32).

3. The GOA circuit of claim 2, wherein all transistors of the GOA circuit are N-type thin film transistors, the first potential is a constant voltage low potential (VGL), and the second potential is a constant voltage high potential (VGH);

when the first pull-down maintaining circuit (401) is operated, the first node (Q) and the first low frequency clock signal (LC1) are both high, so that the second node (P1) is switched to low, so that the second three transistor (T23) is turned off, at this time, the first node (Q) is switched to low, and the second node (P1) is switched to high, so that the third transistor (T23) is turned on, and the second capacitor (C2) is charged, so that the first node (Q) is kept at the constant voltage low potential (VGL);

when the second pull-down maintaining circuit 402 is operated, the first node (Q) and the second low frequency clock signal (LC2) are both high, so that the third node (P2) is switched to low, so that the third transistor (T33) is turned off, at this time, the first node (Q) is switched to low, and the third node (P2) is switched to high, so that the third transistor (T33) is turned on, and the third capacitor (C3) is charged, so that the first node (Q) is maintained at the constant voltage low potential (VGL).

4. The GOA circuit of claim 1, wherein the pull-down module 300 comprises a fourth first transistor (T41) and a fourth transistor (T42);

the sources of the fourth first transistor (T41) and the fourth transistor (T42) are both connected to a first potential; a gate of the fourth transistor (T41) is electrically connected to the (N +2) th-stage gate signal output terminal G (N +2), and a drain thereof is electrically connected to the first node (Q); the gate of the fourth transistor (T42) is connected to the (N +1) th clock signal (CK (N +1)), and the drain is electrically connected to the nth stage gate signal output terminal (g (N)).

5. The GOA circuit of claim 1, wherein the forward-reverse scan module 100 comprises a first transistor (T1) and a second transistor (T2);

the grid of the first transistor (T1) is connected to the N-2 th stage grid signal output end G (N-2), the source is connected to the forward scanning signal (U2D), and the drain is electrically connected to the first node (Q);

the grid of the second transistor (T2) is connected to the (N +2) th-stage grid signal output end G (N +2), the source is connected to the reverse scanning signal (D2U), and the drain is electrically connected with the first node (Q);

one of the forward direction scan signal (U2D) and the reverse direction scan signal (D2U) is high and the other is low.

6. A GOA circuit according to claim 1, characterized in that it further comprises an anti-creeping module (500), which anti-creeping module (500) comprises a seventh transistor (T7); the gate of the seventh transistor (T7) is connected to the second potential, the source is electrically connected to the first node (Q), and the drain is electrically connected to the pull-up node (W).

7. The GOA circuit of claim 1, wherein the pull-up module (200) comprises a ninth transistor (T9), the gate of the ninth transistor (T9) is electrically connected to the pull-up node (W), the source is connected to the Nth clock signal CK (N), and the drain is electrically connected to the Nth gate signal output (G (N)).

8. A GOA circuit according to claim 1, further comprising a regulator module (600), the regulator module (600) comprising a first capacitor (C1), one end of the first capacitor (C1) being electrically connected to the first node (Q) and the other end being connected to the first potential.

9. The GOA circuit of claim 1, further comprising a global control module (700), wherein the global control module (700) comprises a thirteenth transistor (T13), the gate of the thirteenth transistor (T13) is connected to a global control signal (GAS), the source is connected to the first potential, and the drain is electrically connected to the Nth gate signal output terminal (G (N)).

10. A display panel comprising the GOA circuit of any one of claims 1-9.