CN111477141A

CN111477141A - Display screen structure capable of saving power consumption and driving method thereof

Info

Publication number: CN111477141A
Application number: CN202010270359.6A
Authority: CN
Inventors: 熊克; 谢建峰
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-04-08
Filing date: 2020-04-08
Publication date: 2020-07-31

Abstract

The invention discloses a display screen structure capable of saving power consumption and a driving method thereof, wherein the display screen structure comprises: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines; the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into six rows of sub-pixel pairs, each row of sub-pixel pair comprises two rows of sub-pixels, and each row of sub-pixels comprises an upper gate line and a lower gate line; a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, six TFT switches are formed in total, and the output end of each TFT switch is connected with the data line; the input ends of the TFT switches are respectively connected with the three source lines one by one; each row of sub-pixels comprises an upper gate line and a lower gate line, and each data line is used for connecting the two sub-pixels in each row of pixels. The technical scheme reduces the number of source lines and saves the power consumption of a pure color picture.

Description

Display screen structure capable of saving power consumption and driving method thereof

Technical Field

The invention relates to the field of display screens, in particular to a display screen structure capable of saving power consumption and a driving method thereof.

Background

The design of the display screen with the narrow frame and the full screen is mainstream, with the wide popularization of the display screen, from the aspect of screen occupation ratio, the initial generation iPhone screen occupation ratio in 2007 is only about 50%, in the following years, the mobile phone screen occupation ratio is continuously improved, but the improvement range is not large.

Disclosure of Invention

Therefore, it is desirable to provide a power-saving display panel structure and a driving method thereof, which can greatly reduce the number of source lines and reduce the manufacturing cost of the driving unit.

To achieve the above object, the present invention provides a display screen structure capable of saving power consumption, including: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines;

the pixel unit comprises a plurality of sub-pixels, the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels, the sub-pixels of each pixel unit are divided into six rows of sub-pixel pairs, and each row of sub-pixel pair comprises two rows of sub-pixels;

a data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT switch, the total number of the TFT switches is six, the output ends of the TFT switches are connected with the data lines, all the TFT switches are divided into two groups, the TFT switches are positioned at odd number positions and divided into one group, and the TFT switches are positioned at even number positions and divided into the other group according to the column sequence;

one Demux line is connected with the grid electrodes of one group of TFT switches of each pixel unit, the other Demux line is connected with the other group of TFT switches of each pixel unit and the grid lines, and the input ends of the three TFT switches of each group are respectively connected with the three source lines one by one;

each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

Further, one data line connects two subpixels in one subpixel pair, respectively.

Furthermore, the input ends of the TFT switch of the first column sub-pixel pair and the TFT switch of the fourth column sub-pixel pair are respectively connected with the first source line;

the input ends of the TFT switch of the second column of sub-pixel pairs and the TFT switch of the fifth column of sub-pixel pairs are respectively connected with a second source line;

the inputs of the TFT switches in the third column of pairs of sub-pixels and the TFT switches in the sixth column of pairs of sub-pixels are connected to a third source line, respectively.

Further, the display device further comprises a driving unit which is connected with the plurality of source lines.

Further, the plurality of sub-pixels are arranged in an array in sequence in the manner of R, G, B.

The inventor provides a driving method of a power-saving display screen structure, which is applied to the power-saving display screen structure in any one of the embodiments, and the driving method comprises the following steps:

opening a gate line of a row of sub-pixels;

sequentially opening two Demux lines during the opening period of one gate line;

during the opening period of one Demux line, the driving unit transmits signals to sub-pixels connected with data lines positioned at odd numbers through a source line, and during the opening period of the other Demux line, the driving unit transmits signals to sub-pixels connected with data lines positioned at even numbers through the source line;

opening another gate line of a row of sub-pixels;

sequentially turning on two Demux lines during the turning on of the other gate line;

and driving the sub-pixels of each row by circulating the steps.

Different from the prior art, the above technical solution greatly reduces the number of source lines, provides a better solution for reducing the length of the driving unit, and this embodiment also provides a novel implementation solution for realizing a full panel. In addition, the pixel connection mode provided by the method is matched with a special time sequence, so that the purpose of saving the power consumption of the pure color picture of the display screen can be achieved.

Drawings

Fig. 1 is an internal structure diagram of a display screen structure with power consumption saving according to a first embodiment of the present invention;

fig. 2 is a timing diagram of a power-saving display screen structure according to a first embodiment of the present invention;

fig. 3 is an internal structure diagram of a display screen structure with power consumption saving according to the second embodiment;

fig. 4 is a timing diagram of the display screen structure with power saving according to the second embodiment.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

Referring to fig. 1 to 4, a display panel structure with reduced power consumption of the present embodiment includes: the pixel structure comprises a plurality of pixel units and two Demux lines (Demux1 and Demux2), wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines (G1, G2, G3 and G4 …), six data lines (D1, D2 and D3 … D6) and three source lines (S1, S2 and S3). The pixel unit comprises a plurality of sub-pixels, and the sub-pixels of the pixel unit are arranged in an array mode and comprise a plurality of rows of sub-pixels. The sub-pixels of each pixel unit are divided into six columns of sub-pixel pairs, and each column of sub-pixel pair comprises two columns of sub-pixels. A data line is arranged between each column of sub-pixel pairs, each data line is connected with a TFT (Thin Film Transistor) switch, the total number of the TFT switches is six, and the output end of each TFT switch is connected with the data line. All TFT switches are divided into two groups, in column order, in the odd positions (on D1, D3, D5) into one group, and in the even positions (on D2, D4, D6) into another group. One Demux line is connected with the grid electrode of one group of TFT switches of each pixel unit, the other Demux line is connected with the other group of TFT switches of each pixel unit and the grid electrode line, and the input ends of the three TFT switches of each group are respectively connected with the three source lines one by one. Each row of sub-pixels comprises an upper gate line and a lower gate line, each data line is used for connecting the two sub-pixels in each row of pixels, and the two sub-pixels connected by each data line are respectively connected with the data line through one of the two gate lines in the row.

The technical scheme can reduce the number of Source lines (Source L ine) of a driving unit (IC) (less than the Source L ine of the conventional Demux or HSD) and make the IC narrower, thereby reducing the lower boundary (Border) of the display screen.

In this application (first and second embodiments), the display panel structure further includes a driving unit connected to the plurality of source lines. Because the drive unit is connected with the data line in the screen through the TFT switch, the HSD mode is used for arranging and designing the sub-pixels, and the number of the source lines is greatly reduced. Due to the fact that the number of the source lines is reduced, not only is the Y axis of the driving unit reduced, but also the manufacturing cost of the driving unit is saved, and components in the driving unit are reduced.

Referring to fig. 1, in the present application, a plurality of sub-pixels are sequentially arranged in an array in a manner of R (red), G (green), and B (blue). In some embodiments, the subpixel arrangement may be in other arrangements, such as R, B, G, R, B, G … arrangement, or may be similarly arranged with the addition of W (white).

Referring to fig. 1, in the present application, the gate lines are located at upper and lower sides of each row of sub-pixel pairs. Specifically, G1 and G2 are located at the upper and lower sides of the first row of sub-pixel pairs, G3 and G4 are located at the upper and lower sides of the second row of sub-pixel pairs, and G2n and G2n +1 are located at the upper and lower sides of the nth row of sub-pixel pairs.

Referring to fig. 1, in the first embodiment, the TFT switch of the first column sub-pixel pair (through D1) and the TFT switch of the fourth column sub-pixel pair (through D4) are respectively connected to the first source line; the TFT switch of the second column sub-pixel pair (through D2) and the TFT switch of the fifth column sub-pixel pair (through D5) are respectively connected with the second source line; the TFT switches in the third column subpixel pair (via D3) and the TFT switches in the sixth column subpixel pair (via D6) are connected to the third source line, respectively.

Specifically, S1 is connected through D1 in the display screen of Demux1, and R and G sub-pixels are connected to D1, and all the sub-pixels are on the left side of D1 (one data line is connected to each of two sub-pixels in one sub-pixel pair, but may be connected to each of two sub-pixels in two sub-pixel pairs); s1 is connected through D4 in the display screen of Demux2, and the D4 is connected with the R sub-pixel and the G sub-pixel, and the sub-pixels are both on the left side of D4, so that S1 only transmits the R/G sub-pixel data. S2 is connected through D2 in the display screen of the Demux1, and the sub-pixels B and R are connected to the D2 and are arranged on the left side of D2; s2 is connected through D5 in the display screen of Demux2, and the sub-pixels B and R are connected to D5, and the sub-pixels are on the left side of D5, so that S2 only transmits the data of the sub-pixels B/R. S3 is connected through D3 in a display screen of the Demux1, a G sub-pixel and a B sub-pixel are connected to the D3, and the sub-pixels are arranged on the left side of D3; s2 is connected through D6 in the display screen of Demux2, and the sub-pixels G and B are connected to D6, and the sub-pixels are on the left side of D6, so that S3 only transmits the data of the sub-pixels G/B. The pixel units are used as basic units, a plurality of pixel units can be arranged in order in the display screen surface of the framework, and the number of the pixel units can be selected according to the resolution ratios of different display screens.

Referring to FIG. 1, in a first embodiment, taking Data transmission on S as an example, the Data transmission sequence is represented by G → G → G → G.cndot.Gn, and referring to the timing diagram of FIG. 2, when G is on and Demux is on, S transmits sub-pixel R Data to D through Demux, as in FIG. 1, when G is on and Demux is on, S transmits sub-pixel G Data to D, as in FIG. 1, when G is still on and Demux is on, S transmits sub-pixel G Data to D through Demux, as in FIG. 1, and when S is on, G + R is on, and G + R.

It can be seen from the above that the data on S1 is repeatedly transmitted with R +/G-as the basic unit, the data on S2 is repeatedly transmitted with B +/R-as the basic unit, and the data on S3 is repeatedly transmitted with G +/B-as the basic unit, such a data transmission manner can reduce the frequency of positive and negative inversion of the Source voltage on the Source line (Source L ine). taking S1 as an example, the voltage on Source L ine is inverted into two G sub-pixel voltages through two R sub-pixel voltages, if the pure color picture, such as red, is the G sub-pixel and B sub-pixel voltages are both 0, the R sub-pixel data is R + (assuming that the frame is positive), when the display screen displays the pure color red picture, the voltage on Source L ine is not high → low → high-polarity inversion, but high → low → high → low → high pure color picture, and high → low → high → low power consumption of the pixel voltage can be left.

Fig. 2 is a timing diagram of a first embodiment, which is a timing diagram of data transmission at S1 in fig. 1, and is explained in fig. 1, and is not repeated herein.

Referring to fig. 3 and 4, in the second embodiment, the connection of pixels is still the same as that of the first embodiment, the connection relationship between Source L ine and Demux line is also the same as that of embodiment 1, and the second embodiment is characterized by changing timing of GIP so as to achieve the purpose of saving more power consumption than that of the first embodiment, in combination with the timing chart of fig. 4 of the second embodiment, in fig. 3 of the second embodiment, taking S1 as an example, the opening sequence of GIP is G1 → G3 → G2 → G4 → G6 → G8 → G5 → G7 → G → 28 → gng → wherein the opening sequence of G → 4 → G6 → G8 → G7 → G7 is a group of pixels (G → 2 +1 → gng → 3 → G → 7 → gnn → 7 → gnn → …), and the transmission pattern of the transmission of the group of pixels … is also shown as a group …, a transmission pattern 363672, a transmission pattern 36363672 is repeated.

In FIG. 3, when G1 is turned on and Demux1 is turned on, S1 passes the sub-pixel R data to D1 via Demux1, as shown in (1) of FIG. 3; when Demux2 is turned on while G1 remains turned on, S1 passes subpixel R data to D4 via Demux2 as shown in (2) of fig. 3; when G3 is turned on and Demux1 is turned on, S1 passes the subpixel R data to D1 through Demux1 as shown in (3) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes subpixel R data to D4 via Demux2, as shown at (4) in fig. 3; the principle of G5/G7 Data transmission is the same as G1/G3, and will not be described in detail. When G2 is turned on and Demux1 is turned on, S1 passes the sub-pixel G data to D1 via Demux1 as shown in (5) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes sub-pixel G data to D4 via Demux2 as shown at (6) in fig. 3; when G4 is turned on and Demux1 is turned on, S1 passes the sub-pixel G data to D1 via Demux1 as shown in (7) of fig. 3; when Demux2 is turned on while G2 remains turned on, S1 passes sub-pixel G data to D4 via Demux2 as shown at (8) in fig. 3; the transmission principle of G6/G8 is the same as that of G2/G4, and will not be described in detail.

In the second embodiment, for S1, GIP is turned on according to the transmission sequence G1 → G3 → G2 → G4 → G6 → G8 → G5 → G7, and the data transmission at S1 is repeated in one frame with the basic unit R +/G-/R +, when displaying a pure color picture such as red, the voltage at Source L ine transmits the G sub-pixel data of 8 voltages of 0V after transmitting the 4R sub-pixel data (± 5V), so that the voltage at Source L ine has a lower number of changes, i.e., the voltage at Source L ine has a lower frequency and the power consumption is lower, if the picture is a green picture, the voltage at Source L ine has a higher voltage than the voltage of 8G subpixels of green picture and then has a higher voltage of 0V, and thus the power consumption is more consistent with the picture voltage of red (the picture) and the picture is more power consumption is less than the picture (the picture is more consistent with the voltage of red picture).

Referring to fig. 4, a timing diagram of a second embodiment of the present invention, Data transmission of the timing diagram is described in fig. 3, and will not be described in detail herein. Under the time sequence diagram, the power consumption of the pure color picture of the display screen is lower.

In some embodiments, one data line connects one sub-pixel of one sub-pixel pair and one sub-pixel of the other sub-pixel pair, respectively, so that more types of sub-pixels can be provided for the source line.

The embodiment provides a driving method of a power consumption-saving display screen structure, which applies the power consumption-saving display screen structure described in the embodiment, and includes the following steps: one gate line of a row of sub-pixels is turned on. During the period that one gate line is opened, two Demux lines are sequentially opened. During the period that one Demux line (Demux1) is turned on, the driving unit transmits signals to sub-pixels connected to data lines (D1, D3, D5) located at odd-numbered positions through the source line, and during the period that the other Demux line (Demux2) is turned on, the driving unit transmits signals to sub-pixels connected to data lines (D2, D4, D6) located at even-numbered positions through the source line. The other gate line of a row of subpixels is turned on. During the other gate line is turned on, the two Demux lines are turned on in sequence. During the opening period of one Demux line, the driving unit transmits signals to the sub-pixels connected to the data lines positioned at odd numbers through the source lines, and during the opening period of the other Demux line, the driving unit transmits signals to the sub-pixels connected to the data lines positioned at even numbers through the source lines. And driving the sub-pixels of each row by circulating the steps.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims

1. A power-saving display screen structure, comprising: the pixel structure comprises a plurality of pixel units and two Demux lines, wherein each pixel unit comprises a plurality of sub-pixels, a plurality of gate lines, six data lines and three source lines;

2. The power-saving display screen structure of claim 1, wherein one data line connects two sub-pixels in one sub-pixel pair respectively.

3. The power-saving display panel structure of claim 1, wherein the input terminals of the TFT switches of the first column of sub-pixel pairs and the TFT switches of the fourth column of sub-pixel pairs are respectively connected to the first source line;

4. The power consumption-saving display structure according to claim 1, further comprising a driving unit connected to the plurality of source lines.

5. The power-saving display screen structure of claim 1, wherein the plurality of sub-pixels are arranged in an array R, G, B.

6. A driving method of a power consumption saving display screen structure, applied to the power consumption saving display screen structure of any one of claims 1 to 5, comprising the steps of:

opening a gate line of a row of sub-pixels;

opening another gate line of a row of sub-pixels;

and driving the sub-pixels of each row by circulating the steps.