CN111430352A

CN111430352A - Three-dimensional memory and manufacturing method thereof

Info

Publication number: CN111430352A
Application number: CN202010269894.XA
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-04-08
Filing date: 2020-04-08
Publication date: 2020-07-17

Abstract

The invention provides a three-dimensional memory and a manufacturing method thereof, wherein the three-dimensional memory comprises a stacked structure, the stacked structure comprises a memory block and a step structure positioned on the periphery of the memory block, the step structure comprises n × m steps, n and m are integers larger than 1 respectively, the step structure is provided with n first sub step areas in a first direction, each first sub step area is sequentially provided with a height difference of the m steps along the first direction, each first sub step area is provided with m second sub step areas in a second direction perpendicular to the first direction, and each second sub step area in the same first sub step area is sequentially provided with a height difference of the single step along the second direction. The invention also provides a manufacturing method of the three-dimensional memory. According to the manufacturing method provided by the invention, the number of the optical masks used for forming the stepped structure can be minimized, the occupied area of the formed stepped structure is greatly reduced, the manufacturing method has universality, and the next-generation three-dimensional memory supporting more stepped layers can be expanded.

Description

Three-dimensional memory and manufacturing method thereof

Technical Field

The invention relates to the field of semiconductors, in particular to a three-dimensional memory and a manufacturing process flow thereof.

Background

In order to meet the development of the high-efficiency and inexpensive microelectronics industry, a semiconductor memory device is required to have a higher integration density. Regarding semiconductor memory devices, since their integration density is very important in determining product prices, that is, high-density integration is very important. For conventional two-dimensional and planar semiconductor memory devices, since their integration density mainly depends on the unit area occupied by a single memory device, the degree of integration is very dependent on the quality of the photolithography and mask process. However, even though expensive processing equipment is continuously used to improve the precision of the photolithography and masking process, the improvement of the integration density is still very limited.

As an alternative to overcoming such two-dimensional limitations, three-dimensional semiconductor memory devices have been proposed that are expected to enable more reliable performance of the memory structure by a lower manufacturing cost process.

In a three-dimensional memory such as a 3D NAND flash memory, the memory array may include a core (core) region and a staircase region for contact to control gates in the layers of the memory array.

In the current overall structure of the three-dimensional memory, the step region occupies a large wafer area, and 5 or more reticles are used to form the step region. As the number of word line layers is further increased, a stepped region occupying a larger wafer surface is required, and the number of reticles has been increased to 8 blocks in order to form a stepped region of a 128-layer three-dimensional memory.

It can be understood that, in the semiconductor field, the manufacturing cost of the photomask is relatively high, and in order to reduce the manufacturing cost of the three-dimensional memory, the cost control of the photomask is a feasible scheme.

Therefore, there is a need for a three-dimensional memory and a manufacturing method thereof, which can minimize the number of photomasks required for forming the step region of the three-dimensional memory, and can be compatible with three-dimensional memories of various specifications, thereby providing universality.

Disclosure of Invention

The following presents a simplified summary of one or more aspects in order to provide a basic understanding of such aspects. This summary is not an extensive overview of all contemplated aspects, and is intended to neither identify key or critical elements of all aspects nor delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

In order to solve the above-mentioned problems, the present invention provides a three-dimensional memory, including a stacked structure, the stack structure comprises a memory block and a step structure positioned at the periphery of the memory block, the step structure comprises n × m steps, n and m are integers more than 1 respectively, wherein the stepped structure has n first sub-stepped regions in a first direction, each first sub-stepped region having a height difference of m steps in sequence along the first direction, each first sub-stepped region having m second sub-stepped regions in a second direction perpendicular to the first direction, each second sub-stepped region in the same first sub-stepped region having a height difference of a single step in sequence along the second direction, the step structure is located outside the memory block in the first direction, and a first sub-step region having a highest height in the step structure is adjacent to the memory block.

In an embodiment of the three-dimensional memory, optionally, the stacked structure includes a plurality of memory blocks arranged at intervals along the second direction and a staircase structure thereof, the staircase structure of each memory block is located at the same outer side of each memory block along the first direction, and the staircase structures of two memory blocks adjacent to each other along the second direction are symmetrical to each other along the second direction.

In an embodiment of the three-dimensional memory, optionally, the stacked structure includes a plurality of memory blocks arranged at intervals along the first direction and a staircase structure thereof, and the staircase structure of each memory block is alternately disposed at different outer sides of each memory block along the first direction.

The invention also provides a three-dimensional memory, which comprises a stacked structure, wherein the stacked structure comprises a memory block and a step structure positioned at the periphery of the memory block, the step structure comprises n × m steps, n and m are integers more than 1 respectively, wherein the stepped structure has n first sub-stepped regions in a first direction, each first sub-stepped region having a height difference of m steps in sequence along the first direction, each first sub-stepped region having m second sub-stepped regions in a second direction perpendicular to the first direction, each second sub-stepped region in the same first sub-stepped region having a height difference of a single step in sequence along the second direction, the step structure is located outside the memory block in the second direction, and a second sub-step region having the highest height among the first sub-step regions is adjacent to the memory block.

In an embodiment of the three-dimensional memory, optionally, the stacked structure includes a plurality of memory blocks arranged at intervals along the first direction and a staircase structure thereof, the staircase structure of each memory block is located on the same outer side of each memory block along the second direction, and the staircase structures of two memory blocks adjacent to each other in the first direction are symmetrical to each other along the first direction.

In an embodiment of the three-dimensional memory, optionally, the stacked structure includes a plurality of memory blocks arranged at intervals along the second direction and a stair structure thereof, and the stair structure of each memory block is alternately disposed at different outer sides of each memory block along the second direction.

The invention also provides a method for manufacturing a stepped structure of a three-dimensional memory, wherein the stepped structure comprises n × m steps, n and m are integers greater than 1, and the method specifically comprises the following steps:

etching the stacked structure of the three-dimensional memory for n times in a first direction to form n first sub-step regions; and

etching the stacked structure m times in a second direction perpendicular to the first direction to form m second sub-step regions; wherein

Each etching in the first direction is m-layer etching, each etching in the second direction is single-layer etching, so that each first sub-step area sequentially has the height difference of m steps along the first direction, and each second sub-step area in the same first sub-step area sequentially has the height difference of single step along the second direction; or

Each etching in the first direction is single-layer etching, each etching in the second direction is n-layer etching, so that each first sub-step area sequentially has the height difference of a single-step along the first direction, and each second sub-step area in the same first sub-step area sequentially has the height difference of n steps along the second direction.

In an embodiment of the above manufacturing method, optionally, etching the stacked structure of the three-dimensional memory n times in the first direction further includes:

forming a first photoresist layer with a first mask pattern above the stacked structure by using a first photomask, wherein the first mask pattern is a notch extending along the second direction;

etching the stacked structure by taking the first photoresist layer as a mask layer; and

trimming the first photoresist layer (n-1 times), and etching the stacked structure once after each trimming;

etching the stacked structure of the three-dimensional memory m times in the second direction further comprises:

forming a second photoresist layer with a second mask pattern above the stacked structure by using a second photomask, wherein the second mask pattern is a gap extending along the first direction;

etching the stacked structure by taking the second photoresist layer as a mask layer; and

and (m-1) trimming the second photoresist layer, and etching the stacked structure once after each trimming.

In an embodiment of the manufacturing method, optionally, the positions of the notches in the first mask pattern and the positions of the notches in the second mask pattern are configured to divide the stacked structure into four regions, so as to simultaneously form four independent sets of the step structures in the stacked structure, wherein the step structures are formed in the stacked structure

The two sets of stepped structures in the first direction are mirror symmetric with respect to the notches in the first mask pattern, and the two sets of stepped structures in the second direction are mirror symmetric with respect to the notches in the second mask pattern.

In an embodiment of the manufacturing method, optionally, the first mask pattern further includes a plurality of notches parallel to the first direction and extending along the second direction.

According to the three-dimensional memory and the manufacturing method thereof provided by the invention, the following technical effects can be produced:

(a) minimizing the number of photomasks used for forming a step structure in the three-dimensional memory;

(b) the floor area of a stepped structure area in the three-dimensional memory is reduced; and

(c) the method can be expanded to support the next generation of three-dimensional memories with more step layers while keeping the same number of masks or less than that of the traditional process method.

According to the three-dimensional memory and the manufacturing method thereof provided by the invention, the number of photomasks used for forming the step region can be minimized by performing multiple trimming and etching on the photoresist in the X and Y directions, for example, for a 64-layer three-dimensional memory, the number of photomasks required can be reduced from 5 to 2 to provide 9X9(81 or less) step layers. The manufacturing method provided by the invention can be expanded, for example, for a 128-layer three-dimensional memory, the number of photomasks required can be reduced from 8 to 2 so as to provide a step level of 12X12 (144). Meanwhile, the step structure in the three-dimensional memory formed by the method has the advantages that the occupied area is greatly reduced, and the occupied area of a wafer can be reduced.

Drawings

The above features and advantages of the present disclosure will be better understood upon reading the detailed description of embodiments of the disclosure in conjunction with the following drawings. In the drawings, components are not necessarily drawn to scale, and components having similar relative characteristics or features may have the same or similar reference numerals.

Fig. 1 is a schematic top view of a stacked structure of a three-dimensional memory provided by the present invention (including a core array region and a peripheral region) and a photoresist with a first mask pattern.

Fig. 2 is a schematic top view illustrating a stacked structure after a plurality of etching and trimming operations in a first direction according to the manufacturing method of the present invention.

Fig. 3A-3E are schematic structural diagrams illustrating respective intermediate steps of performing multiple etching and trimming on a stacked structure in a first direction by the manufacturing method provided by the present invention from the direction AA' of fig. 2.

Fig. 4 is a schematic top view of a stacked structure of a three-dimensional memory provided by the present invention (including a core array region and a peripheral region) and a photoresist with a second mask pattern.

Fig. 5 is a schematic top view illustrating a stacked structure after a plurality of etching and trimming operations in a second direction according to the manufacturing method of the present invention.

Fig. 6A-6E are schematic structural diagrams illustrating respective intermediate steps of performing multiple etching and trimming on the stacked structure in the second direction by the manufacturing method provided by the present invention from the direction BB' of fig. 5.

Fig. 7 shows a schematic top view of a staircase structure in a three-dimensional memory provided by the present invention and a schematic diagram of its respective memory blocks leading out of the core array region.

Fig. 8 is a schematic structural diagram illustrating an embodiment of a staircase structure in a three-dimensional memory according to the present invention.

Fig. 9A is a schematic structural diagram illustrating an embodiment of a staircase structure lead-out memory block in a three-dimensional memory provided by the present invention.

Fig. 9B is a schematic structural diagram illustrating another embodiment of a staircase structure lead-out memory block in a three-dimensional memory provided by the present invention.

Fig. 10A shows a front view of an embodiment of the stair-step structure of fig. 8.

Fig. 10B illustrates a right side view of an embodiment of the stair-step structure of fig. 8.

Reference numerals

1-81 steps

110. 120 core array region

111-114, 121-124 storage block

210. 220 nitride

310. 320 gap/first mask pattern

400 gap/second mask pattern

500 step structure region

511-521-524-511-524-step structure

600 stack structure

601 first sublayer

602 second sublayer

700 first photoresist layer

800 second photoresist layer

n1-n9, m1-m9 sub-ladder regions

Detailed Description

The invention is described in detail below with reference to the figures and specific embodiments. It is noted that the aspects described below in connection with the figures and the specific embodiments are only exemplary and should not be construed as imposing any limitation on the scope of the present invention.

The invention relates to a three-dimensional memory and a manufacturing method thereof. More particularly, embodiments of the present invention provide a staircase structure in a three-dimensional memory and a method for fabricating the same. The ladder structure in the three-dimensional memory and the manufacturing method thereof can minimize the number of photomasks used for forming the ladder structure, the occupied area of the formed ladder structure is greatly reduced, and the ladder structure has universality and can expand and support the next-generation three-dimensional memory with more step layers.

The following description is presented to enable any person skilled in the art to make and use the invention and is incorporated in the context of a particular application. Various modifications, as well as various uses in different applications will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to a wide range of embodiments. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the practice of the invention may not necessarily be limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.

The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

Note that where used, the designations left, right, front, back, top, bottom, positive, negative, clockwise, and counterclockwise are used for convenience only and do not imply any particular fixed orientation. In fact, they are used to reflect the relative position and/or orientation between the various parts of the object.

The terms "over.," under., "" between., "(between)," and ". on.," as used herein refer to the relative position of this layer with respect to other layers. Likewise, for example, a layer deposited or placed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Further, a layer deposited or placed between layers may be directly in contact with the layers or may have one or more intervening layers. In contrast, a first layer "on" a second layer is in contact with the second layer. In addition, the relative position of one layer with respect to the other layers is provided (assuming deposition, modification and removal of the thin film operations with respect to the starting substrate without regard to the absolute orientation of the substrate).

As described above, in order to minimize the number of photomasks used to form the staircase structure in the three-dimensional memory, so that the occupied area of the formed staircase structure is greatly reduced, and the next-generation three-dimensional memory supporting a larger number of staircase layers can be expanded, the present invention provides a three-dimensional memory and a method for manufacturing the same, and particularly relates to a staircase structure in a three-dimensional memory and a method for manufacturing the same, and please refer to fig. 1 to 7 for understanding the manufacturing method provided by the present invention.

Referring to fig. 1, fig. 1 is a schematic top view illustrating a stacked structure (including a core array region and a peripheral region) of a three-dimensional memory and a photoresist with a first mask pattern according to an aspect of the present invention. As shown in fig. 1, a stacked structure extending in a substrate height direction in a three-dimensional memory has been formed. Wherein, in a direction parallel to the substrate, the stacked structure includes a

core array region

110, 120 and a peripheral region located at the periphery of the core array region. Although not depicted in fig. 1, the area between the

core array regions

110 and 120 may be understood as the peripheral area of the three-dimensional memory. A plurality of memory blocks of the three-dimensional memory may be formed in the

core array regions

110, 120 to constitute a memory area of the three-dimensional memory. A stepped structure may be formed in the peripheral region to form a contact to electrically connect the word line of each individual control gate and lead out. The tops of the

core array regions

110, 120 are protected by the

nitrides

210, 220 in fig. 1, so as to ensure that the

core array regions

110, 120 are not erroneously etched during the subsequent etching of the step regions in the stacked structure, and can also be used as a contact stop layer for chemical mechanical planarization CMP.

In fig. 1, the top of the stacked structure of the three-dimensional memory is formed with a first photoresist layer with

first mask patterns

310, 320, it is noted that although the mask patterns are illustrated with dotted fills, the dotted fills actually illustrate the notched portions of the entire first photoresist layer. It should be understood by those skilled in the art that the first mask pattern can be formed by transferring a first photomask, i.e., only one photomask is needed to complete the etching in the first direction.

If the vertical direction of fig. 1 is a first direction and the horizontal direction is a second direction, it can be understood that the first mask pattern shown in fig. 1 includes a plurality of notches extending in parallel in the first direction and in the second direction.

The manufacturing method provided by the invention takes the first photoresist layer as a mask to etch the stacked structure, wherein the etching is mainly embodied in the step in the first direction, the etching comprises the step of trimming the first photoresist layer for multiple times, and the first photoresist layer is taken as the mask to etch the stacked structure after each trimming. If n × m steps are to be formed, the first photoresist layer may be trimmed (n-1) times by performing n etches in the first direction. In the first embodiment, each of the n times of etching is m-layer etching, and in the second embodiment, each of the n times of etching is single-layer etching.

Fig. 3A-3E are schematic structural diagrams illustrating respective intermediate steps of performing multiple etching and trimming on a stacked structure in a first direction by the manufacturing method provided by the present invention from the direction AA' of fig. 2. Fig. 3A-3E show schematic views of a second embodiment, i.e. a single layer etch per etch.

First, as shown in fig. 3A, a first photoresist layer 700 with a gap 310, i.e., an initial gap, is formed on the stacked structure 600. It is understood that the stacked structure 600 includes several stacked layers stacked in a height direction of the three-dimensional memory substrate, wherein each stacked layer includes a first sub-layer 601 and a second sub-layer 602, and those skilled in the art will understand that the first sub-layer 601 may be a metal layer, a polysilicon layer, etc. for forming three-dimensional memory gates/dummy gates, and the second sub-layer 602 may be an interlayer insulating layer for forming three-dimensional memory gates. The specific structure of the stacked structure 600 should not unduly limit the scope of the present invention, and may be set by those skilled in the art according to actual needs.

A schematic diagram of etching the top of the stack 600 using the first photoresist layer 700 with the initial notch as a mask is shown in fig. 3B. Since in the second embodiment the direction is a single layer etch, i.e. only one stack of layers (i.e. one set of first and second sub-layers) is etched at a time. It is understood that the etching can be implemented by those skilled in the art according to the existing or future means, and the specific implementation manner of the etching should not unduly limit the scope of the present invention.

A schematic view of the trimmed (trim) first photoresist layer 700 is shown in fig. 3C, where the gap 310 of the trimmed first photoresist layer 700 is shown enlarged. It will be appreciated that those skilled in the art may implement the above modifications in accordance with existing or future practices, and that the specific implementation of the modifications should not unduly limit the scope of the present invention.

Fig. 3D shows a schematic structure diagram after 2 etching operations are performed on the top of the stacked structure 600 after one trimming operation. It will be appreciated that in the second embodiment, the etching is still a single layer etching, i.e. all the stacked structures not blocked by the photoresist are lowered by one stacked layer in the height direction. It is understood that the etching can be implemented by those skilled in the art according to the existing or future means, and the specific implementation manner of the etching should not unduly limit the scope of the present invention.

After cycling through (n-1) trims and n etches, FIG. 3E shows the final structure. In addition, referring to fig. 2, since the first mask pattern is a strip notch pattern formed in the photoresist layer, a stacked layer structure of a plurality of concentric strip notches corresponding to the initial notches is formed after each trimming and etching, and thus, two groups of etched stacked structures are formed with the notches as centers when viewed from the direction of a-a'.

After the etching in the first direction is completed, the manufacturing method provided by the invention further comprises the step of etching the stacked structure in the second direction for multiple times. Referring to fig. 4, after the etching in the first direction is completed, a second photoresist layer with a second mask pattern 400 is formed on the top of the stacked structure of the three-dimensional memory, and it should be noted that although the mask pattern is illustrated by dot filling, the dot filling actually illustrates the gap portion of the entire second photoresist layer.

Still taking the vertical direction of fig. 4 as the first direction and the horizontal direction as the second direction, it is understood that the second mask pattern shown in fig. 4 includes notches extending in the first direction. It should be appreciated by those skilled in the art that the second mask pattern can be formed by transferring a second photomask, i.e., only one photomask is needed to complete the etching in the second direction.

The manufacturing method provided by the invention takes the second photoresist layer as a mask to etch the stacked structure, wherein the etching is mainly embodied in the step in the second direction, the etching comprises the step of trimming the second photoresist layer for multiple times, and the second photoresist layer is taken as the mask to etch the stacked structure after each trimming. If n × m steps are to be formed, the second photoresist layer may be trimmed (m-1) times by performing m etches in the second direction. In the first embodiment, each of the m times of etching is single-layer etching, and in the second embodiment, each of the m times of etching is n-layer etching.

Fig. 6A-6E are schematic structural diagrams illustrating respective intermediate steps of performing multiple etching and trimming on the stacked structure in the second direction by the manufacturing method provided by the present invention from the direction BB' of fig. 5. Fig. 6A-6E show schematic diagrams of a second embodiment, i.e. n-layer etches per etch. It is noted that for ease of understanding, none of the structures of the various intermediate steps shown in fig. 6A-6E overlap the etching that has been completed in the first direction.

First, as shown in fig. 6A, a second photoresist layer 800 with a gap 400, i.e., an initial gap, is formed over the stacked structure 600. It will be appreciated that the stacked structure 600 is still the stacked structure of fig. 3A-3E, and although the stacked structure 600 has completed the first direction step etch in the steps of fig. 6A-6E, for ease of understanding, none of the structures of the various intermediate steps shown in fig. 6A-6E overlap the etch that has completed in the first direction.

A schematic diagram of etching the top of the stack 600 using the second photoresist layer 800 with the initial notch as a mask is shown in fig. 6B. Since in the second embodiment there is n-layer etching in this direction, i.e. only n stacked layers (i.e. n sets of first and second sublayers) are etched at a time, 9 layers are shown in fig. 6B. It is understood that the etching can be implemented by those skilled in the art according to the existing or future means, and the specific implementation manner of the etching should not unduly limit the scope of the present invention.

A schematic diagram of the trimmed (trim) second photoresist layer 800 is shown in fig. 6C, where the gap 400 of the trimmed second photoresist layer 800 is shown enlarged. It will be appreciated that those skilled in the art may implement the above modifications in accordance with existing or future practices, and that the specific implementation of the modifications should not unduly limit the scope of the present invention.

Fig. 6D shows a schematic structure diagram after 2 times of etching the top of the stacked structure 600 after one trimming. It will be appreciated that in the second embodiment, the etch is still an n-layer etch, i.e. all stacked structures not blocked by the photoresist are lowered in height by n stacked layers. It is understood that the etching can be implemented by those skilled in the art according to the existing or future means, and the specific implementation manner of the etching should not unduly limit the scope of the present invention.

After cycling through (m-1) trims and m etches, the final structure is shown in FIG. 6E, with 8 trims and 9 etches shown in FIG. 6E. In addition, referring to fig. 5, since the second mask pattern is a strip notch pattern formed in the photoresist layer, a stacked layer structure of several concentric strip notches corresponding to the initial notches is formed after each trimming and etching. Although only one etched stack structure is formed when viewed from the direction B-B', two etched stack structures mirror-symmetrically in the second direction are actually formed on both sides of the notch with the notch 400 as the center.

Referring to fig. 5, the circled portion in fig. 5 is a set of step structures of a three-dimensional memory provided in an aspect of the present invention, and the circled portion means that the stacked structure of the portion is etched in both a first direction and a second direction, that is, the step structure overlaps n × m etches in the first direction and the second direction.

Referring to fig. 7, fig. 7 is a schematic top view showing a step region formed by etching, after removing nitride as a protection layer above the core array region, and performing a gap etching on the core array region to form a plurality of memory blocks of the three-dimensional memory. As shown in fig. 7, the memory blocks 111 and 112 and the memory blocks 121 and 122 are separated by a gap, and the positions of the first mask pattern and the second mask pattern are adjusted so that the stack structure etched in the first direction and the second direction has four partitions, each of which includes an

independent step structure

511, 512, 521 and 522, wherein each of the independent step structures includes n × m steps, and in the schematic diagram of fig. 7, 81 steps are shown.

Similarly, the memory blocks 113 and 114 and the memory blocks 123 and 124 are separated by a gap, and the positions of the first mask pattern and the second mask pattern are adjusted so that the stack structure after being etched in the first direction and the second direction has four partitions, each of which includes an

independent step structure

513, 514, 523, and 524, wherein each of the independent step structures includes n × m steps, and in the schematic diagram of fig. 7, 81 steps are shown.

A gap may be formed between the first set of memory blocks (including memory blocks 111 and 112 and memory blocks 121 and 122) and the second set of memory blocks (including memory blocks 113 and 114 and memory blocks 123 and 124), i.e., between memory blocks 112 and 113 and between memory blocks 122 and 123.

That is, according to the manufacturing method provided by the present invention, only two photomasks can be used to simultaneously form a step structure (corresponding to the step structure 511), a pair of step structures (corresponding to the

step structures

511 and 512 or the step structures 511 and 521), a group of step structures (corresponding to the

step structures

511, 512, 521 and 522), or even several groups of step structures on the corresponding sides of the memory block.

Since the manufacturing method provided by one aspect of the present invention forms a plurality of step structures by only two photomasks, it can be understood, with reference to fig. 7, that, for a plurality of memory blocks 111, 112, 113, 114 arranged at intervals in the vertical direction of fig. 7 (the first direction defined in fig. 1), the

step structures

511, 512, 513, 514 leading out of the plurality of memory blocks 111, 112, 113, 114 are located on the same outer side (both right sides) of the memory blocks 111, 112, 113, 114 in the horizontal direction of fig. 7 (the second direction defined in fig. 1). And two

step structures

511 and 512, 512 and 513 or 513 and 514 adjacent in the first direction are symmetrical to each other along the first direction, i.e., mirror-symmetrical about an axis (e.g., the slit described above) extending in the second direction.

For a plurality of memory blocks, such as the memory blocks 111 and 121, which are arranged at intervals in the second direction of fig. 7, the

step structures

511 and 521 leading out the memory blocks are alternately arranged on different outer sides of the respective memory blocks in the second direction, i.e., the step structure 511 is arranged on the right side of the memory block 111, and the step structure 521 is arranged on the left side of the memory block 121.

Therefore, the manufacturing method of the stepped structure provided by the invention can minimize the number of photomasks used for forming the stepped structure, the occupied area of the formed stepped structure is greatly reduced, and the stepped structure has universality and can expand and support the next-generation three-dimensional memory with more step layers.

Referring to fig. 8, the step structure in the three-dimensional memory provided by the present invention is further understood, and fig. 8 shows a step structure 511 formed after the etching in the first direction and the etching in the second direction are superimposed in the second embodiment, which corresponds to the memory block 111. The stepped structure shown in fig. 8 includes 9 × 9 steps for a total of 81 steps. It can be seen that each layer in the stacked structure is led out and uniquely led out by each step of the step structure to ensure that Contacts (CT) subsequently formed on each step control and uniquely control the gate layer in one stacked layer. The stepped structure can greatly reduce the area of the wafer occupied by the stepped area, thereby effectively reducing the cost and being capable of expanding to support the next generation of three-dimensional memories with more stepped layers.

Please further understand two different relationships between the staircase structure in the three-dimensional memory and the memory blocks of the core array region derived from the staircase structure provided by an aspect of the present invention with reference to fig. 9A and fig. 10A, 10B and fig. 9B and fig. 10A, 10B, respectively.

Referring to fig. 9A and fig. 10A and 10B, fig. 9A shows the case of the second embodiment, taking the staircase structure 511 as an example, that is, the staircase structure 511 leads the memory blocks 111 in the core array region from the second direction (defined in fig. 1). As can be understood in conjunction with fig. 10A and 10B, fig. 10A shows a front view of an embodiment of the stepped structure of fig. 8, and fig. 10B shows a right side view of an embodiment of the stepped structure of fig. 8. From the above-described attempted relationship, it can be understood that the horizontal direction in fig. 10A is the second direction defined in fig. 1, and the horizontal direction in fig. 10B is the first direction defined in fig. 1.

The second embodiment in fig. 9A features that the step structure 511 has n (9) sub-step regions (n 1-n9 in fig. 10A, for example, sub-step region n1 includes

steps

1, 10, 19, 28, 37, 46, 55, 64 and 73) in the second direction defined in fig. 1, each sub-step region n1-n9 has a height difference of m steps (9 steps) in the second direction in sequence, each sub-step region n1-n9 has m sub-step regions (m 1-m9 in fig. 10B, m sub-step regions corresponding to sub-step region n1 correspond to

steps

1, 10, 19, 28, 37, 46, 55, 64 and 73, respectively) in the first direction defined in fig. 1, and each sub-step region m1-m9 in the same sub-step region n1-n9 has a height difference of a single step in sequence in the first direction. Since the ladder structure 511 in fig. 9A leads the memory block 111 of the core array region from the second direction (defined in fig. 1), the highest sub-ladder region n1 is adjacent to the memory block 111 of the core array region.

Referring to fig. 9B and fig. 10A and 10B, fig. 9B shows the case of the first embodiment, taking the staircase structure 511 as an example, that is, the staircase structure 511 leads the memory blocks 111 in the core array region from the first direction (defined in fig. 1). As can be understood in conjunction with fig. 10A and 10B, fig. 10A shows a front view of an embodiment of the stepped structure of fig. 8, and fig. 10B shows a right side view of an embodiment of the stepped structure of fig. 8. From the above-described attempted relationship, it can be understood that the horizontal direction in fig. 10A is the second direction defined in fig. 1, and the horizontal direction in fig. 10B is the first direction defined in fig. 1.

The first embodiment in fig. 9B features that the stair structure 511 has m (9) sub-stair-step regions in the first direction defined in fig. 1 (m 1-m9 in fig. 10B, for example, sub-stair-step region m1 includes steps 73-81), each sub-stair-step region m1-m9 has a height difference of a single step in sequence along the first direction, each sub-stair-step region m1-m9 has n sub-stair-step regions in the second direction defined in fig. 1 (corresponding to m1, i.e., steps 73-81), each sub-stair-step region in the same sub-stair-step region m1-m9 has a height difference of an m steps in sequence along the second direction (step 73 is 9 steps higher than step 74 as shown in fig. 9B). Since the stepped structure 511 in fig. 9B leads the memory block 111 of the core array region from the first direction (defined in fig. 1), the highest sub-step region m9 is adjacent to the memory block 111 of the core array region.

Thus, various embodiments of the three-dimensional memory and methods of fabricating the same provided by the present invention have been described. The manufacturing method provided by the invention can form a step structure containing n × m steps by only adopting two photomask plates. The manufacturing method provided by the invention forms the step structure by trimming the photoresist as a mask in one direction (n-1 times), etching the stack layer in the one direction n times, trimming the photoresist as a mask in the other direction (m-1) times, and etching the stack layer in the other direction m times. In an embodiment of the above etching, the etching in one direction may be single layer etching, and the etching in the other direction is n layer etching. Alternatively, in another embodiment, the etch in one direction may be an m-layer and the other direction is a single layer etch. Therefore, each stacked layer in the stacked structure can be led out and led out only by the n × m steps of the stepped structure, and n × m contacts can be formed on the n × m steps through a back-end process of a semiconductor process, so that the gate electrode layer in the corresponding stacked layer can be led out and controlled only.

(d) minimizing the number of photomasks used for forming a step structure in the three-dimensional memory;

(e) the floor area of a stepped structure area in the three-dimensional memory is reduced; and

(f) the method can be expanded to support the next generation of three-dimensional memories with more step layers while keeping the same number of masks or less than that of the traditional process method.

Although the present disclosure has been described with respect to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the disclosure. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, it can be seen that various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Reference in the specification to one embodiment or an embodiment is intended to include within at least one embodiment of a circuit or method a particular feature, structure, or characteristic described in connection with the embodiment. The appearances of the phrase one embodiment in various places in the specification are not necessarily all referring to the same embodiment.

Claims

1. The utility model provides a three-dimensional memory, includes the stacked structure, the stacked structure includes the memory block and is located memory block outlying stair structure, stair structure includes n m level steps, n, m are respectively for being greater than 1 integer, its characterized in that, stair structure has n first sub-ladder district in the first direction, and each first sub-ladder district is followed the first direction has the difference in height of m level steps in proper order, and each first sub-ladder district is perpendicular to m second sub-ladder district has in the second direction of first direction, and each second sub-ladder district in same first sub-ladder district is followed the second direction has the difference in height of single-stage step in proper order, stair structure is located memory block follows the outside of first direction, the first sub-ladder district that the height is the highest in stair structure borders on memory block.

2. The three-dimensional memory according to claim 1, wherein the stacked structure includes a plurality of memory blocks arranged at intervals in the second direction and a staircase structure thereof, the staircase structure of each memory block is located on the same outer side of each memory block in the first direction, and the staircase structures of two memory blocks adjacent in the second direction are symmetrical to each other in the second direction.

3. The three-dimensional memory according to claim 1, wherein the stacked structure includes a plurality of memory blocks arranged at intervals in the first direction and a staircase structure thereof, the staircase structure of each memory block being alternately disposed at different outer sides of each memory block in the first direction.

4. The utility model provides a three-dimensional memory, includes the stacked structure, the stacked structure includes the memory block and is located memory block outlying stair structure, stair structure includes n m level steps, n, m are respectively for being greater than 1 integer, its characterized in that, stair structure has n first sub-ladder district in the first direction, and each first sub-ladder district is followed the first direction has the difference in height of m level steps in proper order, and each first sub-ladder district is perpendicular to m second sub-ladder districts have in the second direction of first direction, and each second sub-ladder district in same first sub-ladder district is followed the second direction has the difference in height of single-stage step in proper order, stair structure is located memory block follows the outside of second direction, the second sub-ladder district that the height is the highest in each first sub-ladder district borders on memory block.

5. The three-dimensional memory according to claim 4, wherein the stacked structure includes a plurality of memory blocks arranged at intervals in the first direction and a staircase structure thereof, the staircase structure of each memory block is located on the same outer side of each memory block in the second direction, and the staircase structures of two memory blocks adjacent in the first direction are symmetrical to each other in the first direction.

6. The three-dimensional memory according to claim 4, wherein the stacked structure includes a plurality of memory blocks arranged at intervals in the second direction and a staircase structure thereof, the staircase structure of each memory block being alternately disposed at different outer sides of each memory block in the second direction.

7. A method for manufacturing a stair structure of a three-dimensional memory, wherein the stair structure comprises n × m steps, and n and m are integers greater than 1, the method comprising the steps of:

8. The method of manufacturing of claim 7, wherein etching the stacked structure of the three-dimensional memory n times in the first direction further comprises:

forming a first photoresist layer with first mask patterns above the stacked structure by using a first photomask, wherein the first mask patterns are gaps extending along the second direction;

etching the stacked structure of the three-dimensional memory m times in a second direction further comprises:

9. The manufacturing method according to claim 8, wherein the positions of the notches in the first mask pattern and the positions of the notches in the second mask pattern are arranged to divide the stacked structure into four regions to simultaneously form four independent sets of the stair-step structures in the stacked structure, wherein

10. The method of manufacturing of claim 9, wherein the first mask pattern further comprises a plurality of notches parallel in the first direction and extending along the second direction.