CN111415930B - Electrostatic discharge protection structure and electrostatic discharge protection circuit - Google Patents
Electrostatic discharge protection structure and electrostatic discharge protection circuit Download PDFInfo
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
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Abstract
An electrostatic discharge protection structure and an electrostatic discharge protection circuit, the structure includes: the substrate is provided with two parallel and isolated drift regions; the LDMOS transistor is positioned in each drift region and comprises a grid structure positioned on the substrate, a body region positioned in the drift region on one side of the grid structure, and a source region and a drain region which are respectively positioned on two sides of the grid structure, wherein the grid structure crosses the boundary surface of the drift region and the body region, the source region is positioned in the body region, the drain region is positioned in the drift region, and the body region is connected with the source region; the source regions in the two drift regions are connected; the drain region in one drift region is connected to the electrostatic discharge input terminal, and the drain region in the other drift region is connected to the ground terminal. The invention is beneficial to discharging the static current when the static discharge input end is negative pressure or positive pressure, avoids the reverse flow of the negative pressure signal in the static discharge protection structure when the chip protected by the static discharge protection structure works normally, and reduces the chip area occupied by the static discharge protection structure.
Description
Technical Field
The embodiment of the invention relates to the field of electrostatic discharge protection, in particular to an electrostatic discharge protection structure and an electrostatic discharge protection circuit.
Background
The electrostatic discharge phenomenon is a common phenomenon in the manufacturing, production, assembly, test, storage, transportation, etc. of semiconductor devices or circuits, and an excessive charge carried by the phenomenon is transferred into the integrated circuit via the input/output pin of the integrated circuit in a very short time, thereby damaging the internal circuit of the integrated circuit.
In order to solve this problem, it is usually necessary to provide a protection circuit between the internal circuit and the input/output pin, and the protection circuit must be activated before the pulse current of the Electrostatic Discharge reaches the internal circuit to rapidly eliminate the excessive voltage, thereby reducing the damage caused by the ESD (Electrostatic Discharge) phenomenon.
Power management ICs (Integrated circuits), driver ICs and automotive ICs play an important role in everyday applications, and high voltage ESD protection is increasingly important for these IC devices, but these high voltage IC devices result in poor electrostatic discharge performance (ESD robustness) due to their inherent weak electrostatic stress bearing capability. Moreover, when the voltage applied to the input/output pin of the power management IC (integrated circuit), the driver IC, and the auto IC is negative, the parasitic diode in the esd protection structure is turned on in the forward direction, and a signal cannot be normally input or output to the inside/outside of the chip, thereby disabling the chip.
In addition, the high voltage pin in the IC is also sensitive to latch-up, and when the IC is powered for stress ESD testing, if the holding voltage of the ESD clamp protection device is lower than the supply voltage, the ESD clamp device will be turned on all the time after the ESD testing is completed, which may result in large current and damage to the high voltage IC device.
Disclosure of Invention
The present invention provides an electrostatic discharge protection structure and an electrostatic discharge protection circuit, which reduce the chip area occupied by the electrostatic discharge protection structure while preventing the electrostatic current from leaking when the electrostatic discharge input terminal is negative or positive, and preventing the negative voltage signal from flowing backward in the electrostatic discharge protection structure when the chip protected by the electrostatic discharge protection structure is working normally.
To solve the above problems, an embodiment of the present invention provides an electrostatic discharge protection structure, including: the substrate is internally provided with two parallel-arranged and isolated drift regions; the LDMOS transistor is positioned in each drift region and comprises a grid structure positioned on the substrate, a body region positioned in the drift region on one side of the grid structure, and a source region and a drain region which are respectively positioned on two sides of the grid structure, wherein the grid structure stretches across the boundary surfaces of the drift region and the body region, the source region is positioned in the body region, the drain region is positioned in the drift region, and the body region is connected with the source region; the source regions in the two drift regions are connected with each other; drain regions in one drift region are connected with the electrostatic discharge input end, and drain regions in the other drift region are connected with the grounding end; the drift region, the source region and the drain region are of a first conductivity type, the body region is of a second conductivity type, and the first conductivity type is different from the second conductivity type.
Optionally, in each LDMOS transistor, a resistor is connected between the gate structure and the corresponding source region, and a capacitor is connected between the gate structure and the corresponding drain region.
Optionally, a product of the resistance value of the resistor and the capacitance value of the capacitor is less than 2 μ s.
Optionally, the voltage at the electrostatic discharge input terminal is positive voltage or negative voltage.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type.
Optionally, the LDMOS transistor is a common source-drain LDMOS transistor.
Optionally, a body region contact region is arranged in the source region, the body region contact region is in contact with the body region, and the body region contact region is of a second conductivity type; the body region contact region is connected with the source region.
Optionally, in each of the drift regions, a distance from each of the body regions to an adjacent drain region is equal.
Optionally, the electrostatic discharge protection structure is a mirror-symmetric structure.
Optionally, the ion doping concentrations in the two drift regions are the same, and the ion doping concentration in each body region is the same.
Optionally, the electrostatic discharge protection structure further includes: and the guard ring structure comprises a first well region surrounding each drift region, a second well region surrounding the first well region and a third well region surrounding the second well region, wherein the first well region and the third well region are of a second conductivity type, and the second well region is of a first conductivity type.
Optionally, each of the first well region, the second well region, and the third well region is provided with a well region contact region, and the well region contact region has the same conductivity type as the corresponding well region, the well region contact region in each of the first well region and the third well region is connected to a ground terminal, and the well region contact region in each of the second well region is connected to a power supply terminal.
Optionally, the third well region is shared between the two drift regions.
Optionally, the substrate is of a second conductivity type; the electrostatic discharge protection structure further comprises: and the fourth well region is positioned in the substrate at the bottom of the drift region, is of the first conduction type, and has ion doping concentration lower than that in the drift region.
Accordingly, an embodiment of the present invention further provides an electrostatic discharge protection circuit, including: a first LDMOS transistor; a second LDMOS transistor; in the first LDMOS transistor and the second LDMOS transistor, the source electrodes are in short circuit with the substrate; the source electrodes of the first LDMOS transistor and the second LDMOS transistor are connected with each other; the drain electrodes of the first LDMOS transistors are connected with the electrostatic discharge input end, and the drain electrodes of the second LDMOS transistors are connected with the grounding end.
Optionally, in the first LDMOS transistor and the second LDMOS transistor, a resistor is connected between the gate and the corresponding source, and a capacitor is connected between the gate and the corresponding drain.
Optionally, a product of the resistance value of the resistor and the capacitance value of the capacitor is less than 2 μ s.
Optionally, the voltage at the electrostatic discharge input terminal is a positive voltage or a negative voltage.
Optionally, the first LDMOS transistor and the second LDMOS transistor are N-type transistors.
Optionally, the first LDMOS transistor and the second LDMOS transistor are common source-drain transistors.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the electrostatic discharge protection structure comprises an LDMOS transistor, and by taking the first conduction type as an N type and the second conduction type as a P type as an example, when a chip protected by the electrostatic discharge protection structure works, the electrostatic discharge input end is connected to a signal line, and when the voltage of the signal line is positive voltage, a parasitic diode formed by a drain region and a body region cannot be conducted reversely in a drift region where the drain region connected with the signal line is located, so that the electrostatic discharge protection structure cannot be started; when the voltage of the signal line is negative pressure, a parasitic diode formed by the drain region and the body region cannot be conducted reversely in the drift region where the drain region connected with the grounding end is located, and the electrostatic discharge protection structure cannot be started, so that the problem that the current flows backwards in the electrostatic discharge protection structure when the voltage of the signal line is negative pressure is avoided. When the chip protected by the electrostatic discharge protection structure does not work and the voltage of the electrostatic discharge input end is negative voltage, a parasitic triode formed by the drain region, the body region and the source region is turned on in a drift region where the drain region connected with the grounding end is located, so that electrostatic current is conducted to the body region of the other drift region through the source region, and the body region and the drift region in the other drift region form a forward conducting diode, so that the electrostatic current is discharged; similarly, when the chip protected by the electrostatic discharge protection structure does not work and the voltage of the electrostatic discharge input end is positive, a parasitic triode formed by the drain region, the body region and the source region is turned on in a drift region where the drain region connected with the electrostatic discharge input end is located, so that electrostatic current is conducted into the body region of the other drift region through the source region, and the body region in the other drift region is conducted in the forward direction with a diode formed by the drift region, so that the electrostatic current is discharged.
And, the LDMOS transistor is a high-voltage device, under the condition that the voltage absolute value of the electrostatic discharge input end is the same, compared with the scheme that the electrostatic discharge protection structure discharges the electrostatic current through a diode or an MOS transistor, the LDMOS transistor with less quantity is adopted to discharge the electrostatic current, thereby being beneficial to reducing the chip area occupied by the electrostatic discharge protection structure and improving the area utilization rate of the chip.
In an alternative scheme, in each LDMOS transistor, a resistor is connected between the gate structure and the corresponding source region, a capacitor is connected between the gate structure and the corresponding drain region, the resistor and the capacitor form capacitance-resistance coupling, when an electrostatic signal comes, the capacitor is turned on, so that a voltage is applied to the gate structure to turn on the LDMOS transistor, and a current is conducted through a channel.
Drawings
FIG. 1 is a schematic structural diagram of an ESD protection structure;
FIG. 2 is a schematic structural diagram of another ESD protection structure;
FIG. 3 is a schematic structural diagram of an ESD protection structure according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of an esd protection circuit according to an embodiment of the invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason of poor performance of the device is analyzed by combining an electrostatic discharge protection structure.
Referring to fig. 1, a schematic diagram of an esd protection structure is shown.
The electrostatic discharge protection structure includes: a substrate 1, wherein a first portion (not labeled) of an electrostatic discharge protection structure and a second portion (not labeled) of the electrostatic discharge protection structure are formed in the substrate 1; the first part and the second part of the electrostatic discharge protection structure both comprise a plurality of diodes 3 arranged in parallel, each diode 3 comprises a well region 2, and a first doped region 4 and a second doped region 5 which are positioned in the well region 2 and are isolated from each other; the second doping region 5 of the previous diode 3 in the first part of the electrostatic discharge protection structure is connected with the first doping region 4 of the next diode 3, the first doping region 4 of the previous diode 3 in the second part of the electrostatic discharge protection structure is connected with the second doping region 5 of the next diode 3, and the second doping region 5 of the last diode 3 in the first part of the electrostatic discharge protection structure is connected with the second doping region 5 of the first diode 3 in the second part of the electrostatic discharge protection structure; the first doping region 4 of the first diode 3 of the first part of the electrostatic discharge protection structure is connected with an electrostatic discharge input end In, and the first doping region 4 of the last diode 3 of the second part of the electrostatic discharge protection structure is connected with a ground end GND; the well region 2 and the first doped region 4 are of a first conductivity type, the second doped region 5 is of a second conductivity type, and the first conductivity type is different from the second conductivity type.
When the chip protected by the esd protection structure does not work, taking the first conductivity type In the esd protection structure as P-type and the In voltage at the esd input end as negative voltage as an example, the diodes 3 In the second part of the esd protection structure are all biased forward, thereby releasing the esd current. However, when the voltage of the esd input terminal In is negative voltage, the diodes 3 In the first portion of the esd protection structure are all reverse biased, but the reverse on-resistance of the diodes 3 is relatively large, so that the speed of the esd protection structure for discharging the esd current is reduced, and the capability of the esd protection structure for discharging the esd current is relatively poor.
Referring to fig. 2, a schematic structural diagram of another esd protection structure is shown.
The electrostatic discharge protection structure includes: a substrate 10, wherein a first portion (not labeled) of an esd protection structure and a second portion (not labeled) of the esd protection structure are formed in the substrate 10, the first portion and the second portion of the esd protection structure both include a plurality of MOS transistors 11 arranged in parallel and connected in series, each MOS transistor 11 includes a well region 12, a gate structure 13 located on the well region 12, and a source region 14 and a drain region 15 located in the well region 12 on two sides of the gate structure 13, respectively; the drain region 15 of the previous MOS transistor 11 in the first electrostatic discharge part is connected with the source region 14 of the next MOS transistor 11, the source region 14 of the previous MOS transistor 11 in the second electrostatic discharge protection structure part is connected with the drain region 15 of the next MOS transistor 11, and the source region 14 of the last MOS transistor 11 in the first electrostatic discharge protection structure part is connected with the source region 14 of the first MOS transistor 11 in the second electrostatic discharge protection structure part; the drain region 15 of the first MOS transistor 11 In the first part of the esd protection structure is connected to the esd input terminal In, and the source region 14 of the last MOS transistor 11 In the second part of the esd protection structure is connected to the ground terminal GND; the well region 12 is of a first conductivity type, the source region 14 and the drain region 15 are of a second conductivity type, and the first conductivity type is different from the second conductivity type.
When the chip protected by the electrostatic discharge protection structure does not work, taking the example that the first conduction type is an N type and the electrostatic discharge input end In is negative pressure In the electrostatic discharge protection structure, the MOS transistor In the first part of the electrostatic discharge protection structure is all conducted In the forward direction, so that electrostatic current is discharged, the MOS transistor In the second part of the electrostatic discharge protection structure is conducted In the reverse direction, and compared with a diode, the reverse conduction resistance of the MOS transistor is smaller, so that the electrostatic discharge protection structure can discharge electrostatic discharge current faster. However, the MOS transistors have a lower operating voltage, and when the voltages at the electrostatic discharge input terminals are the same, a larger number of MOS transistors are required to discharge the electrostatic current, so that the chip area occupied by the electrostatic discharge protection structure is larger, and the area utilization rate of the chip is reduced.
In order to solve the above technical problem, the present invention provides an electrostatic discharge protection structure, including: the substrate is internally provided with two parallel and isolated drift regions; the LDMOS transistor is positioned in each drift region and comprises a grid structure positioned on the substrate, a body region positioned in the drift region on one side of the grid structure, and a source region and a drain region which are respectively positioned on two sides of the grid structure, wherein the grid structure stretches across the boundary surfaces of the drift region and the body region, the source region is positioned in the body region, the drain region is positioned in the drift region, and the body region is connected with the source region; the source regions in the two drift regions are connected with each other; drain regions in one drift region are connected with the electrostatic discharge input end, and drain regions in the other drift region are connected with the grounding end; the drift region, the source region and the drain region are of a first conductivity type, the body region is of a second conductivity type, and the first conductivity type is different from the second conductivity type.
The electrostatic discharge protection structure comprises an LDMOS transistor, and by taking the first conduction type as an N type and the second conduction type as a P type as an example, when a chip protected by the electrostatic discharge protection structure works, the electrostatic discharge input end is connected to a signal line, and when the voltage of the signal line is positive voltage, a parasitic diode formed by a drain region and a body region cannot be conducted reversely in a drift region where the drain region connected with the signal line is located, so that the electrostatic discharge protection structure cannot be started; when the voltage of the signal line is negative pressure, a parasitic diode formed by the drain region and the body region cannot be conducted reversely in the drift region where the drain region connected with the grounding end is located, and the electrostatic discharge protection structure cannot be started, so that the problem that the current flows backwards in the electrostatic discharge protection structure when the voltage of the signal line is negative pressure is avoided.
When the chip protected by the electrostatic discharge protection structure does not work and the voltage of the electrostatic discharge input end is negative voltage, a parasitic triode formed by the drain region, the body region and the source region is turned on in a drift region where the drain region connected with the grounding end is located, so that electrostatic current is conducted to the body region of the other drift region through the source region, and the body region and the drift region in the other drift region form a forward conducting diode, so that the electrostatic current is discharged; similarly, when the chip protected by the electrostatic discharge protection structure does not work and the voltage of the electrostatic discharge input end is positive, a parasitic triode formed by the drain region, the body region and the source region is turned on in a drift region where the drain region connected with the electrostatic discharge input end is located, so that electrostatic current is conducted into the body region of the other drift region through the source region, and the body region in the other drift region is conducted in the forward direction with a diode formed by the drift region, so that the electrostatic current is discharged.
And, the LDMOS transistor is a high-voltage device, under the condition that the voltage absolute value of the electrostatic discharge input end is the same, compared with the scheme that the electrostatic discharge protection structure discharges the electrostatic current through a diode or an MOS transistor, the LDMOS transistor with less quantity is adopted to discharge the electrostatic current, thereby being beneficial to reducing the chip area occupied by the electrostatic discharge protection structure and improving the area utilization rate of the chip.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention more comprehensible, embodiments of the present invention are described in detail below with reference to the accompanying drawings.
Referring to fig. 3, a schematic structural diagram of an embodiment of an esd protection structure of the present invention is shown.
The electrostatic discharge protection structure includes: the substrate 100, wherein the substrate 100 has two parallel arranged and isolated drift regions 101 therein; an LDMOS transistor 110 located in each of the drift regions 101, wherein the LDMOS transistor 110 includes a gate structure 103 located on the substrate 100, a body region 102 located in the drift region 101 at one side of the gate structure 103, and a source region 104b and a drain region 104a located at two sides of the gate structure 103, respectively, the gate structure 103 crosses over the interface surfaces of the drift region 101 and the body region 102, the source region 104b is located in the body region 102, the drain region 104a is located in the drift region 101, and the body region 102 is connected to the source region 104 b; the source regions 104b in both of the drift regions 101 are connected to each other; drain regions 104a IN one drift region 101 are all connected with an electrostatic discharge input terminal IN, and drain regions 104a IN the other drift region 101 are all connected with a ground terminal VSS; the drift region 101, the source region 104b, and the drain region 104a are of a first conductivity type, the body region 102 is of a second conductivity type, and the first conductivity type is different from the second conductivity type.
The esd protection structure according to the embodiment of the present invention includes LDMOS transistors 110, where the LDMOS transistors 110 are located IN a corresponding drift region 101, and drain regions 104a IN one drift region 101 are all connected to an esd input terminal IN, and drain regions 104a IN the other drift region 101 are all connected to a ground terminal VSS.
Taking the first conductivity type as an N-type and the second conductivity type as a P-type as an example, when the chip protected by the electrostatic discharge protection structure works, the electrostatic discharge input terminal IN is connected to the signal line, and when the voltage of the signal line is positive voltage, a parasitic diode formed by the drain region 104a and the body region 102 IN the drift region 101 where the drain region 104a connected to the signal line is located is not reversely conducted, so that the electrostatic discharge protection structure is not turned on; when the voltage of the signal line is a negative voltage, in the drift region 101 where the drain region 104a connected to the ground terminal VSS is located, the parasitic diode formed by the drain region 104a and the body region 102 is not reversely conducted, and the electrostatic discharge protection structure is not turned on, so that the problem of current backflow in the electrostatic discharge protection structure when the voltage of the signal line is a negative voltage is advantageously avoided.
When the chip protected by the electrostatic discharge protection structure does not work and the electrostatic discharge input terminal IN is a negative voltage, IN the drift region 101 where the drain region 104a connected with the ground terminal VSS is located, a parasitic triode formed by the drain region 104a, the body region 102 and the source region 104b is turned on, so that current is conducted into the body region 102 IN another drift region 101 through the source region 104b, and the body region 102 and the drift region 101 IN another drift region 101 form a forward conducting diode, so that electrostatic current is discharged, and therefore the problem of current backflow when the voltage of a signal line is a negative voltage is avoided; similarly, when the chip protected by the esd protection structure does not operate and the voltage of the esd input terminal IN is a positive voltage, IN the drift region 101 where the drain region 104a connected to the esd input terminal IN is located, a parasitic transistor formed by the drain region 104a, the body region 102 and the source region 104b is turned on, so that an electrostatic current is conducted into the body region 102 of another drift region 101 through the source region 104b, and a diode formed by the body region 102 and the drift region 101 IN another drift region 101 is conducted IN a forward direction, so as to drain the electrostatic current.
Moreover, the LDMOS transistor is a high-voltage device, and under the condition that the absolute value of the voltage of the electrostatic discharge input end IN is the same, compared with the scheme that the electrostatic discharge protection structure discharges the electrostatic current through a diode or an MOS transistor, the LDMOS transistor with less quantity is adopted to discharge the electrostatic current, so that the occupied chip area of the electrostatic discharge protection structure is favorably reduced, and the area utilization rate of the chip is improved.
The substrate 100 is used to provide a process platform for forming an esd protection structure.
In this embodiment, the LDMOS transistor 110 is taken as a planar transistor as an example, and the substrate 100 is a planar substrate. In other embodiments, when the LDMOS transistor is a fin field effect transistor, the substrate comprises a substrate and a discrete fin portion on the substrate.
In this embodiment, the base 100 is a silicon substrate. In other embodiments, the base may also be a substrate made of other materials such as a germanium substrate, a silicon carbide substrate, a gallium arsenide substrate, or an indium gallium arsenide substrate, and the base may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate.
The drift region 101 is used to withstand a larger bias voltage, thereby increasing the breakdown voltage of the LDMOS transistor 110.
In this embodiment, the LDMOS transistor 110 is an N-type transistor, and the N-type transistor has a high carrier concentration, a high conductivity, and a low on-resistance, which is beneficial to improving the electrostatic discharge capability of the electrostatic discharge protection circuit.
The drift region 101 is of a first conductivity type, which is correspondingly N-type, that is, the doped ions in the drift region 101 are N-type ions, for example: p ions, as ions or Sb ions. In other embodiments, when the LDMOS transistor is a P-type transistor, the first conductivity type is correspondingly P-type, that is, the doped ions in the drift region are P-type ions, for example: b ions, ga ions, or In ions.
The esd protection structure includes an LDMOS transistor 110 located in each of the drift regions 101. The LDMOS transistor 110 is a high-voltage device, and the use number of the LDMOS transistor 110 is favorably reduced by adopting the LDMOS transistor 110, so that the chip area occupied by the electrostatic discharge protection structure is correspondingly favorably saved, and the utilization rate of the chip area is improved.
The gate structure 103 is used to control the turn-on and turn-off of the channel of the LDMOS transistor 110.
In this embodiment, since the LDMOS transistor 110 is a high voltage device, the gate structure 103 includes a gate dielectric layer (not shown) on the surface of the substrate 100 at the boundary between the body region 102 and the drift region 101 and a gate layer (not shown) on the gate dielectric layer.
In this embodiment, the gate structure 103 is a metal gate structure, the gate dielectric layer correspondingly includes a high-k gate dielectric layer (not shown), and the gate layer correspondingly is a gate electrode layer (not shown). In other embodiments, the gate structure may also be a polysilicon gate structure, the gate dielectric layer is a gate oxide layer, and the gate layer is made of polysilicon.
The gate structure 103 spans the interface surface of the drift region 101 and the body region 102, thereby enabling the drift region 101 to withstand a larger partial voltage.
The body region 102 acts as a lateral diffusion region to form a channel with a concentration gradient.
The body region 102 is of a second conductivity type. In this embodiment, the LDMOS transistor is an N-type transistor, and the second conductive type is a P-type transistor, that is, the doped ions In the body region 102 are P-type ions, such as B ions, ga ions, or In ions. In other embodiments, when the LDMOS transistor is a P-type transistor, the second conductivity type is correspondingly N-type, that is, the doped ions in the body region are N-type ions, for example: p ions, as ions or Sb ions.
In this embodiment, the body region 102 is located in the drift region 101, which is beneficial to simplifying the formation process of the LDMOS transistor 110. In other embodiments, the body region and the drift region may be located in different regions of the substrate and in contact with each other.
In this embodiment, the ion doping concentrations in the two drift regions 101 are the same, and the ion doping concentration in each body region 102 is the same, so that the uniformity of the leakage current of the electrostatic discharge protection structure can be further improved, and the symmetry and uniformity of the leakage current when the electrostatic discharge input end is positive voltage and negative voltage can be further improved.
The source region 104b is located in the body region 102 on one side of the gate structure 103, the drain region 104a is located in the drift region 101 on the other side of the gate structure 103, and the source region 104b and the drain region 104a are of the first conductivity type. In this embodiment, the LDMOS transistor is an N-type transistor, and the first conductivity type is an N-type correspondingly, so the doped ions of the source region 104b and the drain region 104a are N-type ions correspondingly. In other embodiments, when the LDMOS transistor is a P-type transistor, the doping ions of the source region and the drain region are P-type ions.
IN this embodiment, the source regions 104b of the LDMOS transistors 110 are all connected to each other, the drain region 104a IN one drift region 101 is connected to the electrostatic discharge input terminal IN, and the drain region 104a IN the other drift region 101 is connected to the ground terminal VSS.
When the chip protected by the electrostatic discharge protection structure works, the electrostatic discharge input end IN is connected to the signal line, and when the voltage of the signal line is positive voltage or negative voltage, the electrostatic discharge protection structure is not opened, so that the function of an internal circuit of the chip is prevented from being influenced. Specifically, when the chip works normally, the absolute value of the voltage of the signal line is smaller than the reverse conduction voltage of the parasitic diode formed by each drain region 104a and the corresponding body region 102, so that the electrostatic discharge protection structure cannot be turned on when the signal line is under positive voltage or negative voltage.
When the chip protected by the electrostatic discharge protection structure does not work, the electrostatic discharge protection structure is used for releasing electrostatic current, so that the chip is prevented from being damaged by electrostatic discharge. When the chip is not IN operation, the electrostatic discharge input terminal IN may contact with charged bodies such as human body and machine IN the processes of assembling, storing, transporting and the like, or the electrostatic discharge input terminal IN may be connected to a negative voltage or a positive voltage IN the electrostatic test, and thus, the electrostatic discharge input terminal IN may be a positive voltage or a negative voltage. Wherein positive voltage refers to a voltage greater than 0 volts and negative voltage refers to a voltage less than 0 volts.
It should be noted that the electrostatic signal is usually a high-frequency high-voltage signal, and the absolute value of the voltage of the electrostatic signal is greater than the reverse conducting voltage of the parasitic diode formed by each drain region 104a and the corresponding body region 102, so that the parasitic transistor formed by the drain region 104a and the corresponding body region 102 and the source region 104b is conducted, thereby discharging the electrostatic current.
By connecting the source regions 104b to each other, the drain regions 104a IN one drift region 101 are connected to an electrostatic discharge input terminal IN, and the drain region 104a IN the other drift region 101 is connected to a ground terminal VSS, so that the LDMOS transistors 110 IN the two drift regions 101 are connected back to back, when the electrostatic discharge input terminal IN is at a positive voltage and the voltage value of the electrostatic discharge input terminal IN is greater than the turn-on voltage of the parasitic transistor formed by the drain region 104a, the body region 102 and the source region 104b, the parasitic transistor formed by the drain region 104a, the body region 102 and the source region 104b is turned on IN the drift region 101 IN which the drain region 104a connected to the electrostatic discharge input terminal IN is located, so that the electrostatic current is conducted to the source region 104b and then to the other drift region 101 through a connection line, and since the body region 102 IN the LDMOS transistor 110 is connected to the source region 104b, the body region 102 has a high potential, the diode formed by the body region 102 and the drift region 101 is conducted IN a forward direction, so that the electrostatic current is conducted to the ground terminal VSS through the drain region 104 a.
Similarly, when the electrostatic discharge input terminal IN is at a negative voltage and the absolute value of the voltage of the electrostatic discharge input terminal IN is greater than the turn-on voltage of the parasitic transistor formed by the drain region 104a, the body region 102 and the source region 104b, the drain region 104a connected to the ground terminal VSS is equivalent to a high voltage, and IN the drift region 101 where the drain region 104a, the body region 102 and the source region 104b are located, the parasitic transistor formed by the drain region 104a, the body region 102 and the source region 104b is turned on to conduct the electrostatic current, and the body region 102 IN the other drift region 101 and the parasitic diode formed by the drift region 101 are conducted IN the forward direction to drain the electrostatic current.
In this embodiment, in each of the drift regions 101, the distance from each of the body regions 102 to the adjacent drain region 104a is equal, so that the electrical parameters of the parasitic transistor formed by each of the adjacent drain region 104a, the body region 102 and the source region 104b are close to or even the same, and the electrical parameters of the parasitic diode formed by each of the body regions 102 and the drift region 101 are close to or even the same. When the voltage of the electrostatic discharge input end IN is positive, the electrostatic discharge input end IN is correspondingly high IN potential; when the voltage of the electrostatic discharge input terminal IN is negative, the grounding terminal VSS is correspondingly high potential. When an electrostatic signal comes temporarily, each parasitic triode can be simultaneously turned on in the drift region 101 where the drain region 104a connected with a high potential is located, and each parasitic diode in the other drift region 101 can also be simultaneously turned on, so that the uniformity and stability of the leakage current of the electrostatic discharge protection structure can be improved.
In other embodiments, the distance from each body region to the adjacent drain region in each drift region may also be unequal.
It should be noted that, in this embodiment, a body contact region 105 is disposed in the source region 104b, the body contact region 105 contacts the body 102, the body contact region 105 is of the second conductivity type, and the body contact region 105 is connected to the source region 104 b. The body contact region 105 is used as a signal contact for the body region 102 to electrically connect the body region 102 to other circuitry. Therefore, in the present embodiment, the body region 102 is connected to the source region 104b through the body contact region 105.
Specifically, the conductivity types of the body region contact region 105 and the body region 102 are the same, and the ion doping concentration in the body region contact region 105 is greater than that of the body region 102, so that the contact resistance of the body region contact region 105 and a contact electrode formed on the surface of the body region contact region 105 is favorably reduced.
In this embodiment, the second conductive type is P-type, and the doped ions of the body contact region 105 are correspondingly P-type ions.
In this embodiment, the body contact region 105 is located in the source region 104b and contacts with the source region 104b, which is beneficial to simplifying the process flow of forming the esd protection structure.
It should be noted that, since the body contact region 105 and the source region 104b have different conductivity types, the depletion region formed therebetween may electrically isolate the body contact region 105 from the source region 104 b.
In this embodiment, the body region contact region 105 is located in the source region 104b, the source regions 104b are symmetric with respect to the body region contact region 105, and the source regions 104b on two sides of the body region contact region 105 are connected, so as to improve the layout symmetry and matching of the esd protection structure, and improve the uniformity of the esd protection structure for discharging the electrostatic current.
In other embodiments, the body region contact region may not be located in the source region, and an isolation structure may be formed between the body region contact region and the source region, so as to enhance the breakdown resistance between the body region contact region and the source region. In this case, the isolation structure can also increase the distance between the body region contact region and the source region, so as to increase the parasitic resistance between the body region contact region and the source region, and increase the potential difference generated between the body region contact region and the source region, so that the PN junction formed between the body region and the source region is easier to conduct in the forward direction, and thus the parasitic triode formed by the drain region, the body region and the source region is easier to conduct, and the electrostatic discharge capability of the electrostatic discharge protection structure is further improved.
It should be further noted that, in each of the LDMOS transistors 110, the gate structure 103 is isolated from the drain region 104 a; the electrostatic discharge protection structure further comprises: and an isolation layer 106, located on the substrate 100 between the gate structure 103 and the drain region 104a, wherein the isolation layer 106 further extends to a sidewall and a partial top of a side of the gate structure 103 close to the drain region 104 a.
The isolation layer 106 is used to isolate the gate structure 103 from the drain region 104a, so as to increase the resistance between the drain region 104a and the gate structure 103, and further increase the bias voltage that the drain region 104a can bear.
In this embodiment, the material of the isolation layer 106 is silicon oxide. In other embodiments, the material of the isolation layer may also be an insulating material such as silicon nitride, silicon oxynitride, or the like.
In this embodiment, the LDMOS transistor 110 is a common source-drain LDMOS transistor. In each drift region 101, the drain region 104a or the common source region 104b is shared by adjacent gate structures 103, the source regions 104b and the drain regions 104a are alternately distributed at intervals, and the gate structures 103 are correspondingly located on the substrate 100 between the adjacent source regions 104b and the adjacent drain regions 104a, so that the chip area occupied by the electrostatic discharge protection structure is further saved.
In addition, the shared source-drain LDMOS transistor is favorable for improving the layout symmetry and the matching property of the electrostatic discharge protection structure, and in addition, the shared source-drain LDMOS transistor comprises a plurality of source regions 104b and drain regions 104a, so that the electrostatic discharge path of the electrostatic discharge protection structure can be increased, the electrostatic discharge capacity of the electrostatic discharge protection structure can be improved, and meanwhile, the reliability and the stability of the electrostatic discharge protection structure can be improved.
In other embodiments, the LDMOS transistor may not be a common source-drain LDMOS transistor according to actual circuit requirements.
In this embodiment, the esd protection structure is a mirror-symmetric structure. Specifically, the LDMOS transistors 110 in two of the drift regions 101 constitute a mirror-symmetric structure.
Through making the electrostatic discharge protection structure is the mirror symmetry structure to further improved the overall arrangement symmetry and the matching of electrostatic discharge protection structure also are favorable to improving when electrostatic discharge input IN is positive pressure and negative pressure respectively symmetry and the homogeneity of bleeder current. In this embodiment, in each LDMOS transistor 110, a resistor R is connected between the gate structure 103 and the corresponding source region 104b, and a capacitor C is connected between the gate structure 103 and the corresponding drain region 104 a.
The resistor R and the capacitor C form a capacitance-resistance coupling, when an electrostatic signal comes, the capacitor C is turned on, so that a voltage is applied to the gate structure 103, the LDMOS transistor 110 is turned on, and a voltage required for turning on the channel of the LDMOS transistor 110 is lower than a mechanism for turning on an electrostatic current through a parasitic triode formed by the drain region 104, the body region 102 and the source region 104b, so that a turn-on voltage of the electrostatic discharge protection structure when an electrostatic voltage comes can be reduced, which is beneficial to improving a response speed of the electrostatic discharge protection structure to an electrostatic voltage and discharging an electrostatic current faster.
Moreover, when the absolute value of the voltage at the electrostatic discharge input terminal IN is greater than the turn-on voltage of the parasitic triode formed by the drain region 104, the body region 102 and the source region 104b, the electrostatic discharge protection structure can also conduct current through the parasitic triode, so that current can be conducted through the channel of the LDMOS transistor 110 and the dual mechanism of the parasitic triode, which is beneficial to further improving the electrostatic discharge capability of the electrostatic discharge protection structure.
It should be noted that the product of the resistance value of the resistor R and the capacitance value of the capacitor C is a time constant, specifically, the channel on time of the LDMOS transistor 110, and therefore, the product of the resistance value of the resistor R and the capacitance value of the capacitor C should not be too large. If the product of the resistance value of the resistor R and the capacitance value of the capacitor C is too large, the time for turning on the channel of the LDMOS transistor 110 is too long, so that the response speed of the electrostatic discharge protection structure to electrostatic signals is easily reduced. For this reason, in the present embodiment, the product of the resistance value of the resistor R and the capacitance value of the capacitor C is less than 2 μ s.
In this embodiment, the esd protection structure further includes: a guard ring structure (not shown), which includes a first well region 111 surrounding each of the drift regions 101, a second well region 112 surrounding the first well region 111, and a third well region 113 surrounding the second well region 112, wherein the first well region 111 and the third well region 113 are of the second conductivity type, and the second well region 112 is of the first conductivity type.
The guard ring structure is used for isolating noise, absorbing electrons and holes from the external environment or the drift region 101, and preventing voltage fluctuation, thereby realizing isolation of each drift region 101 from the external environment and avoiding influence of the other drift region 101 on the drift region 101, thereby being beneficial to preventing Latch up (Latch up), and further improving the stability and reliability of the electrostatic discharge protection structure.
Specifically, each of the first well region 111, the second well region 112, and the third well region 113 is provided therein with a well region contact region 114 (114a, 114b, 114c), and the well region contact region 114 has the same conductivity type as the corresponding well region, the well region contact region 114a in the first well region 111 and the well region contact region 114c in the third well region 113 are both connected to a ground terminal VSS, and the well region contact region 114b in the second well region 112 is connected to a power terminal VDD.
The ion doping concentration in the well region contact region 114 is greater than that in the corresponding well region, thereby being beneficial to reducing the contact resistance between the well region contact region 114 and the contact electrode formed on the surface thereof.
In this embodiment, the third well region 113 is shared between the two drift regions 101, so as to further save the chip area occupied by the esd protection structure.
In this embodiment, the substrate 100 is of the second conductivity type, and the esd protection structure further includes: a fourth well region 107 located in the substrate 100 at the bottom of the drift region 101, wherein the fourth well region 107 is of the first conductivity type, and an ion doping concentration in the fourth well region 107 is lower than that in the drift region 101.
The ion doping concentration in the fourth well region 107 is lower than that in the drift region 101, so that the reverse breakdown voltage of a parasitic diode formed by the drift region 101 and the substrate 100 is increased, and the substrate 100 and the drift region 101 are isolated.
Correspondingly, the invention also provides an electrostatic discharge protection circuit. Referring to fig. 4, a schematic circuit diagram of an esd protection circuit according to an embodiment of the invention is shown.
The electrostatic discharge protection circuit includes: a first LDMOS transistor M1; a second LDMOS transistor M2; in the first LDMOS transistor M1 and the second LDMOS transistor M2, the source electrodes are in short circuit with the substrate; the sources of the first LDMOS transistor M1 and the second LDMOS transistor M2 are connected with each other; the drains of the first LDMOS transistor M1 are connected to the electrostatic discharge input terminal IN, and the drains of the second LDMOS transistor M2 are connected to the ground terminal VSS.
In the esd protection circuit according to the embodiment of the present invention, the first LDMOS transistor M1 and the second LDMOS transistor M2 are connected back to back, that is, the source of the first LDMOS transistor M1 is connected to the source of the second LDMOS transistor M2, the drain of the first LDMOS transistor M1 is connected to the esd input terminal, and the drain of the second LDMOS transistor M2 is connected to the ground terminal.
Taking the first LDMOS transistor M1 and the second LDMOS transistor M2 as N-type transistors as an example, when the chip protected by the electrostatic discharge protection circuit operates, the electrostatic discharge input terminal IN is connected to a signal line, and when the voltage of the signal line is positive voltage, a parasitic diode formed by a drain connected to the signal line and a substrate is not reversely conducted, so that the electrostatic discharge protection circuit is not turned on; when the voltage of the signal line is negative voltage, a parasitic diode formed by the substrate and a drain electrode connected with the grounding terminal VSS cannot be conducted reversely, and the electrostatic discharge protection circuit cannot be started, so that the problem of current backflow in the electrostatic discharge protection circuit when the voltage of the signal line is negative voltage is avoided.
When the chip protected by the electrostatic discharge protection circuit does not work and the voltage of the electrostatic discharge input terminal IN is negative voltage, a parasitic triode formed by the drain electrode, the substrate and the source electrode IN the second LDMOS transistor M2 is turned on, so that electrostatic current is conducted into the substrate of the first LDMOS transistor M1 through the source electrode, and the substrate and the drain electrode IN the first LDMOS transistor M1 form a forward conducting diode, so that the electrostatic current is discharged; similarly, when the chip protected by the esd protection circuit does not operate and the voltage of the voltage at the esd input terminal IN is a positive voltage, the parasitic triode formed by the drain, the substrate and the source of the first LDMOS transistor M1 is turned on to conduct the electrostatic current into the substrate of the second LDMOS transistor M2 through the source, and the diode formed by the substrate and the drain of the second LDMOS transistor M2 is turned on IN the forward direction to drain the electrostatic current.
Moreover, the LDMOS transistor is a high-voltage device, and IN the case that the absolute value of the voltage at the electrostatic discharge input terminal IN is the same, compared with the scheme that the electrostatic discharge protection circuit discharges the electrostatic current through a diode or a MOS transistor, the LDMOS transistor with a smaller number is adopted to discharge the electrostatic current, which is beneficial to reducing the chip area occupied by the electrostatic discharge protection circuit and improving the area utilization rate of the chip.
In this embodiment, the first LDMOS transistor M1 and the second LDMOS transistor M2 are N-type transistors. The N-type transistor has higher carrier concentration, stronger conductive capability and smaller on-resistance, and is beneficial to improving the electrostatic discharge capability of the electrostatic discharge protection circuit. In other embodiments, the first and second LDMOS transistors may also be P-type transistors.
When the chip protected by the electrostatic discharge protection circuit works, the electrostatic discharge input end IN is connected to the signal line, and when the voltage of the signal line is positive voltage or negative voltage, the electrostatic discharge protection circuit is not started, so that the function of the internal circuit of the chip is prevented from being influenced. Specifically, when the chip works normally, the absolute value of the voltage of the signal line is smaller than the reverse conducting voltage of a parasitic diode formed by the drain and the substrate in each LDMOS transistor, so that the electrostatic discharge protection circuit cannot be started when the signal line is in positive voltage or negative voltage.
When the chip protected by the electrostatic discharge protection circuit does not work, the electrostatic discharge protection circuit is used for releasing electrostatic current, so that the chip is prevented from being damaged by electrostatic discharge. When the chip is not IN operation, the electrostatic discharge input terminal IN may contact with charged bodies such as human body and machine IN the processes of assembling, storing, transporting and the like, or the electrostatic discharge input terminal IN may be connected to a positive voltage or a negative voltage IN the electrostatic test, and thus, the electrostatic discharge input terminal IN may be a positive voltage or a negative voltage. Wherein positive voltage refers to a voltage greater than 0 volts and negative voltage refers to a voltage less than 0 volts.
It should be noted that the electrostatic signal is usually a high-frequency high-voltage signal, and the absolute value of the voltage of the electrostatic signal is greater than the reverse conducting voltage of the parasitic diode formed by each drain region 104a and the corresponding body region 102, so that the parasitic transistor formed by the drain region 104a and the corresponding body region 102 and the source region 104b is conducted, thereby discharging the electrostatic current.
By connecting the first LDMOS transistor M1 and the second LDMOS transistor M2 back to back, the electrostatic current at the electrostatic discharge input terminal IN is not only discharged at a positive voltage but also discharged at a negative voltage.
In this embodiment, the first LDMOS transistor M1 and the second LDMOS transistor M2 are both common source-drain transistors, which is favorable for improving the circuit layout symmetry and matching of the electrostatic discharge protection circuit, and can also increase the electrostatic discharge path of the electrostatic discharge protection circuit, thereby improving the electrostatic discharge capability of the electrostatic discharge protection circuit and improving the reliability and stability of the electrostatic discharge protection circuit.
In other embodiments, the first LDMOS transistor and the second LDMOS transistor may not be a common source-drain LDMOS transistor according to actual circuit requirements.
IN this embodiment, the esd protection circuit has mirror symmetry, so that the circuit layout symmetry and matching of the esd protection circuit are further improved, and the symmetry and uniformity of the leakage current when the esd input terminal IN is respectively a positive voltage and a negative voltage are also improved. Specifically, the first LDMOS transistor M1 and the second LDMOS transistor M2 constitute a mirror structure.
It should be noted that a protection ring structure (not shown) is further disposed around the first LDMOS transistor M1 and the second LDMOS transistor M2, and the protection ring structure surrounds the first LDMOS transistor M1 and the second LDMOS transistor M2, so as to isolate the first LDMOS transistor M1 and the second LDMOS transistor M2 from an external circuit, and the protection ring structure is further configured to isolate noise, absorb electrons and holes from an external environment, and prevent voltage fluctuation, thereby facilitating prevention of latch-up effect and improving stability and reliability of the electrostatic discharge protection circuit.
Specifically, the guard ring structure has a first well region (not shown) adjacent to the first LDMOS transistor M1 and the second LDMOS transistor M2 and surrounding the first LDMOS transistor M1 and the second LDMOS transistor M2, a second well region (not shown) surrounding the first well region, and a third well region (not shown) surrounding the second well region, the first well region and the third well region are connected to a power supply voltage VDD, and the second well region is connected to a ground terminal VSS. The power supply voltage VDD is also the power supply voltage of the chip protected by the esd protection circuit.
In this embodiment, the operating voltage of the first LDMOS transistor M1 and the second LDMOS transistor M2 is the same as the power supply voltage VDD, so that the first LDMOS transistor M1 and the second LDMOS transistor M2 can be applied to the chip.
In this embodiment, the first LDMOS transistor M1 and the second LDMOS transistor M2 have the same electrical parameters, such as threshold voltage, on-resistance, and the like, so as to further improve the electrostatic discharge uniformity of the electrostatic discharge protection circuit.
In this embodiment, in the first LDMOS transistor M1 and the second LDMOS transistor M2, a resistor R is connected between the gate and the corresponding source, and a capacitor C is connected between the gate and the corresponding drain.
The resistor R and the capacitor C form capacitance-resistance coupling, when an electrostatic signal comes, the capacitor C is conducted, so that voltage is applied to the grid electrode of the LDMOS transistor, the LDMOS transistor is started, current is conducted through a channel, and compared with a mechanism that the electrostatic current is conducted through a parasitic triode formed by a drain electrode, a substrate and a source electrode in the LDMOS transistor, the voltage required by starting the channel of the LDMOS transistor is lower, so that the response speed of the electrostatic discharge protection circuit to the electrostatic signal is improved, and the electrostatic current is discharged more quickly.
And, when the absolute value of electrostatic discharge input IN voltage is greater than during the parasitic triode turn-on voltage that drain electrode, substrate and source formed among the LDMOS transistor, electrostatic discharge protection circuit also can pass through parasitic triode turn-on current to can pass through the channel of LDMOS transistor and the dual mechanism turn-on current of parasitic triode is favorable to further improving electrostatic discharge protection circuit's electrostatic discharge ability.
It should be noted that a product of the resistance value of the resistor R and the capacitance value of the capacitor C is a time constant, specifically, the turn-on time of the LDMOS transistor channel, and therefore, the product of the resistance value of the resistor R and the capacitance value of the capacitor C should not be too large. If the product of the resistance value of the resistor R and the capacitance value of the capacitor C is too large, the time for turning on the channel of the LDMOS transistor 110 is too long, so that the response speed of the electrostatic discharge protection structure to electrostatic signals is easily reduced. For this reason, in the present embodiment, the product of the resistance value of the resistor R and the capacitance value of the capacitor C is less than 2 μ s.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. An electrostatic discharge protection structure, comprising:
the substrate is internally provided with two parallel and isolated drift regions;
the LDMOS transistor is positioned in each drift region and comprises a grid structure positioned on the substrate, a body region positioned in the drift region on one side of the grid structure, and a source region and a drain region which are respectively positioned on two sides of the grid structure, wherein the grid structure stretches across the boundary surfaces of the drift region and the body region, the source region is positioned in the body region, the drain region is positioned in the drift region, and the body region is connected with the source region;
the source regions in the two drift regions are connected with each other;
drain regions in one drift region are connected with the electrostatic discharge input end, and drain regions in the other drift region are connected with the grounding end;
the drift region, the source region and the drain region are of a first conductivity type, the body region is of a second conductivity type, and the first conductivity type is different from the second conductivity type;
in each LDMOS transistor, a resistor is connected between the grid structure and the corresponding source region, and a capacitor is connected between the grid structure and the corresponding drain region.
2. The esd-protection structure of claim 1, wherein a product of a resistance of the resistor and a capacitance of the capacitor is less than 2 μ β.
3. The esd-protection structure of claim 1, wherein the voltage at the esd input is positive or negative.
4. The esd-protection structure of claim 1, wherein the first conductivity type is N-type and the second conductivity type is P-type.
5. The esd-protection structure of claim 1, wherein the LDMOS transistor is a common source-drain LDMOS transistor.
6. The esd-protection structure of claim 1, wherein a body contact region is disposed in the source region, the body contact region contacting the body region, the body contact region being of the second conductivity type;
the body region contact region is connected with the source region.
7. The esd-protection structure of claim 1, wherein a distance from each body region to an adjacent drain region is equal in each drift region.
8. The esd-protection structure of claim 1, wherein the esd-protection structure is a mirror-symmetric structure.
9. The esd-protection structure of claim 1, wherein the ion doping concentration in both of the drift regions is the same, and the ion doping concentration in each body region is the same.
10. The esd-protection structure of claim 1, further comprising: and the guard ring structure comprises a first well region surrounding each drift region, a second well region surrounding the first well region and a third well region surrounding the second well region, wherein the first well region and the third well region are of a second conductivity type, and the second well region is of a first conductivity type.
11. The esd-protection structure of claim 10, wherein each of the first well region, the second well region, and the third well region has a well contact region therein, and the well contact region has the same conductivity type as the corresponding well region, the well contact region in each of the first well region and the third well region is connected to a ground terminal, and the well contact region in each of the second well regions is connected to a power source terminal.
12. The esd-protection structure of claim 10, wherein the third well region is shared between two drift regions.
13. The esd-protection structure of claim 1, wherein the substrate is of a second conductivity type;
the electrostatic discharge protection structure further comprises: and the fourth well region is positioned in the substrate at the bottom of the drift region, is of the first conduction type, and has the ion doping concentration lower than that in the drift region.
14. An electrostatic discharge protection circuit, comprising:
a first LDMOS transistor;
a second LDMOS transistor;
in the first LDMOS transistor and the second LDMOS transistor, the source electrodes are in short circuit with the substrate;
the source electrodes of the first LDMOS transistor and the second LDMOS transistor are connected with each other;
the drain electrodes of the first LDMOS transistors are connected with the electrostatic discharge input end, and the drain electrodes of the second LDMOS transistors are connected with the ground end;
in the first LDMOS transistor and the second LDMOS transistor, a resistor is connected between a gate and a corresponding source, and a capacitor is connected between the gate and a corresponding drain.
15. The esd protection circuit of claim 14, wherein a product of a resistance value of the resistor and a capacitance value of the capacitor is less than 2 μ β.
16. The esd protection circuit of claim 14, wherein the voltage at the esd input is positive or negative.
17. The electrostatic discharge protection circuit of claim 14, wherein the first LDMOS transistor and the second LDMOS transistor are N-type transistors.
18. The electrostatic discharge protection circuit of claim 17, wherein the first LDMOS transistor and the second LDMOS transistor are common source-drain transistors.
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104835816A (en) * | 2014-12-30 | 2015-08-12 | 香港应用科技研究院有限公司 | ESD protection circuit of silicon-on-insulator |
| CN104753055A (en) * | 2015-04-17 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge protection circuit |
| CN108878416A (en) * | 2018-06-28 | 2018-11-23 | 武汉新芯集成电路制造有限公司 | ESD protection circuit |
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| CN111415930A (en) | 2020-07-14 |
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