CN111414037B - LDO voltage stabilizing circuit - Google Patents
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Abstract
The invention discloses an LDO voltage stabilizing circuit, which comprises: the power supply circuit comprises a reference voltage terminal Vref, a first bias voltage terminal Vb1, a second bias voltage terminal Vb2, a third bias voltage terminal Vb3, an input voltage terminal VDD, an output voltage terminal Vout, a control circuit, a feedback circuit, a ground terminal GND and a power tube MP; the feedback circuit receives feedback of the output voltage end Vout and feeds a signal back to the control circuit, and the control circuit adjusts the power tube MP according to the feedback signal so as to stabilize the voltage of the output voltage end Vout. Through the circuit structure of the LDO voltage stabilizing circuit, a triple voltage stabilizing circuit form is formed, and the stability and the reliability of the whole LDO voltage stabilizing circuit are improved. The invention is mainly used for the technical field of integrated circuit power management.
Description
Technical Field
The invention relates to the technical field of integrated circuit power management, in particular to an LDO voltage stabilizing circuit.
Background
Low dropout linear LDOs are widely used in various wearable electronic devices to provide stable power supply voltages. With the increasing requirements of products on energy consumption and functional integration, how to effectively improve power management has become a difficult problem. The LDO circuit can provide ultra-low quiescent current to reduce power consumption, and is widely used in SoC chip design as an important power management module. The typical LDO circuit includes a reference voltage, an error amplifier EA, a power tube MP, and a feedback resistor. The LDO is one of important power management modules, and is widely applied to SoC chips. The existing LDO circuit has slow response to the output voltage change and can not output stable voltage.
Disclosure of Invention
The invention aims to provide an LDO voltage stabilizing circuit, which aims to solve the problem that the output of the existing low dropout regulator is unstable.
The solution of the invention for solving the technical problem is as follows: an LDO voltage regulator circuit, comprising: the power supply circuit comprises a reference voltage terminal Vref, a first bias voltage terminal Vb1, a second bias voltage terminal Vb2, a third bias voltage terminal Vb3, an input voltage terminal VDD, an output voltage terminal Vout, a control circuit, a feedback circuit, a ground terminal GND and a power tube MP;
the control circuit includes: a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, and an error amplifier EA, the feedback circuit including: a transistor M13 and a transistor M14;
the negative terminal of the error amplifier EA is connected to the reference voltage terminal Vref, the positive terminal of the error amplifier EA is connected to the gate of the transistor M8, the source of the transistor M13, and the drain of the transistor M14, the output terminal of the error amplifier EA is connected to the gate of the transistor M1, the gate of the transistor M4, the drain of the transistor M4, the drain of the transistor M3, the gate of the transistor M9, the drain of the transistor M9, the drain of the transistor M10, and the gate of the power transistor MP, the drain of the transistor M1 is connected to the gate of the transistor M2, the drain of the transistor M2, the gate of the transistor M5, and the gate of the transistor M7, the drain of the transistor M5 is connected to the source of the transistor M4, the drain of the transistor M7 is connected to the drain of the transistor M6, and the source of the transistor M7 is connected to the gate of the transistor M10 and the drain of the transistor M8, the source of the transistor M10 is connected to the drain of the transistor M11 and the drain of the transistor M12 respectively, the source of the transistor M11 is connected to the drain of the power transistor MP, the drain of the transistor M13, the gate of the transistor M13, the gate of the transistor M14 and the output voltage terminal Vout, the gate of the transistor M3 is respectively connected with the first bias voltage terminal Vb1, the gate of the transistor M6 and the gate of the transistor M9, the gate of the transistor M11 is connected to the second bias voltage terminal Vb2, the gate of the transistor M12 is connected to the third bias voltage terminal Vb3, the source of the transistor M2, the source of the transistor M5, the source of the transistor M8, the source of the transistor M12, and the source of the transistor M14 are connected to a ground GND, the source of the transistor M1, the source of the transistor M3, the source of the transistor M6, the source of the transistor M9, and the source of the power transistor MP are connected to the input voltage terminal VDD, respectively.
Further, the transistor M1, the transistor M3, the transistor M6, the transistor M9, and the transistor M11 are all PMOS transistors, and the transistor M2, the transistor M4, the transistor M5, the transistor M8, the transistor M10, the transistor M12, the transistor M13, and the transistor M14 are all NMOS transistors.
Further, the power transistor MP is a PMOS transistor.
Further, this LDO voltage stabilizing circuit still includes load circuit, load circuit includes: the load circuit comprises a load capacitor CL and a load resistor RL, wherein the upper ends of the load resistor RL and the load capacitor CL are connected with an output voltage end Vout, and the lower ends of the load resistor RL and the load capacitor CL are connected with a ground end GND.
The invention has the beneficial effects that: through the circuit structure of the LDO voltage stabilizing circuit, a triple voltage stabilizing circuit form is formed, and the stability and the reliability of the whole LDO voltage stabilizing circuit are improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the described drawings are only a part of the embodiments of the invention, not all embodiments, and that a person skilled in the art will be able to derive other designs and drawings from these drawings without the exercise of inventive effort.
FIG. 1 is a schematic diagram of a circuit configuration of an LDO voltage regulator circuit;
FIG. 2 is a graph showing the relationship between V and VoutWhen the voltage rises, the change condition of a control loop of the LDO voltage stabilizing circuit is changed;
FIG. 3 is a graph showing the relationship between V and VoutAnd when the voltage is reduced, the change condition of a control loop of the LDO voltage stabilizing circuit is reduced.
Detailed Description
Reference will now be made in detail to the present preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
In the description of the present invention, it should be understood that the orientation or positional relationship referred to in the description of the orientation, such as up, down, front, rear, left, right, etc., is the orientation or positional relationship shown in the drawings, and is only for convenience of description and simplification of the description of the present invention, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention.
In the description of the invention, if words such as "a number" or the like are used, the meaning is one or more, the meaning of a plurality is two or more, more than, less than, more than, etc. are understood as not including the number, and more than, less than, more than, etc. are understood as including the number.
In the description of the present invention, unless otherwise explicitly defined, terms such as setup, installation, connection, and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the terms in the present invention in combination with the detailed contents of the technical solutions.
Embodiment 1, referring to fig. 1, an LDO voltage regulator circuit includes: the power transistor comprises a reference voltage terminal Vref, a first bias voltage terminal Vb1, a second bias voltage terminal Vb2, a third bias voltage terminal Vb3, an input voltage terminal VDD, an output voltage terminal Vout, a control circuit 100, a feedback circuit 200, a ground terminal GND, a power transistor MP and a load circuit 300.
The control circuit 100 includes: a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, and an error amplifier EA, the feedback circuit 200 including: a transistor M13 and a transistor M14;
the negative terminal of the error amplifier EA is connected to the reference voltage terminal Vref, the positive terminal of the error amplifier EA is connected to the gate of the transistor M8, the source of the transistor M13, and the drain of the transistor M14, the output terminal of the error amplifier EA is connected to the gate of the transistor M1, the gate of the transistor M4, the drain of the transistor M4, the drain of the transistor M3, the gate of the transistor M9, the drain of the transistor M9, the drain of the transistor M10, and the gate of the power transistor MP, the drain of the transistor M1 is connected to the gate of the transistor M2, the drain of the transistor M2, the gate of the transistor M5, and the gate of the transistor M7, the drain of the transistor M5 is connected to the source of the transistor M4, the drain of the transistor M7 is connected to the drain of the transistor M6, and the source of the transistor M7 is connected to the gate of the transistor M10 and the drain of the transistor M8, the source of the transistor M10 is connected to the drain of the transistor M11 and the drain of the transistor M12 respectively, the source of the transistor M11 is connected to the drain of the power transistor MP, the drain of the transistor M13, the gate of the transistor M13, the gate of the transistor M14 and the output voltage terminal Vout, the gate of the transistor M3 is respectively connected with the first bias voltage terminal Vb1, the gate of the transistor M6 and the gate of the transistor M9, the gate of the transistor M11 is connected to the second bias voltage terminal Vb2, the gate of the transistor M12 is connected to the third bias voltage terminal Vb3, the source of the transistor M2, the source of the transistor M5, the source of the transistor M8, the source of the transistor M12, and the source of the transistor M14 are connected to a ground GND, the source of the transistor M1, the source of the transistor M3, the source of the transistor M6, the source of the transistor M9, and the source of the power transistor MP are connected to the input voltage terminal VDD, respectively. The transistor M1, the transistor M3, the transistor M6, the transistor M9 and the transistor M11 are all PMOS transistors, and the transistor M2, the transistor M4, the transistor M5, the transistor M8, the transistor M10, the transistor M12, the transistor M13, the transistor M14 and the power transistor MP are all NMOS transistors.
The load circuit 300 includes: the load circuit comprises a load capacitor CL and a load resistor RL, wherein the upper ends of the load resistor RL and the load capacitor CL are connected with an output voltage end Vout, and the lower ends of the load resistor RL and the load capacitor CL are connected with a ground end GND.
The working principle of the LDO voltage stabilizing circuit is as follows:
referring to fig. 2, the control circuit 100, when operating, can be divided into three control loops, respectively: a first control loop 110, a second control loop 120, and a third control loop 130. Wherein the first control loop 110 comprises: a transistor M11, a transistor M12, a transistor M10, a transistor M9 and a power transistor MP.
The second control loop 120 includes: a transistor M1, a transistor M2, a transistor M7, a transistor M8, a transistor M10, and an error amplifier EA.
The third control loop 130 includes: transistor M5, transistor M2, and transistor M4.
Referring to fig. 2, when the output voltage of the output voltage terminal Vout increases, the source voltage of the transistor M11 increases, the current flowing through the transistor M11 increases, the current flowing through the transistor M12 remains unchanged, the current flowing through the transistor M10 decreases, the current flowing through the transistor M9 remains unchanged, the voltage at the point C is pulled up, the gate voltage of the power transistor MP increases, the current flowing through the power transistor MP decreases, and the output voltage of the output voltage terminal Vout is pulled down and restored to the normal state.
When the voltage at point a also increases, the voltage across the positive terminal of the error amplifier EA increases, the output voltage of the error amplifier EA increases, the gate voltage of the transistor M1 increases, the current flowing through the transistor M1 decreases, the transistor M2 is diode-connected, the current flowing through the transistor M2 decreases, the current flowing through the transistor M7 decreases, the gate voltage of the transistor M8 increases, the current flowing through the transistor M8 increases, the voltage at point B is pulled down, the current flowing through the transistor M10 decreases faster, the voltage at point C increases faster, that is, the gate voltage of the power transistor MP increases faster, the current flowing through the power transistor MP decreases, and the output voltage at the output voltage terminal Vout is pulled down and restored to a normal state.
The current flowing through the transistor M5 decreases as the current of the transistor M2 decreases, and the transistor M4 is diode-connected, so that the drain voltage of the transistor M4 is pulled high, the gate voltage of the power transistor MP increases more quickly, and the output voltage of the output voltage terminal Vout recovers more quickly.
In a state where the output voltage of the output voltage terminal Vout rises:
the first control loop 110 pulls down the output voltage of the output voltage terminal Vout and makes it return to a normal state by reducing the current of the power transistor MP. The current of the transistor M9 is kept unchanged, the voltage of the point C is pulled high, the grid voltage of the power tube MP is increased, the current flowing through the power tube MP is reduced, the output voltage of the output voltage end Vout is pulled low, the output voltage is recovered to a normal state, and the purpose of stabilizing the output voltage of the output voltage end Vout is achieved.
The second control loop 120 pulls down the voltage at the point B, so that the current flowing through the transistor M10 decreases faster, the voltage at the point C increases faster, that is, the gate voltage of the power transistor MP increases faster, and the current flowing through the power transistor MP decreases, thereby pulling down the output voltage of the output voltage terminal Vout, restoring the output voltage to a normal state, and achieving the purpose of stabilizing the output voltage of the output voltage terminal Vout.
The third control loop 130 increases the gate voltage of the power transistor MP faster by pulling up the drain voltage of the transistor M4, so that the output voltage of the output voltage terminal Vout recovers faster, thereby achieving the purpose of stabilizing the output voltage of the output voltage terminal Vout.
Referring to fig. 3, when the output voltage of the output voltage terminal Vout decreases, the source voltage of the transistor M11 decreases, the current flowing through the transistor M11 decreases, the current flowing through the transistor M12 remains unchanged, the current flowing through the transistor M10 increases, the current flowing through the transistor M9 remains unchanged, the voltage at the point C is pulled down, the gate voltage of the power transistor MP decreases, the current flowing through the power transistor MP increases, and the output voltage of the output voltage terminal Vout is pulled up and restored to the normal state;
when the voltage at the point a is also decreased, the voltage across the positive terminal of the error amplifier EA is decreased, the output voltage of the error amplifier EA is decreased, the gate voltage of the transistor M1 is increased, the current flowing through the transistor M1 is increased, the transistor M2 is connected in a diode form, the current flowing through the transistor M2 is increased, the current flowing through the transistor M7 is increased, the gate voltage of the transistor M8 is decreased, the current flowing through the transistor M8 is decreased, the voltage at the point B is pulled up, the current flowing through the transistor M10 is increased more quickly, the voltage at the point C is decreased more quickly, that is, the gate voltage of the power transistor MP is decreased more quickly, the current flowing through the power transistor MP is increased, and the output voltage Vout at the output voltage terminal Vout is pulled up and restored to a normal state;
the current flowing through the transistor M5 increases as the current of the transistor M2 increases, and the transistor M4 is connected in a diode manner, so that the drain voltage of the transistor M4 is pulled down, the gate voltage of the power tube MP drops more quickly, and the output voltage of the output voltage terminal Vout recovers more quickly.
In a state where the output voltage of the output voltage terminal Vout is lowered:
the first control loop 110 pulls down the voltage at the point C, so that the gate voltage of the power tube MP is decreased, and the current flowing through the power tube MP is increased, thereby pulling up the output voltage of the output voltage terminal Vout, restoring the output voltage to a normal state, and achieving the purpose of stabilizing the output voltage of the output voltage terminal Vout.
The second control loop 120 pulls up the output voltage of the output voltage terminal Vout by pulling up the voltage at the point B, so that the current flowing through the transistor M10 increases more quickly, and the voltage at the point C decreases more quickly, i.e., the gate voltage of the power transistor MP decreases more quickly, so that the current flowing through the power transistor MP increases, thereby achieving the purpose of stabilizing the output voltage of the output voltage terminal Vout.
The third control loop 130 pulls down the drain voltage of the transistor M4, so that the gate voltage of the power transistor MP drops faster, the output voltage of the output voltage terminal Vout recovers faster, and the purpose of stabilizing the output voltage of the output voltage terminal Vout is achieved.
By the circuit structure of the LDO voltage regulator circuit, a first control loop 110, a second control loop 120, and a third control loop 130 are formed in the control circuit 100, and the three control loops affect each other. The circuit form of triple voltage stabilization is formed, and the stability and the reliability of the whole LDO voltage stabilizing circuit are improved.
It is found that the third control loop 130 has a faster response speed than the second control loop 120, and the second control loop 120 has a faster response speed than the first control loop 110. And the integral transient response speed is higher than that of the conventional LDO voltage stabilizing circuit. Therefore, the LDO voltage stabilizing circuit of this application also has the high beneficial effect of transient response speed with current LDO voltage stabilizing circuit contrast.
The working principle of the LDO voltage stabilizing circuit provided by the invention is quantitatively analyzed as follows:
description of the symbols: vfbVoltage, V, indicated as point ADVoltage shown as point D, VDD is voltage of input voltage terminal VDD, VBExpressed as the point B voltage, VGSPDenoted as the gate-source voltage, K, of the power transistor MPPExpressed as transistor parameter, Δ V, of the power transistor MPDVoltage change quantity, Δ I, represented as point DiExpressed as the amount of current change, Δ V, flowing through the ith transistorDSiExpressed as the amount of change, V, in the drain-source voltage of the ith transistorDSiDenoted as drain-source voltage, Δ V, of the ith transistoroutExpressed as a voltage variation of the voltage of the output voltage terminal Vout, λ is a channel length modulation coefficient, Δ VoutExpressed as a voltage variation, V, of the output voltage terminal Voutb3Indicated as the voltage, V, of the third bias voltage terminal Vb3outExpressed as the voltage, μ, of the output voltage terminal VoutpIs the mobility of electrons, CoxIs the gate capacitance per unit area. W is the conduction channel width, L is the conduction channel length, VGSiExpressed as the gate-source voltage, Δ I, of the ith transistoriExpressed as the amount of current change, V, flowing through the ith transistorTHExpressed as the threshold voltage of the transistor, IiExpressed as the current through the ith transistor, (W/L)iDenoted as transistor parameter of the ith transistor, KiDenoted as transistor parameter of the ith transistor, Ki＝μpCox(W/L)iThe subscript i denotes the reference number of the transistor, for example: when i is 4, the corresponding transistor is the transistor M4, and when i is P, the corresponding transistor is the power transistor MP.
As can be seen from FIGS. 1 to 3, the voltage V at point AfbIs dependent on the output voltage VoutSynchronously changing. The transistor M13 is diode connected and therefore in the saturation region, and the transistor M14 is in the triode region.
I13＝I14 (3)，
The combined type (1) and (3) can obtain:
VGS14＝Vout (5)，
VDS14＝Vfb (6)，
VGS13＝Vout-Vfb (7)，
from the formulae (2), (4), (5), (6) and (7)
Derived from formula (8)
As can be seen from the formula (9), the voltage V at the point AfbThe derivative with the output voltage is greater than zero and therefore in a directly proportional relationship. The voltage at point a increases with increasing output.
Setting PMOS current to flow from source to drain as positive direction, VDVoltage at point D, Δ VDVoltage change amount of point D, VGS1The gate-source voltage of the transistor M1, the current flowing through the transistor M1 is:
VGS1＝VDD-VD (11)，
let the voltage variation at point D be DeltaVDThen, the formula (10) or (11) can be used to obtain
Δ V when the voltage at D point increasesDIs positive, when decreasing Δ VDIs negative. From the formula (12), it can be seen that I is increased when the voltage at the D point is increased1Decrease, when D point voltage decreases I1And is increased. The transistor M2 is diode-connected, so the current flowing through the transistor M2 follows the current I flowing through the transistor M11Decrease and decrease with I1And increases with an increase.
The transistor M5 and the transistor M2 form a current mirror structure, and then the current flowing through the transistor M5:
it can be seen that the current flowing through transistor M5 is directly proportional to the current flowing through transistor M1, the current flowing through transistor M5 is a function of the current I flowing through transistor M11Decrease and decrease with I1And increases with an increase. The transistor M4 is diode-connected, so the current I flowing through the transistor M44And I5When the gate-source voltage of the transistor M3 is equal to the gate-source voltage of the transistor M3, the current I flows through the transistor M33Remains unchanged, I4Reduce and rapidly raise the grid voltage, I of the power tube MP4And increasing and rapidly reducing the grid voltage of the power tube MP to achieve the purpose of adjusting the grid voltage of the power tube MP to rapidly rise and fall.
From the equation (12), the current I flowing through the transistor M22As the voltage at point D increases and decreases, the transistor M7 and the transistor M2 form a current mirror structure, and then:
from the equation (14), the current I flowing through the transistor M77With I2And decreased.
The current flowing through transistor M8 is:
VGS8＝Vfb (16)，
can be obtained by combining the vertical type (15) and the vertical type (16)
The current I flowing through the transistor M8 can be obtained from equation (17)8The current I increases as the voltage at point A increases8Increase of I7When the voltage at the point B decreases, the gate voltage of the transistor M10 decreases, and the current flowing through the transistor M10 decreases.
The output voltage terminal Vout is connected to the source of the transistor M11, and the output voltage V is known in consideration of the channel modulation effectoutAnd the current I flowing through the PMOS tube11The relationship is:
VDS11＝Vout-VDS12 (19)，
wherein Ki＝μpCox(W/L)i＝1,2…
In the PMOS transistor current expression, the negative sign inside does not represent magnitude, but represents direction, equation (18) represents that the current direction is from drain to source, where the current direction is specified as from source to drain, and the PMOS transistor source-drain current expression is obtained considering the channel modulation effect:
voltage V of output voltage terminal VoutoutChange is made, and the change amount is set as DeltaVoutDrain-source voltage of transistor M11 and voltage VoutThe variation of (c) is as follows:
ΔVDS11＝ΔVout-VDS12 (21)，
the total current flowing through the transistor M12 is constant, so when the current flowing through the transistor M11 changes, the current flowing through the transistor M10 changes accordingly, namely:
ΔI11＝-ΔI10 (22)，
from the equations (20), (21) and (22), the current flowing through the transistor M15 and VoutHas the following relationship
From the formula (23), Δ VoutWhen negative, Δ I10Is positive, i.e. VoutWhen decreasing, the current through transistor M10 increases, VoutWhen increasing, the current flowing through transistor M10 decreases.
Since the current flowing through the transistor M9 remains unchanged, the current flowing through the transistor M10 decreases, which pulls up the voltage at point C, i.e., the gate voltage of the power transistor MP increases, and the current flowing through the power transistor MP is:
the gate voltage of the power transistor MP is increased, the gate source voltage is decreased, and the formula (24) shows that the current flowing through the power transistor MP is decreased, so that V is increasedoutPulling down to restore the normal state.
In conclusion, when V isoutWhen the voltage rises, the voltage at the point a rises, the voltage at the point D at the output terminal rises by the error amplifier EA, the current flowing through the transistor M1 decreases as shown by the equation (12), the current flowing through the transistor M5 decreases as shown by the equation (13), the transistor M4 is diode-connected, the current flowing through the transistor M5 is equal to the current flowing through the transistor M3526, the gate voltage of the power transistor MP is pulled up, and the current flowing through the power transistor MP decreases as shown by the equation (24), and V is pulled downoutRecovering to a normal state; when the voltage at point a increases and the gate voltage of the transistor M8 increases, the current flowing through the transistor M8 increases as shown by equation (17), and when the current flowing through the transistor M7 decreases as shown by equation (14), the voltage at point B is pulled down and the current flowing through the transistor M10 decreases as shown by equation (2)3) It is known that the current flowing through the transistor M11 increases, the current flowing through the transistor M10 decreases faster, the voltage at the point C is pulled high, i.e., the gate voltage of the power transistor MP increases, and equation (24) shows that the current flowing through the power transistor MP decreases, and the voltage V is pulled lowoutAnd the normal state is recovered.
VoutWhen the voltage at the point a decreases, as can be seen from the equation (9), the voltage at the point D at the output terminal decreases by the error amplifier EA, and as can be seen from the equation (12), the current flowing through the transistor M1 increases, and as can be seen from the equation (13), the current flowing through the transistor M5 increases, and the transistor M4 is diode-connected, and the current flowing through the transistor M5 is equal to the current flowing through the transistor M5, the gate voltage of the power transistor MP is pulled down, and as can be seen from the equation (24), the current flowing through the power transistor MP increases, and the output V is pulled upoutRecovering to a normal state; the voltage at point a decreases, the gate voltage of the transistor M8 decreases, as shown in equation (17), the current flowing through the transistor M8 decreases, as shown in equation (14), the current flowing through the transistor M7 increases, the voltage at point B is pulled up, and the current flowing through the transistor M10 increases, as shown in equation (23), the current flowing through the transistor M11 decreases, the current flowing through the transistor M10 increases more rapidly, the voltage at point C is pulled down, i.e., the gate voltage of the power transistor MP decreases, as shown in equation (24), the current flowing through the power transistor MP increases, and the voltage V is pulled upoutAnd the normal state is recovered.
Current flowing through transistor M12:
the transistor M6 and the transistor M9 form a current mirror structure, and then:
the process sets the current flowing through transistor M10 to be half the current flowing through transistor M12, then:
the output V can be obtained by the united vertical type (8), (25), (26) and (27)outRelational expression with bias voltage:
to sum up, the LDO voltage stabilizing circuit of this application, it is fast to output voltage's change reaction rate to obtain stable supply voltage output.
While the preferred embodiments of the present invention have been described in detail, it will be understood by those skilled in the art that the invention is not limited to the details of the embodiments shown, but is capable of various modifications and substitutions without departing from the spirit of the invention.
Claims (4)
1. An LDO voltage regulator circuit, comprising: the power supply circuit comprises a reference voltage terminal Vref, a first bias voltage terminal Vb1, a second bias voltage terminal Vb2, a third bias voltage terminal Vb3, an input voltage terminal VDD, an output voltage terminal Vout, a control circuit, a feedback circuit, a ground terminal GND and a power tube MP;
the control circuit includes: a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, and an error amplifier EA, the feedback circuit including: a transistor M13 and a transistor M14;
the negative terminal of the error amplifier EA is connected to the reference voltage terminal Vref, the positive terminal of the error amplifier EA is connected to the gate of the transistor M8, the source of the transistor M13, and the drain of the transistor M14, the output terminal of the error amplifier EA is connected to the gate of the transistor M1, the gate of the transistor M4, the drain of the transistor M4, the drain of the transistor M3, the gate of the transistor M9, the drain of the transistor M9, the drain of the transistor M10, and the gate of the power transistor MP, the drain of the transistor M1 is connected to the gate of the transistor M2, the drain of the transistor M2, the gate of the transistor M5, and the gate of the transistor M7, the drain of the transistor M5 is connected to the source of the transistor M4, the drain of the transistor M7 is connected to the drain of the transistor M6, and the source of the transistor M7 is connected to the gate of the transistor M10 and the drain of the transistor M8, the source of the transistor M10 is connected to the drain of the transistor M11 and the drain of the transistor M12 respectively, the source of the transistor M11 is connected to the drain of the power transistor MP, the drain of the transistor M13, the gate of the transistor M13, the gate of the transistor M14 and the output voltage terminal Vout, the gate of the transistor M3 is respectively connected with the first bias voltage terminal Vb1, the gate of the transistor M6 and the gate of the transistor M9, the gate of the transistor M11 is connected to the second bias voltage terminal Vb2, the gate of the transistor M12 is connected to the third bias voltage terminal Vb3, the source of the transistor M2, the source of the transistor M5, the source of the transistor M8, the source of the transistor M12, and the source of the transistor M14 are connected to a ground GND, the source of the transistor M1, the source of the transistor M3, the source of the transistor M6, the source of the transistor M9, and the source of the power transistor MP are connected to the input voltage terminal VDD, respectively.
2. The LDO voltage regulator circuit of claim 1, wherein: the transistor M1, the transistor M3, the transistor M6, the transistor M9 and the transistor M11 are all PMOS tubes, and the transistor M2, the transistor M4, the transistor M5, the transistor M8, the transistor M10, the transistor M12, the transistor M13 and the transistor M14 are all NMOS tubes.
3. The LDO voltage regulator circuit of claim 1, wherein: the power tube MP is a PMOS tube.
4. The LDO voltage regulator circuit of claim 1, further comprising a load circuit, the load circuit comprising: the load circuit comprises a load capacitor CL and a load resistor RL, wherein the upper ends of the load resistor RL and the load capacitor CL are connected with an output voltage end Vout, and the lower ends of the load resistor RL and the load capacitor CL are connected with a ground end GND.
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| CN202010162004.5A CN111414037B (en) | 2020-03-10 | 2020-03-10 | LDO voltage stabilizing circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE10119858A1 (en) * | 2001-04-24 | 2002-11-21 | Infineon Technologies Ag | voltage regulators |
| CN1825240A (en) * | 2006-03-24 | 2006-08-30 | 启攀微电子（上海）有限公司 | Low voltage difference linear voltage stabilizer circuit |
| TW201005466A (en) * | 2008-07-24 | 2010-02-01 | Advanced Analog Technology Inc | Low dropout regulator |
| CN102298407A (en) * | 2010-06-28 | 2011-12-28 | 中国人民解放军国防科学技术大学 | Low-output voltage and fast response low-dropout regulator (LDO) circuit based on current control loop |
| CN107291144B (en) * | 2017-05-23 | 2019-02-12 | 上海集成电路研发中心有限公司 | It is a kind of with transient state enhancing structure unit without capacitor LDO circuit outside piece |
| CN107544605B (en) * | 2017-10-16 | 2023-11-28 | 佛山科学技术学院 | Digital-analog hybrid multi-loop substrate dynamic bias LDO circuit |
| CN107783588B (en) * | 2017-11-10 | 2023-11-28 | 佛山科学技术学院 | Push-pull type quick response LDO circuit |
| CN108874008B (en) * | 2018-06-22 | 2021-04-27 | 佛山科学技术学院 | LDO circuit with double feedback |
| CN109739293B (en) * | 2019-01-25 | 2020-12-15 | 湖南文理学院 | Substrate bias-based FVF dual-loop LDO circuit |
| CN109917847A (en) * | 2019-03-26 | 2019-06-21 | 佛山市顺德区德雅军民融合创新研究院 | Voltage stabilizing circuit and voltage stabilizing chip |
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