CN111403405B

CN111403405B - 3D NAND storage structure and preparation method thereof

Info

Publication number: CN111403405B
Application number: CN202010156682.0A
Authority: CN
Inventors: 孙中旺; 吴林春; 张坤; 王迪; 周文犀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-03-09
Filing date: 2020-03-09
Publication date: 2021-08-13
Anticipated expiration: 2040-03-09
Also published as: CN111403405A

Abstract

The invention provides a 3D NAND storage structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a semiconductor intermediate structure, said semiconductor intermediate structure comprising: the semiconductor device comprises a semiconductor substrate, a laminated structure formed on the semiconductor substrate and a front grid gap formed in the laminated structure; wherein the front gate gap penetrates through the stacked structure and extends to the semiconductor substrate; forming an initial common source line on the inner wall of the front gate gap to fill the front gate gap; forming a back gate gap on a surface of the semiconductor substrate away from the front gate gap opening, wherein the back gate gap exposes the bottom of the initial common source line; and forming a common source line on the inner wall of the back gate gap to fill the back gate gap. The invention solves the problem of storage area loss caused by larger characteristic size when the front side grid gap is formed on the front side of the wafer.

Description

3D NAND storage structure and preparation method thereof

Technical Field

The invention belongs to the technical field of integrated circuit design and manufacture, and particularly relates to a 3D NAND storage structure and a preparation method thereof.

Background

In recent years, Flash memories (Flash memories) have been developed rapidly, and have been widely used in various fields such as microcomputers and automation control, because they have the main characteristics of retaining stored information for a long time without power-on, and have the advantages of high integration, fast access speed, easy erasing and rewriting, etc. In order to further improve the Bit Density (Bit Density) of the flash memory and simultaneously reduce the Bit Cost (Bit Cost), the three-dimensional flash memory (3D NAND) technology has been rapidly developed.

With the increase of the number of layers of the 3D NAND memory, the process challenge of a Gate Line Slit (GLS) is larger and larger; in the traditional method, a grid gap is formed on the front surface of a wafer, and then the grid gap is filled to lead out a common source line; however, this method has the following problems: in order to ensure the extraction of the common source line, a larger characteristic size is required when a gate gap is formed, so that a certain storage area is lost.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a 3D NAND memory structure and a method for fabricating the same, which are used to solve the problem of a certain loss of memory area due to a large feature size when a gate gap is formed on the front surface of a wafer in the conventional method.

To achieve the above and other related objects, the present invention provides a method for fabricating a 3D NAND memory structure, the method comprising:

providing a semiconductor intermediate structure, said semiconductor intermediate structure comprising: the semiconductor device comprises a semiconductor substrate, a laminated structure formed on the semiconductor substrate and a front grid gap formed in the laminated structure; wherein the front gate gap penetrates through the stacked structure and extends to the semiconductor substrate;

forming an initial common source line on the inner wall of the front gate gap to fill the front gate gap;

forming a back gate gap on a surface of the semiconductor substrate away from the front gate gap opening, wherein the back gate gap exposes the bottom of the initial common source line;

and forming a common source line on the inner wall of the back gate gap to fill the back gate gap.

Optionally, after the initial common source line is formed on the inner wall of the front-side gate gap, the preparation method further includes: and etching back the initial common source line to form a back etching hole, and filling an isolation material in the back etching hole to form a top isolation layer.

Optionally, the isolation material is a material with high stress resistance, and includes: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina.

Optionally, the method of forming the back gate gap on a surface of the semiconductor substrate away from the front gate gap opening includes: and etching a surface of the semiconductor substrate, which is far away from the front side gate gap opening, by taking the initial common source line as an etching stop layer so as to form the back side gate gap in the semiconductor substrate.

Optionally, before forming the initial common source line on the inner wall of the front-side gate gap, the preparation method further includes: forming an initial adhesion layer on the inner wall of the front gate gap, wherein the initial common line is formed on the inner wall of the initial adhesion layer;

before forming the common source line on the inner wall of the back gate gap, the preparation method further comprises: and forming an adhesion layer on the inner wall of the back gate gap, wherein the common source line is formed on the inner wall of the adhesion layer.

Optionally, before forming the initial common source line on the inner wall of the front-side gate gap, the preparation method further includes: forming an initial isolation layer on the side wall of the front side grid electrode gap;

before forming the common source line on the inner wall of the back gate gap, the preparation method further comprises: and forming an isolation layer on the side wall of the back gate gap.

Optionally, the method for forming the initial isolation layer on the sidewall of the front-side gate gap includes: and forming an initial isolation material layer on the inner wall of the front gate gap, and then removing the initial isolation material layer formed at the bottom of the front gate gap so as to form the initial isolation layer on the side wall of the front gate gap.

The method for forming the isolation layer on the side wall of the back gate gap comprises the following steps: and forming an isolation material layer on the inner wall of the back gate gap, and then removing the isolation material layer formed at the bottom of the back gate gap to form the isolation layer on the side wall of the back gate gap.

Optionally, the semiconductor intermediate structure further comprises: the semiconductor device comprises a semiconductor substrate, a laminated structure and a channel structure, wherein the semiconductor substrate is provided with a plurality of gate layers and dielectric layers, the semiconductor substrate is provided with a plurality of stacked layers, the stacked layers are arranged on the semiconductor substrate, the channel structure is formed between the semiconductor substrate and the laminated structure and comprises gate layers and dielectric layers which are stacked alternately, and the channel structure penetrates through the laminated structure and extends to the semiconductor substrate; the channel structure comprises a channel through hole formed in the laminated structure, and a functional side wall, a channel layer and a filling insulating layer which are sequentially formed on the inner wall of the channel through hole, wherein part of the channel layer is in contact with the conducting layer through a communication channel penetrating through the functional side wall, and the semiconductor intermediate structure further comprises: and an insulating layer formed between the conductive layer and the stacked structure and between the communication channel and the gate layer.

Optionally, the preparation method of the semiconductor intermediate structure comprises the following steps:

providing a semiconductor substrate, and sequentially forming a substrate protection layer, a support layer, a laminated protection layer and an initial laminated structure on the semiconductor substrate, wherein the initial laminated structure comprises sacrificial layers and dielectric layers which are alternately laminated;

forming a channel through hole in the initial laminated structure, and sequentially forming a functional side wall, a channel layer and a filling insulating layer on the inner wall of the channel through hole to fill the channel through hole, wherein the channel through hole penetrates through the initial laminated structure and extends to the semiconductor substrate;

forming an initial gate gap in the initial stacked structure, and forming a sidewall protection layer on a sidewall of the initial gate gap, wherein the initial gate gap penetrates through the initial stacked structure and extends to the support layer;

removing the support layer based on the initial gate gap to form a support gap;

removing at least a portion of the functional sidewall within the support gap based on the support gap to expose the channel layer and removing the stack protection layer, the substrate protection layer, and the sidewall protection layer;

forming a conductive layer on the semiconductor substrate in the support gap while forming a communication channel at the exposed channel layer to contact the conductive layer with the channel layer through the communication channel;

etching the conductive layer and the semiconductor substrate based on the initial gate gap to form a front side gate gap;

forming an insulating layer on the conductive layer in the support gap and the surface of the communication channel;

and removing the sacrificial layer based on the front-side gate gap to form a sacrificial gap, and forming a gate layer in the sacrificial gap and the support gap.

Optionally, after the front-side gate gap is formed, the method for manufacturing the semiconductor intermediate structure further includes: forming a source region in the semiconductor substrate at the bottom of the front side gate gap and in the conductive layer at the sidewall of the front side gate gap; in this case, the semiconductor intermediate structure further includes: a source region formed in the semiconductor substrate and the conductive layer at the bottom of the front side gate gap.

Optionally, the method for forming the functional sidewall on the inner wall of the trench via includes: and forming a blocking layer on the inner wall of the channel through hole, then forming a storage layer on the inner wall of the blocking layer, and finally forming a tunneling layer on the inner wall of the storage layer.

Optionally, the method of forming the sidewall protection layer on the sidewall of the initial gate gap includes: and forming a side wall protection material layer on the inner wall of the initial grid gap, and then removing the side wall protection material layer formed at the bottom of the initial grid gap so as to form the side wall protection layer on the side wall of the initial grid gap.

Optionally, the channel layer includes a polysilicon layer, an epitaxial growth process is adopted to form an epitaxial silicon layer on the semiconductor substrate in the supporting gap as the conductive layer, an epitaxial polysilicon layer is formed at the exposed channel layer as the communication channel, and in-situ moisture is adopted to generate silicon oxide as the insulating layer.

The present invention also provides a 3D NAND memory structure, comprising:

a semiconductor intermediate structure, the semiconductor intermediate structure comprising: the semiconductor device comprises a semiconductor substrate, a laminated structure formed on the semiconductor substrate and a front side gate gap formed in the laminated structure, wherein the front side gate gap penetrates through the laminated structure and extends to the semiconductor substrate;

an initial common source line formed in the front gate gap;

a back gate gap formed in the semiconductor substrate, wherein the back gate gap exposes a bottom of the initial common source line;

and the common source line is formed in the back gate gap.

Optionally, the storage structure further comprises:

etching back the hole to form above the reserved initial common source line;

and the top isolating layer is formed in the back etching hole.

Optionally, the top isolation layer is a material layer with high stress resistance, and includes: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina.

Optionally, the storage structure further comprises:

the initial adhesion layer is formed on the inner wall of the front gate gap, and the initial common source line is formed on the inner wall of the initial adhesion layer;

and the adhesion layer is formed on the inner wall of the back gate gap, and the common source line is formed on the inner wall of the adhesion layer.

Optionally, the storage structure further comprises:

the initial isolation layer is formed on the side wall of the front grid electrode gap;

and the isolation layer is formed on the side wall of the back grid gap.

Optionally, the semiconductor intermediate structure further comprises: a source region formed in the semiconductor substrate and the conductive layer at the bottom of the front side gate gap.

Optionally, the functional sidewall comprises:

the barrier layer is formed on the inner wall of the channel through hole;

the storage layer is formed on the inner wall of the barrier layer;

and the tunneling layer is formed on the inner wall of the storage layer.

Optionally, the channel layer comprises a polysilicon layer, the conductive layer comprises an epitaxial silicon layer, the communication channel comprises an epitaxial polysilicon layer, and the insulating layer comprises a silicon oxide layer.

As described above, the 3D NAND memory structure and the method for manufacturing the same of the present invention have the following advantages:

according to the invention, the back grid gap is formed on the back surface of the semiconductor substrate and the common source line is led out from the back grid gap, so that the common source line is prevented from being led out from the front surface of the semiconductor substrate, the characteristic size of the front grid gap formed on the front surface of the semiconductor substrate is effectively reduced, the area of the front grid gap of the semiconductor substrate is reduced, and the storage area of the 3D NAND storage structure is increased by nearly 1%; meanwhile, the common source line is led out from the back surface of the semiconductor substrate, so that the positions of the common source line and the channel structure of the 3D NAND memory structure are staggered, and the parasitic capacitance between the common source line and the channel structure is effectively reduced.

According to the invention, the initial common source line formed on the front surface of the semiconductor substrate is etched back, and the top insulating layer is filled in the etching-back hole, so that the anti-stress capability of the 3D NAND memory structure is improved by utilizing the high anti-stress performance of the top insulating layer, meanwhile, the insulating performance between the word line and the common source line in the 3D NAND memory structure is improved by utilizing the etching-back initial common source line and the filling of the top insulating layer, and the electric leakage risk between the word line and the common source line in the 3D NAND memory structure is reduced.

Drawings

Fig. 1 is a flowchart illustrating a method for fabricating a 3D NAND memory structure according to an embodiment of the invention.

Fig. 2 is a schematic structural diagram of a substrate protection layer, a support layer, a stack protection layer and an initial stack structure sequentially formed on a semiconductor substrate according to a first embodiment of the invention.

Fig. 3 is a schematic structural diagram illustrating the formation of a trench via according to an embodiment of the invention.

Fig. 4 is a schematic structural diagram illustrating a functional sidewall, a channel layer and a filling insulation layer sequentially formed in a trench via according to a first embodiment of the invention.

Fig. 5 is a schematic structural diagram illustrating the formation of an initial gate gap according to one embodiment of the present invention.

Fig. 6 is a schematic structural diagram illustrating the formation of a sidewall protection material layer according to an embodiment of the invention.

Fig. 7 is a schematic structural diagram illustrating the formation of a sidewall protection layer according to an embodiment of the invention.

Fig. 8 is a schematic structural diagram illustrating the formation of a supporting gap according to an embodiment of the invention.

Fig. 9 is a schematic structural diagram illustrating a method of removing a portion of the functional sidewall to expose the channel layer and removing the stacked protection layer, the substrate protection layer, and the sidewall protection layer according to an embodiment of the invention.

Fig. 10 is a schematic structural diagram illustrating the formation of a conductive layer, a communication channel, and a front gate gap according to an embodiment of the invention.

Fig. 11 is a schematic structural diagram illustrating the formation of a source region according to an embodiment of the invention.

Fig. 12 is a schematic structural diagram illustrating the formation of an insulating layer according to an embodiment of the invention.

Fig. 13 is a schematic structural diagram illustrating the formation of a sacrificial gap according to an embodiment of the invention.

Fig. 14 is a schematic structural diagram illustrating a stacked structure according to an embodiment of the invention.

Fig. 15 is a schematic structural diagram illustrating the formation of an initial isolation material layer according to an embodiment of the invention.

FIG. 16 is a schematic diagram illustrating a structure of an initial isolation layer according to an embodiment of the invention.

FIG. 17 is a schematic view of a structure for forming an initial adhesion layer and an initial common source line according to an embodiment of the invention. FIG. 18 is a schematic diagram illustrating a structure of forming a back etching hole according to an embodiment of the invention.

Fig. 19 is a schematic structural diagram illustrating the formation of a top insulating layer according to a first embodiment of the invention.

Fig. 20 is a schematic structural diagram illustrating formation of a back gate gap according to an embodiment of the invention.

Fig. 21 is a schematic structural diagram illustrating the formation of a spacer material layer according to an embodiment of the invention.

Fig. 22 is a schematic structural diagram illustrating the formation of an isolation layer according to an embodiment of the invention.

FIG. 23 is a schematic diagram illustrating the formation of an adhesion layer and a common source line in accordance with one embodiment of the present invention.

Description of the element reference numerals

10 semiconductor intermediate structure

101 semiconductor substrate

102 protective layer of substrate

103 support layer

104 laminated protective layer

105 initial lamination

105a, 116a dielectric layer

105b sacrificial layer

106 channel structure

106a channel via

106b functional side wall

106b1 barrier layer

106b2 storage layer

106b3 tunneling layer

106c channel layer

106d filling the insulating layer

107 initial gate gap

108' layer of sidewall protective material

108 sidewall protection layer

109 support gap

110 conductive layer

111 communicating channel

112 front side gate gap

113 source region

114 insulating layer

115 sacrificial gap

116 laminated structure

116b Gate layer

11' initial layer of isolating Material

11 initial isolation layer

12 initial adhesion layer

13 initial common source line

14 etch back hole

15 top isolation layer

16 back side gate gap

17' layer of isolating material

17 isolating layer

18 adhesion layer

19 common source line

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 23. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.

Example one

As shown in fig. 1, the present embodiment provides a method for manufacturing a 3D NAND memory structure, the method including:

s1: providing a semiconductor intermediate structure 10, said semiconductor intermediate structure 10 comprising: a semiconductor substrate 101, a stacked structure 116 formed on the semiconductor substrate 101, and a front gate gap 112 formed in the stacked structure 116; wherein the front gate gap 112 penetrates through the stacked structure 116 and extends to the semiconductor substrate 101;

s2: forming an initial common source line 13 on the inner wall of the front gate gap 112 to fill the front gate gap 112;

s3: forming a back gate gap 16 on a surface of the semiconductor substrate 101 away from the front gate gap 112 opening, wherein the back gate gap 16 exposes the bottom of the initial common source line 13;

s4: a common source line 19 is formed on the inner wall of the back gate gap 16 to fill the back gate gap 16.

Referring to fig. 1, a method for manufacturing the 3D NAND memory structure according to the present embodiment is described in detail with reference to fig. 2 to 23.

In step S1, as shown in fig. 14, a semiconductor intermediate structure 10 is provided, the semiconductor intermediate structure 10 including: a semiconductor substrate 101, a stacked structure 116 formed on the semiconductor substrate 101, and a front gate gap 112 formed in the stacked structure 116; wherein the front gate gap 112 penetrates through the stacked structure 116 and extends to the semiconductor substrate 101.

As an example, as shown in fig. 14, the semiconductor intermediate structure 10 according to the present example further includes: a conductive layer 110 formed between the semiconductor substrate 101 and the stacked structure 116, and a channel structure 106 formed in the stacked structure 116, wherein the stacked structure 116 includes gate layers 116b and dielectric layers 116a stacked alternately, and the channel structure 106 penetrates through the stacked structure 116 and extends to the semiconductor substrate 101; the channel structure 106 includes a channel via 106a formed in the stacked-layer structure 116, a functional sidewall 106b formed on an inner wall of the channel via 106a, a channel layer 106c, and a filling insulation layer 106d, wherein a portion of the channel layer 106c is in contact with the conductive layer 110 through a communication channel 111 penetrating through the functional sidewall 106b, and in this case, the semiconductor intermediate structure 10 further includes: and an insulating layer 114 formed between the conductive layer 110 and the stacked-layer structure 116 and between the communication channel 111 and the gate layer 116 b.

Specifically, the method for manufacturing the semiconductor intermediate structure 10 includes:

s10: as shown in fig. 2, a semiconductor substrate 101 is provided, and a substrate protection layer 102, a support layer 103, a stack protection layer 104 and an initial stack structure 105 are sequentially formed on the semiconductor substrate 101, wherein the initial stack structure 105 includes a sacrificial layer 105b and a dielectric layer 105a which are alternately stacked;

s11: as shown in fig. 3 and 4, a trench via 106a is formed in the initial stacked structure 105, and a functional sidewall 106b, a channel layer 106c and a filling insulation layer 106d are sequentially formed on an inner wall of the trench via 106a to fill the trench via 106a, wherein the trench via 106a penetrates through the initial stacked structure 105 and extends to the semiconductor substrate 101;

s12: as shown in fig. 5 to 7, an initial gate gap 107 is formed in the initial stacked structure 105, and a sidewall protection layer 108 is formed on a sidewall of the initial gate gap 107, wherein the initial gate gap 107 penetrates through the initial stacked structure 105 and extends to the support layer 103;

s13: as shown in fig. 8, removing the support layer 103 based on the initial gate gap 107 to form a support gap 109;

s14: as shown in fig. 9, removing at least a portion of the functional sidewall 106b located within the support gap 109 based on the support gap 109 to expose the channel layer 106c, and removing the stack protection layer 104, the substrate protection layer 102, and the sidewall protection layer 108;

s15: as shown in fig. 10, a conductive layer 110 is formed on the semiconductor substrate 101 in the support gap 109, and a communication channel 111 is formed at the exposed channel layer 106c, so that the conductive layer 110 is in contact with the channel layer 106c through the communication channel 111;

s16: as shown in fig. 10, the conductive layer 110 and the semiconductor substrate 101 are etched based on the initial gate gap 107 to form a front gate gap 112;

s17: as shown in fig. 12, an insulating layer 114 is formed on the surfaces of the conductive layer 110 and the communication channel 111 in the support gap 112;

s18: as shown in fig. 13 and 14, the sacrificial layer 105a is removed based on the front side gate gap 112 to form a sacrificial gap 115, and a gate layer 116b is formed in the sacrificial gap 115 and the support gap 109.

In step S10, the semiconductor substrate 101 may be selected according to actual requirements of devices, and the semiconductor substrate 101 may include a silicon substrate, a germanium substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like; preferably, in this example, the semiconductor substrate 101 is a silicon substrate.

In step S10, the material of the support layer 103 may include silicon oxide, silicon nitride, polysilicon, or the like; preferably, in this example, the material of the support layer 103 is polysilicon. The material of the substrate protection layer 102 may include silicon oxide, and the material of the stack protection layer 104 may include silicon nitride.

In step S10, the initial stacked structure 105 includes the dielectric layers 105a and the sacrificial layers 105b stacked alternately in sequence from bottom to top, where the bottom layer of the initial stacked structure 105 is the dielectric layer 105a, and the top layer of the initial stacked structure 105 is also the dielectric layer 105 a; the dielectric layer 105a may be made of silicon nitride or hafnium nitride, and the sacrificial layer 105b may be made of any material having a higher etching selectivity than the dielectric layer 105a, such as polysilicon, carbon, or an organic thin film.

In step S11, the method for forming the trench via 106a in the initial stacked structure 105 includes:

s11-1: forming a patterned mask layer (not shown) on the upper surface of the initial stacked structure 105, wherein an opening pattern defining the shape and position of the trench via 106a is formed in the patterned mask layer;

s11-2: sequentially etching the initial laminated structure 105, the laminated protective layer 104, the support layer 103, the substrate protective layer 102 and the semiconductor substrate 101 based on the patterned mask layer to form the channel through hole 106a penetrating through the initial laminated structure 105 and extending to the semiconductor substrate 101;

s11-3: and removing the graphical mask layer.

Wherein, the channel through hole 106a is formed by adopting a dry etching process or a wet etching process; preferably, in this example, the trench via 106a is formed using a dry etching process. It should be noted that the number and distribution of the trench vias 106a may be set according to the actual requirement of the device structure to be formed, and is not limited herein.

In step S11, the method for forming the functional sidewall 106b on the inner wall of the trench via 106a includes: a blocking layer 106b1 is formed on the inner wall of the trench via 106a, a memory layer 106b2 is formed on the inner wall of the blocking layer 106b1, and a tunneling layer 106b3 is formed on the inner wall of the memory layer 106b 2.

Forming the barrier layer 106b1 on the inner wall of the channel through hole 106a by using a chemical vapor deposition process or a high-temperature furnace tube growth process; preferably, in this example, the barrier layer 106b1 is formed using a high temperature furnace growth process. The barrier layer 106b1 may include an oxide layer, wherein the material of the oxide layer may include silicon oxide, hafnium oxide, or the like.

Forming the memory layer 106b2 on the inner wall of the barrier layer 106b1 by using a chemical vapor deposition process or a high temperature furnace tube growth process; preferably, in this example, the memory layer 106b2 is formed using a high temperature furnace growth process. The memory layer 106b2 may include a nitride layer, wherein the material of the nitride layer may include silicon nitride or hafnium nitride, etc.

Forming the tunneling layer 106b3 on the inner wall of the memory layer 106b2 by using a chemical vapor deposition process or a high temperature furnace tube growth process; preferably, in this example, the tunneling layer 106b3 is formed using a high temperature furnace growth process. The tunneling layer 104b3 may include an oxide layer, wherein the material of the oxide layer may include silicon oxide or hafnium oxide, etc.

In step S11, forming the channel layer 106c on the inner wall surface of the functional sidewall 106b by using a chemical vapor deposition process or a high temperature furnace tube growth process; preferably, in this example, the channel layer 106c is formed by a high temperature furnace tube growth process, wherein the material of the channel layer 106c includes polysilicon.

In step S11, forming the filling insulation layer 106d on the inner wall surface of the channel layer 106c by using a chemical vapor deposition process or a high temperature furnace tube growth process to fill the channel via hole 106 a; preferably, in this example, the filling insulation layer 106d is formed by a high temperature furnace growth process, wherein the material of the filling insulation layer 106d may include an oxide dielectric layer, such as silicon oxide.

In step S12, the method for forming the initial gate gap 107 in the initial stacked structure 105 includes:

s12-1: forming a patterned mask layer (not shown) on the upper surface of the initial stacked structure 105, wherein an opening pattern defining the shape and position of the initial gate gap 107 is formed in the patterned mask layer;

s12-2: sequentially etching the initial laminated structure 105, the laminated protective layer 104, the support layer 103, the substrate protective layer 102 and the semiconductor substrate 101 based on the patterned mask layer to form the initial gate gap 107 which penetrates through the initial laminated structure 105 and extends to the support layer 103;

s12-3: and removing the graphical mask layer.

Wherein, the initial gate gap 107 is formed by a dry etching process or a wet etching process; preferably, in this example, the initial gate gap 107 is formed using a dry etch process. It should be noted that the position and the number of the initial gate gaps 107 can be set according to actual needs, and are not limited herein.

Since the 3D NAND memory structure in this example is to form the back gate gap 16 on the back surface of the semiconductor substrate 101 and to lead out the common source line 19 in the back gate gap 16, when the initial gate gap 107 is formed on the front surface of the semiconductor substrate 101, the size (i.e., the characteristic size) of the corresponding opening pattern in the patterned mask layer may be appropriately reduced to reduce the size of the finally formed front gate gap 112, so as to reduce the area occupied by the front gate gap 112 as a whole, that is, the area occupied by the array common source is reduced as a whole, and further, the storage area of the 3D NAND memory structure is increased by approximately 1%. Moreover, in the present example, the common source line 19 is led out from the back surface of the semiconductor substrate 101, so that the positions of the common source line and the channel structure of the 3D NAND memory structure are staggered, and the parasitic capacitance between the two is effectively reduced.

In step S12, the method for forming the sidewall protection layer 108 on the sidewall of the initial gate gap 107 includes: as shown in fig. 6, a sidewall protection material layer 18 'is formed on the inner wall of the initial gate gap 107, and then, as shown in fig. 7, the sidewall protection material layer 108' formed at the bottom of the initial gate gap 107 is removed to form the sidewall protection layer 108 on the sidewall of the initial gate gap 107.

Forming a side wall protection material layer 18' on the inner wall of the initial gate gap 107 by adopting a chemical vapor deposition process or a high-temperature furnace tube growth process; preferably, in this example, the sidewall protection material layer 18' is formed using a chemical vapor deposition process. The sidewall protection material layer 18' may include nitride layers and oxide layers alternately stacked, wherein the material of the nitride layers may include silicon nitride or hafnium nitride, etc., and the material of the oxide layers may include silicon oxide or hafnium oxide, etc. It should be noted that the number of the alternately stacked nitride layers and oxide layers may be set according to actual needs, and a layer far from the edge of the initial gate gap 107 may be a nitride layer or an oxide layer, which is not limited herein.

In step S13, removing the support layer 103 by using a wet etching process; specifically, wet etching is performed by using a wet etching solution which has a high etching removal rate for the support layer 103 and hardly removes the substrate protection layer 102, the stack protection layer 103, and the sidewall protection layer 108, so as to remove the support layer 103. In a specific implementation, the wet etching solution may be disposed in the initial gate gap 107, and the wet etching solution laterally etches the support layer 103 to remove the support layer 103.

In step S14, a wet etching process is used to remove at least a portion of the functional sidewall 106b located in the support gap 109; specifically, wet etching is performed by using a wet etching solution having a high etching removal rate for the functional sidewall 106b, so as to remove at least a portion of the functional sidewall 106b located in the support gap 109. In a specific implementation, the wet etching solution may be disposed in the supporting gap 109, and the wet etching solution laterally etches the functional sidewall 106b to remove at least a portion of the functional sidewall 106b located in the supporting gap 109. In this example, since the functional sidewall 106b has a stacked structure including the blocking layer 106b1, the memory layer 106b2, and the tunneling layer 106b3, the blocking layer 106b1, the tunneling layer 106b3, and the substrate protection layer 102 are all oxide layers, the memory layer 106b2 and the stacked protection layer 104 are all nitride layers, and the sidewall protection layer 108 is a nitride layer and an oxide layer stacked alternately, the substrate protection layer 102, the stacked protection layer 104, and a portion of the sidewall protection layer 108 can be removed simultaneously when a wet etching process is used to remove a portion of the functional sidewall 106 b.

In step S15, an epitaxial growth process is used to form an epitaxial silicon layer as the conductive layer 110 on the semiconductor substrate 101 in the supporting gap 109, and simultaneously an epitaxial polysilicon layer is used as the communication channel 111 at the exposed channel layer 106 c. It should be noted that when an epitaxial growth process is used to form an epitaxial silicon layer on the semiconductor substrate 101 in the supporting gap 109, the exposed polysilicon channel layer will simultaneously grow polysilicon, so as to form a communication channel 111 penetrating through the functional sidewall 106b to contact the epitaxial silicon layer.

In step S16, the conductive layer 110 and the semiconductor substrate 101 are etched by a dry etching process based on the initial gate gap 107 to form the front gate gap 112.

In step S17, in-situ water vapor generated silicon oxide is used as the insulating layer 114 on the surfaces of the conductive layer 110 and the communication channel 111 in the supporting gap 112.

In step S18, removing the sacrificial layer 105a by using a wet etching process; specifically, wet etching is performed by using a wet etching solution which has a high etching removal rate for the sacrificial layer 105a and hardly removes the dielectric layer 105b, so as to remove the sacrificial layer 105 a. In a specific implementation, the wet etching solution may be disposed in the front-side gate gap 112, and the wet etching solution laterally etches the sacrificial layer 105a to remove the sacrificial layer 105 a.

In step S18, forming the gate layer 116b in the sacrificial gap 115 by using a chemical vapor deposition process or a high temperature furnace growth process; preferably, in this example, the gate layer 116b is formed using a chemical vapor deposition process; wherein the material of the gate layer 116b may include metal tungsten.

Specifically, as shown in fig. 11, after the front-side gate gap 112 is formed, the method for manufacturing the semiconductor intermediate structure 10 further includes: a step of forming a source region 113 in the semiconductor substrate 101 at the bottom of the front side gate gap 112 and in the conductive layer 110 at the sidewall of the front side gate gap 112; in this case, the semiconductor intermediate structure 10 further includes: a source region 113 formed in the semiconductor substrate 101 and the conductive layer 110 at the bottom of the front side gate gap 112. It is noted that when the semiconductor intermediate structure 10 includes the source region 113, the insulating layer 114 is simultaneously formed on the surface of the source region 113.

An ion implantation process is performed on the semiconductor substrate 101 at the bottom of the front gate gap 112 and the conductive layer 110 on the sidewall of the front gate gap 112 to perform N-type ion implantation, so as to form the source region 113.

In step S2, as shown in fig. 17, an initial common line 13 is formed on the inner wall of the front gate gap 112 to fill the front gate gap 112. It is noted that, when the semiconductor intermediate structure 10 further includes the source region 113, the initial common source line 13 is in contact with the source region 113.

As an example, as shown in fig. 17, the initial common source line 13 is formed on the inner wall of the front gate gap 112 by using a chemical vapor deposition process or a high temperature furnace growth process; preferably, in this example, the initial common source line 13 is formed using a chemical vapor deposition process; wherein the material of the initial common source line 13 may include metal tungsten.

As an example, as shown in fig. 17, before forming the initial common source line 13 on the inner wall of the front gate gap 112, the preparation method further includes: and forming an initial adhesion layer 12 on the inner wall of the front gate gap 112, wherein the initial common line 13 is formed on the inner wall of the initial adhesion layer 12. Specifically, the initial adhesion layer 12 may include a titanium layer and a titanium nitride layer.

As an example, as shown in fig. 16, before the initial common source line 13 is formed on the inner wall of the front gate gap 112, the preparation method further includes: and forming an initial isolation layer 11 on the sidewall of the front gate gap 112. It should be noted that, when the initial adhesion layer 12 is further formed on the inner wall of the front gate gap 112, the initial adhesion layer 12 is formed on the inner wall of the initial isolation layer 11 and the bottom of the front gate gap 112.

Specifically, the method for forming the initial isolation layer 11 on the sidewall of the front gate gap 112 includes: as shown in fig. 15, an initial isolation material layer 11 'is formed on the inner wall of the front gate gap 112, and then as shown in fig. 16, the initial isolation material layer 11' formed at the bottom of the front gate gap 112 is removed to form the initial isolation layer 11 on the sidewall of the front gate gap 112. Wherein, the material of the initial isolation layer 11 may be silicon oxide. It is noted that when the insulating layer 114 is formed on the upper surface of the source region 113, the initial isolation material layer 11' formed at the bottom of the front gate gap 112 is removed, and simultaneously, the insulating layer 114 at the corresponding position is removed to expose the source region 113, as shown in fig. 16.

Between the step S2 and the step S3, a step S2-3 is further included: after the initial common source line 13 is formed on the inner wall of the front gate gap 112, the preparation method further includes: as shown in fig. 18, the initial common source line 13 is etched back to form an etch-back hole 14; as shown in fig. 19, the etch back holes 14 are filled with an isolation material to form a top isolation layer 15.

As an example, the initial common source line 13 is etched back by a dry etching process to form the etch-back hole 14. When the initial common source line 13 is etched back by using a dry etching process, in order to improve the stress resistance of the 3D NAND memory structure as much as possible, the more the initial common source line 13 is etched, the better the initial common source line 13 is, but based on that the retained initial common source line 13 is also required to be used as an etching stop layer for forming a back gate gap 16 later, it is required to ensure that the height of the retained initial common source line 13 is greater than 1nm, where the height of the retained initial common source line 13 is the thickness of the retained initial common source line 13 along the depth direction of the front gate gap 112. It should be noted that, when the initial isolation layer 11 and/or the initial adhesion layer 12 are formed between the front gate gap 112 and the initial common source line 13, the initial isolation layer 11 and/or the initial adhesion layer 12 are removed at the same time when the back etching is performed by using the dry etching process.

As an example, a chemical vapor deposition process or a high temperature furnace growth process is used to fill the back etching holes 14 with an isolation material to form the top isolation layer 15; specifically, the isolation material is a material with high stress resistance, and comprises: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina. Preferably, in this example, the top isolation layer 15 is formed using a chemical vapor deposition process, wherein the material of the top isolation layer 15 comprises silicon oxide. It should be noted that, in practical applications, the stress resistance of the generated silicon oxide can be adjusted by adjusting the pressure, deposition rate and temperature of the chemical vapor deposition process, so as to obtain silicon oxide with high stress resistance as the top insulating layer 15, thereby improving the stress resistance of the 3D NAND memory structure in this example, and meanwhile, the insulating property between the word line and the common source line in the 3D NAND memory structure can be improved by using the etched-back initial common source line and the top insulating layer to fill, and the risk of leakage between the word line and the common source line in the 3D NAND memory structure is reduced.

In step S3, as shown in fig. 20, a back gate gap 16 is formed on a surface of the semiconductor substrate 101 away from the front gate gap 112 opening, wherein the back gate gap 16 exposes the bottom of the initial common source line 13.

As an example, the method of forming the back gate gap 16 on a surface of the semiconductor substrate 101 away from the front gate gap 112 opening includes: and etching a surface of the semiconductor substrate 101 away from the opening of the front gate gap 112 by using the initial common source line 13 as an etching stop layer, so as to form the back gate gap 16 in the semiconductor substrate 101.

Specifically, the method for forming the back gate gap 16 includes:

s31: forming a patterned mask layer (not shown) on a surface of the semiconductor substrate 101 away from the front-side gate gap 112 opening, wherein an opening pattern defining the shape and position of the back-side gate gap 16 is formed in the patterned mask layer;

s32: etching the semiconductor substrate 101 based on the patterned mask layer, and taking the reserved initial common source line 13 as an etching stop layer until the bottom of the initial common source line 13 is exposed to form a back gate gap 16;

s33: and removing the graphical mask layer.

Wherein, the back gate gap 16 is formed by a dry etching process or a wet etching process; preferably, in this example, the back gate gap 16 is formed using a dry etch process. It should be noted that the positions and the number of the back gate gaps 16 correspond to the positions and the number of the front gate gaps 112 one to one.

In step S4, as shown in fig. 23, a common source line 19 is formed on the inner wall of the back gate gap 16 to fill the back gate gap 16.

As an example, as shown in fig. 23, the common source line 19 is formed on the inner wall of the back gate gap 16 by using a chemical vapor deposition process or a high temperature furnace growth process; preferably, in the present example, the common source line 19 is formed using a chemical vapor deposition process; wherein the material of the common source line 19 may include metallic tungsten.

As an example, as shown in fig. 23, before forming the common source line 19 on the inner wall of the back gate gap 16, the preparation method further includes: and forming an adhesion layer 18 on the inner wall of the back gate gap 16, wherein the common source line 19 is formed on the inner wall of the adhesion layer 18. Specifically, the adhesion layer 18 may include a titanium layer and a titanium nitride layer.

As an example, as shown in fig. 22, before forming the common source line 19 on the inner wall of the back gate gap 16, the preparation method further includes: and forming an isolation layer 17 on the sidewall of the back gate gap 16. Note that, when the adhesion layer 18 is further formed on the inner wall of the back gate gap 16, the adhesion layer 18 is formed on the inner wall of the isolation layer 17 and the bottom of the back gate gap 16.

Specifically, the method for forming the isolation layer 17 on the sidewall of the back gate gap 16 includes: as shown in fig. 21, an isolation material layer 17 'is formed on the inner wall of the back gate gap 16, and then as shown in fig. 22, the isolation material layer 17' formed at the bottom of the back gate gap 16 is removed to form the isolation layer 17 on the sidewall of the back gate gap 16. Wherein the material of the isolation layer 17 may include silicon oxide.

Example two

As shown in fig. 23, the present embodiment provides a 3D NAND memory structure, which includes:

a semiconductor intermediate structure 10, said semiconductor intermediate structure 10 comprising: the semiconductor device comprises a semiconductor substrate 101, a laminated structure 116 formed on the semiconductor substrate 101, and a front gate gap 112 formed in the laminated structure 116, wherein the front gate gap 112 penetrates through the laminated structure 116 and extends to the semiconductor substrate 101;

an initial common source line 13 formed in the front gate gap 112;

a back gate gap 16 formed in the semiconductor substrate 101, wherein the back gate gap 16 exposes a bottom of the initial common source line 13;

and a common source line 19 formed in the back gate gap 16.

Since the 3D NAND memory structure in this example is to form the back gate gap 16 on the back surface of the semiconductor substrate 101 and to lead out the common source line 19 in the back gate gap 16, when the front gate gap 112 is formed on the front surface of the semiconductor substrate 101, the size (i.e., the characteristic size) of the corresponding opening pattern in the patterned mask layer may be appropriately reduced to reduce the size of the finally formed front gate gap 112, so as to reduce the area occupied by the front gate gap 112 as a whole, that is, the area occupied by the array common source is reduced as a whole, and further, the storage area of the 3D NAND memory structure is increased by approximately 1%. Moreover, in the present example, the common source line 19 is led out from the back surface of the semiconductor substrate 101, so that the positions of the common source line and the channel structure of the 3D NAND memory structure are staggered, and the parasitic capacitance between the two is effectively reduced.

As an example, as shown in fig. 23, the semiconductor intermediate structure 10 further includes: a conductive layer 110 formed between the semiconductor substrate 101 and the stacked structure 116, and a channel structure 106 formed in the stacked structure 116, wherein the stacked structure 116 includes gate layers 116b and dielectric layers 116a stacked alternately, and the channel structure 106 penetrates through the stacked structure 116 and extends to the semiconductor substrate 101; the channel structure 106 includes a channel via 106a formed in the stacked-layer structure 116, a functional sidewall 106b formed on an inner wall of the channel via 106a, a channel layer 106c, and a filling insulation layer 106d, wherein a portion of the channel layer 106c is in contact with the conductive layer 110 through a communication channel 111 penetrating through the functional sidewall 106b, and in this case, the semiconductor intermediate structure 10 further includes: and an insulating layer 114 formed between the conductive layer 110 and the stacked-layer structure 116 and between the communication channel 111 and the gate layer 116 b.

Specifically, the semiconductor substrate 101 may be selected according to actual requirements of devices, and the semiconductor substrate 101 may include a silicon substrate, a germanium substrate, a Silicon On Insulator (SOI) substrate, a Germanium On Insulator (GOI) substrate, or the like; preferably, in this example, the semiconductor substrate 101 is a silicon substrate.

Specifically, the stacked structure 116 includes the dielectric layers 116a and the gate layers 116b stacked alternately, wherein the bottom layer of the stacked structure 116 is the gate layer 116b, and the top layer of the stacked structure 116 is the dielectric layer 116 a; the material of the dielectric layer 116a may include silicon nitride, hafnium nitride, or the like, and the material of the gate layer 116b may include metal tungsten.

Specifically, as shown in fig. 23, the functional side wall 106b includes: a barrier layer 106b1 formed on an inner wall of the trench via 106 a; a memory layer 106b2 formed on the inner wall of the barrier layer 106b 1; and a tunneling layer 106b3 formed on an inner wall of the storage layer 106b 2.

The barrier layer 106b1 may include an oxide layer, wherein the material of the oxide layer may include silicon oxide, hafnium oxide, or the like.

The memory layer 106b2 may include a nitride layer, wherein the material of the nitride layer may include silicon nitride or hafnium nitride.

The tunneling layer 104b3 may include an oxide layer, wherein the material of the oxide layer may include silicon oxide, hafnium oxide, or the like.

Specifically, the channel layer 106c includes a polysilicon layer; the material of the filling insulation layer 106d may include an oxide dielectric layer, such as silicon oxide; the conductive layer 110 comprises an epitaxial silicon layer, and the communication channel 111 comprises an epitaxial polysilicon layer; the insulating layer 114 comprises a silicon oxide layer.

As an example, as shown in fig. 23, the semiconductor intermediate structure 10 further includes: a source region 113 formed in the semiconductor substrate 101 and the conductive layer 110 at the bottom of the front side gate gap 112.

As an example, as shown in fig. 23, the storage structure further includes: an initial adhesion layer 12 is formed on the inner wall of the front gate gap 112, and the initial common line 13 is formed on the inner wall of the initial adhesion layer 12. Specifically, the initial adhesion layer 12 may include a titanium layer and a titanium nitride layer.

As an example, as shown in fig. 23, the storage structure further includes: an initial spacer 11 is formed on the sidewalls of the front gate gap 112. It should be noted that, when the initial adhesion layer 12 is further formed on the inner wall of the front gate gap 112, the initial adhesion layer 12 is formed on the inner wall of the initial isolation layer 11 and the bottom of the front gate gap 112. Specifically, the material of the initial isolation layer 11 may be silicon oxide.

As an example, as shown in fig. 23, the storage structure further includes: and an adhesion layer 18 formed on the inner wall of the back gate gap 16, wherein the common line 19 is formed on the inner wall of the adhesion layer 18. Specifically, the adhesion layer 18 may include a titanium layer and a titanium nitride layer.

As an example, as shown in fig. 23, the storage structure further includes: and an isolation layer 17 formed on the sidewall of the back gate gap 16. Note that, when the adhesion layer 18 is further formed on the inner wall of the back gate gap 16, the adhesion layer 18 is formed on the inner wall of the isolation layer 17 and the bottom of the back gate gap 16. Specifically, the material of the isolation layer 17 may include silicon oxide.

As an example, as shown in fig. 23, the storage structure further includes:

a back-etching hole 14 for back-etching the initial common source line 13 to form above the retained initial common source line 13;

a top spacer layer 15 formed in the etch back hole 14.

Specifically, when the etch-back holes 14 are formed, in order to improve the stress resistance of the 3D NAND memory structure as much as possible, the more the initial common source lines 13 are etched, the better, but based on the retained initial common source lines 13, the original common source lines 13 also need to be used as an etch stop layer for forming the back gate gaps 16 later, so that it is required to ensure that the height of the retained initial common source lines 13 is greater than 1nm, where the height of the retained initial common source lines 13 is the thickness thereof along the depth direction of the front gate gaps 112. Note that when the initial isolation layer 11 and/or the initial adhesion layer 12 are formed between the front gate gap 112 and the initial common source line 13, the initial isolation layer 11 and/or the initial adhesion layer 12 are removed at the same time when the etch back hole 14 is formed.

Specifically, the top isolation layer 15 is a material layer with high stress resistance, and includes: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina. Preferably, in this example, the material of the top spacer layer 15 comprises silicon oxide. It should be noted that, in practical application, a chemical vapor deposition process is used to form silicon oxide, and at this time, the pressure, deposition rate, and temperature of the chemical vapor deposition process may be adjusted to adjust the stress resistance of the generated silicon oxide, so as to obtain silicon oxide with high stress resistance as the top insulating layer 15, thereby improving the stress resistance of the 3D NAND memory structure in this example, and at the same time, the etching back of the initial common source line and the filling of the top insulating layer may be used to improve the insulating performance between the word line and the common source line in the 3D NAND memory structure, and reduce the risk of leakage between the word line and the common source line in the 3D NAND memory structure.

As an example, the material of the initial common source line 13 may include metal tungsten, and the material of the common source line 19 may include metal tungsten.

In summary, the 3D NAND memory structure and the manufacturing method thereof of the present invention have the following beneficial effects: according to the invention, the back grid gap is formed on the back surface of the semiconductor substrate and the common source line is led out from the back grid gap, so that the common source line is prevented from being led out from the front surface of the semiconductor substrate, the characteristic size of the front grid gap formed on the front surface of the semiconductor substrate is effectively reduced, the area of the front grid gap of the semiconductor substrate is reduced, and the storage area of the 3D NAND storage structure is increased by nearly 1%; meanwhile, the common source line is led out from the back surface of the semiconductor substrate, so that the positions of the common source line and the channel structure of the 3D NAND memory structure are staggered, and the parasitic capacitance between the common source line and the channel structure is effectively reduced. According to the invention, the initial common source line formed on the front surface of the semiconductor substrate is etched back, and the top insulating layer is filled in the etching-back hole, so that the anti-stress capability of the 3D NAND memory structure is improved by utilizing the high anti-stress performance of the top insulating layer, meanwhile, the insulating performance between the word line and the common source line in the 3D NAND memory structure is improved by utilizing the etching-back initial common source line and the filling of the top insulating layer, and the electric leakage risk between the word line and the common source line in the 3D NAND memory structure is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A preparation method of a 3D NAND storage structure is characterized by comprising the following steps:

etching back the initial common source line to form a back etching hole, and filling an isolation material in the back etching hole to form a top isolation layer;

forming a common source line on the inner wall of the back gate gap to fill the back gate gap;

the method for forming the back gate gap on the surface of the semiconductor substrate away from the front gate gap opening comprises the following steps: and etching a surface of the semiconductor substrate, which is far away from the front side gate gap opening, by taking the initial common source line as an etching stop layer so as to form the back side gate gap in the semiconductor substrate.

2. The method of claim 1, wherein the isolation material is a material with high stress resistance, and comprises: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina.

3. The method of claim 1, wherein before the forming the initial common source line on the inner wall of the front gate gap, the method further comprises: forming an initial adhesion layer on the inner wall of the front gate gap, wherein the initial common line is formed on the inner wall of the initial adhesion layer;

4. The method of claim 1, wherein before the forming the initial common source line on the inner wall of the front gate gap, the method further comprises: forming an initial isolation layer on the side wall of the front side grid electrode gap;

5. The method of claim 4, wherein the step of forming the initial spacer on the sidewalls of the front gate gap comprises: forming an initial isolation material layer on the inner wall of the front gate gap, and then removing the initial isolation material layer formed at the bottom of the front gate gap to form the initial isolation layer on the side wall of the front gate gap;

6. The method of fabricating a 3D NAND memory structure as claimed in any one of claims 1 to 5 wherein the semiconductor intermediate structure further comprises: the semiconductor device comprises a semiconductor substrate, a laminated structure and a channel structure, wherein the semiconductor substrate is provided with a plurality of gate layers and dielectric layers, the semiconductor substrate is provided with a plurality of stacked layers, the stacked layers are arranged on the semiconductor substrate, the channel structure is formed between the semiconductor substrate and the laminated structure and comprises gate layers and dielectric layers which are stacked alternately, and the channel structure penetrates through the laminated structure and extends to the semiconductor substrate; the channel structure comprises a channel through hole formed in the laminated structure, and a functional side wall, a channel layer and a filling insulating layer which are sequentially formed on the inner wall of the channel through hole, wherein part of the channel layer is in contact with the conducting layer through a communication channel penetrating through the functional side wall, and the semiconductor intermediate structure further comprises: and an insulating layer formed between the conductive layer and the stacked structure and between the communication channel and the gate layer.

7. The method of fabricating a 3D NAND memory structure as claimed in claim 6 wherein the method of fabricating the semiconductor intermediate structure comprises:

removing the support layer based on the initial gate gap to form a support gap;

8. The method of claim 7, wherein after forming the front-side gate gap, the method further comprises: forming a source region in the semiconductor substrate at the bottom of the front side gate gap and in the conductive layer at the sidewall of the front side gate gap; in this case, the semiconductor intermediate structure further includes: a source region formed in the semiconductor substrate and the conductive layer at the bottom of the front side gate gap.

9. The method of claim 7, wherein the step of forming the functional sidewall on the inner wall of the trench via comprises: and forming a blocking layer on the inner wall of the channel through hole, then forming a storage layer on the inner wall of the blocking layer, and finally forming a tunneling layer on the inner wall of the storage layer.

10. The method of claim 7, wherein the step of forming the sidewall protection layer on the sidewall of the initial gate gap comprises: and forming a side wall protection material layer on the inner wall of the initial grid gap, and then removing the side wall protection material layer formed at the bottom of the initial grid gap so as to form the side wall protection layer on the side wall of the initial grid gap.

11. The method of claim 7, wherein the channel layer comprises a polysilicon layer, and wherein an epitaxial growth process is used to form an epitaxial silicon layer on the semiconductor substrate in the support gap as the conductive layer while an epitaxial polysilicon layer is formed at the exposed channel layer as the communication channel and an in-situ moisture-grown silicon oxide is used as the insulating layer.

12. A3D NAND memory structure, wherein the memory structure comprises:

an initial common source line formed in the front gate gap;

etching back the hole to form above the reserved initial common source line;

a top isolation layer formed in the etch-back hole;

a back gate gap formed in the semiconductor substrate with the initial common source line as an etch stop layer, wherein the back gate gap exposes the bottom of the initial common source line;

and the common source line is formed in the back gate gap.

13. The 3D NAND memory structure of claim 12 wherein the top spacer is a layer of material with high stress resistance comprising: silicon oxide, silicon nitride, or high K dielectrics; wherein the high-k dielectric comprises alumina.

14. The 3D NAND memory structure of claim 12 wherein the memory structure further comprises:

15. The 3D NAND memory structure of claim 12 wherein the memory structure further comprises:

and the isolation layer is formed on the side wall of the back grid gap.

16. The 3D NAND memory structure of any of claims 12 to 15 wherein the semiconductor intermediate structure further comprises: the semiconductor device comprises a semiconductor substrate, a laminated structure and a channel structure, wherein the semiconductor substrate is provided with a plurality of gate layers and dielectric layers, the semiconductor substrate is provided with a plurality of stacked layers, the stacked layers are arranged on the semiconductor substrate, the channel structure is formed between the semiconductor substrate and the laminated structure and comprises gate layers and dielectric layers which are stacked alternately, and the channel structure penetrates through the laminated structure and extends to the semiconductor substrate; the channel structure comprises a channel through hole formed in the laminated structure, and a functional side wall, a channel layer and a filling insulating layer which are sequentially formed on the inner wall of the channel through hole, wherein part of the channel layer is in contact with the conducting layer through a communication channel penetrating through the functional side wall, and the semiconductor intermediate structure further comprises: and an insulating layer formed between the conductive layer and the stacked structure and between the communication channel and the gate layer.

17. The 3D NAND memory structure of claim 16 wherein the semiconductor intermediate structure further comprises: a source region formed in the semiconductor substrate and the conductive layer at the bottom of the front side gate gap.

18. The 3D NAND memory structure of claim 16 wherein the functional sidewalls comprise:

the barrier layer is formed on the inner wall of the channel through hole;

the storage layer is formed on the inner wall of the barrier layer;

and the tunneling layer is formed on the inner wall of the storage layer.

19. The 3D NAND memory structure of claim 16 wherein the channel layer comprises a polysilicon layer, the conductive layer comprises an epitaxial silicon layer, the communication channel comprises an epitaxial polysilicon layer, and the insulating layer comprises a silicon oxide layer.