CN111404549B - Analog-to-digital converter and analog-to-digital conversion method - Google Patents
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Abstract
The embodiment of the application provides an analog-to-digital converter and an analog-to-digital conversion method. The capacitor array comprises a first capacitor array and a second capacitor array; the logic control circuit is configured to apply a preset reference control signal to each capacitor in the first capacitor array, adjust the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator, and output an increment digital signal according to the result of the comparison action and the preset reference digital signal. The analog-to-digital converter provided by the embodiment of the application can avoid the possible capacitance state difference of the first capacitor array during conversion, ensure the accuracy of the increment digital signal and improve the conversion precision of the analog-to-digital converter.
Description
Technical Field
The application relates to the technical field of analog-to-digital conversion, in particular to an analog-to-digital converter and an analog-to-digital conversion method.
Background
The successive approximation analog-to-digital converter (Successive Approximation REGISTER ADC, SAR ADC) is a structure which adopts a capacitor inversion strategy to realize medium conversion precision and medium sampling speed. In some measurement applications, only the measured variation is concerned, the conventional SAR ADC needs to accurately measure the determined values before and after the measured variation to accurately determine the variation, and due to factors such as capacitance matching performance, the measured capacitance state is often different before and after, so that an error exists in the measurement result.
Disclosure of Invention
In view of the above, embodiments of the present application provide an analog-to-digital converter and an analog-to-digital conversion method, so as to solve the above technical problems.
The embodiment of the application is realized by adopting the following technical scheme:
An analog-to-digital converter comprises a capacitor array, a comparator and a logic control circuit; the capacitor array is used for sampling and converting analog input signals and comprises a first capacitor array and a second capacitor array; the input end of the comparator is connected with the capacitor array, and the comparator is configured to execute comparison action according to the input signal of the input end based on the control signal; the logic control circuit is connected with the comparator and the capacitor array, is configured to apply a preset reference control signal to each capacitor in the first capacitor array, adjusts the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator, and is also configured to output an increment digital signal according to the result of the comparison action and the preset reference digital signal; after the reference digital signal is obtained by sampling and converting the reference input signal by the capacitor array, the logic control circuit adjusts the conversion result of the analog-to-digital converter when the control signal applied to the first capacitor array is regulated according to the comparison action of the comparator; the reference control signal is a control signal which is applied to the first capacitor array and regulated by the logic control circuit during the generation period of the reference digital signal; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal.
In some embodiments, the logic control circuit is configured to adjust the control signals in the first capacitive array to the reference control signals according to the reference digital signal during application of a preset reference control signal to each of the capacitances in the first capacitive array.
In some embodiments, the logic control circuit is configured to maintain the control signal for each capacitor in the second capacitor array unchanged during the generation of the reference digital signal, and to adjust the control signal applied to the first capacitor array in the current comparison operation based on the result of the last comparison operation by the comparator.
In some embodiments, the reference digital signal includes a number of digital bits, where each digital bit corresponds to the result of a comparison action by the comparator at a time.
In some embodiments, the logic control circuit is configured to generate a comparison digital signal according to a result of the comparison action during output of the delta digital signal, and perform a difference operation on the comparison digital signal and a least significant bit of the reference digital signal to output the delta digital signal.
In some embodiments, the input of the comparator comprises a first input and a second input, the first capacitor array comprises M capacitor pairs, each capacitor pair comprises two capacitors with equal capacitance values, one capacitor is connected with the first input of the comparator, and the other capacitor is connected with the second input of the comparator; in the M-bit capacitor pair, the capacitance values of the first two capacitor pairs are equal, and the capacitance values of the third to M-th capacitors are increased by the power of 2; wherein M is an integer greater than or equal to 1.
In some embodiments, the first capacitor array further includes a pair of redundant capacitors, the pair of redundant capacitors being disposed between any two of the pairs of M-bit capacitors, the pair of redundant capacitors having a capacitance equal to a capacitance of a lower pair of adjacent pairs of two-bit capacitors.
In some embodiments, the second capacitor array comprises P-bit capacitor pairs, each capacitor pair comprising two capacitors of equal capacitance values, one capacitor connected to the first input of the comparator and the other capacitor connected to the second input of the comparator; the capacitance values of the first two capacitor pairs are equal, and the capacitance values of the third capacitor to the P capacitor are increased by the power of 2; wherein P is an integer greater than or equal to 1.
In some embodiments, the number of capacitances in the second capacitive array is less than the number of capacitances in the first capacitive array.
The embodiment of the application also provides an analog-to-digital conversion method which is applied to the analog-to-digital converter and comprises the steps of sampling and converting an analog input signal; applying a preset reference control signal to each capacitor in the first capacitor array, and adjusting the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator; outputting an incremental digital signal according to the result of the comparison action and a preset reference digital signal; the reference digital signal is a conversion result of the analog-to-digital converter when the logic control circuit adjusts the control signal applied to the first capacitor array according to the comparison action of the comparator; the reference control signal is a control signal applied after the logic control circuit adjusts the control signal of the first capacitor array in the reference digital signal generation period; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal.
The embodiment of the application provides an analog-to-digital converter and an analog-to-digital conversion method, wherein the analog-to-digital converter is provided with a capacitor array, a comparator and a logic control circuit; the capacitor array comprises a first capacitor array and a second capacitor array and is used for sampling and converting analog input signals; the comparator comprises a first input end and a second input end, the first input end and the second input end are connected to the capacitor array, and the comparator is configured to perform comparison action on input signals of the first input end and the second input end based on control signals; the logic control circuit is connected with the comparator and the capacitor array, is configured to apply a preset reference control signal to each capacitor in the first capacitor array, adjusts the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator, and is also configured to output an increment digital signal according to the result of the comparison action and the preset reference digital signal; the reference digital signal is a conversion result of the analog-to-digital converter when the logic control circuit adjusts the control signal applied to the first capacitor array according to the comparison action of the comparator; the reference control signal is a control signal applied after the logic control circuit adjusts the control signal of the first capacitor array in the reference digital signal generation period; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal. In the embodiment of the application, when the analog-to-digital converter works, the conversion result of the first capacitor array part is consistent with the reference digital signal by applying the preset reference control signal to each capacitor in the first capacitor array, and the analog-to-digital converter only converts the difference value between the input signal of the current sampling and the reference input signal by only adjusting the control signal of the second capacitor array part when the comparator executes the comparison action, so that the capacitance state difference possibly occurring in the first capacitor array during the conversion is avoided, the accuracy of the increment digital signal is ensured, and the conversion precision of the analog-to-digital converter is improved.
These and other aspects of the application will be more readily apparent from the following description of the embodiments.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a block diagram of an analog-to-digital converter according to an embodiment of the present application.
Fig. 2 is a schematic circuit diagram of an analog-to-digital converter according to an embodiment of the present application.
Fig. 3 shows a schematic circuit structure of a 12-bit analog-to-digital converter according to an embodiment of the present application.
Fig. 4 shows a timing diagram of the operation of the analog-to-digital converter provided in the embodiment of the application in the reference measurement stage.
Fig. 5 shows a timing diagram of the operation of the analog-to-digital converter in the incremental measurement phase according to the embodiment of the present application.
Fig. 6 shows a flow chart of an analog-to-digital conversion method according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present application and are not to be construed as limiting the present application.
The successive approximation analog-to-digital converter (Successive Approximation REGISTER ADC, SAR ADC) is a structure which adopts a capacitor inversion strategy to realize medium conversion precision and medium sampling speed. In some applications of measurement, only the measured variation (especially in the field of touch detection) is concerned, the conventional SAR ADC needs to accurately measure the determined values before and after the measured variation to accurately determine the variation, for example, in the application of pressure measurement, it is first required to measure a reference measurement value when no touch occurs on the device, then measure a press measurement value when the device is in a touch state, and the variation of the press measurement value relative to the reference measurement value, that is, the pressure value applied by the user, and the conventional SAR ADC needs to accurately measure the reference measurement value and the press measurement value to finally obtain the pressure value applied in practice. In actual measurement, due to factors such as capacitance matching performance in the SAR ADC, the capacitance states measured before and after are often different, so that errors exist in the final measurement result.
In order to solve the technical problems, the inventor provides an analog-to-digital converter and an analog-to-digital conversion method in the embodiment of the application through long-term research, wherein the analog-to-digital converter is provided with a capacitor array, a comparator and a logic control circuit; the capacitor array comprises a first capacitor array and a second capacitor array and is used for sampling and converting analog input signals; the input end of the comparator is connected with the capacitor array, and the comparator is configured to execute comparison action on the input signal of the input end based on the control signal; the logic control circuit is connected with the comparator and the capacitor array, is configured to apply a preset reference control signal to each capacitor in the first capacitor array, adjusts the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator, and is also configured to output an increment digital signal according to the result of the comparison action and the preset reference digital signal; the logic control circuit adjusts the conversion result of the analog-to-digital converter when the control signal applied to the first capacitor array is regulated according to the comparison action of the comparator after the reference digital signal is sampled and converted by the capacitor array; the reference control signal is a control signal which is applied to the first capacitor array and regulated by the logic control circuit during the generation period of the reference digital signal; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal. In the embodiment of the application, when the analog-to-digital converter works, the conversion result of the first capacitor array part is consistent with the reference digital signal by applying the preset reference control signal to each capacitor in the first capacitor array, and the analog-to-digital converter only converts the difference value between the input signal of the current sampling and the reference input signal by only adjusting the control signal of the second capacitor array part when the comparator executes the comparison action, thereby avoiding the capacitor state difference possibly occurring in the first capacitor array during the conversion, ensuring the accuracy of the increment digital signal and improving the conversion precision of the analog-to-digital converter.
In order to enable those skilled in the art to better understand the solution of the present application, the following description will make clear and complete descriptions of the technical solution of the present application in the embodiments of the present application with reference to the accompanying drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
As shown in fig. 1, fig. 1 schematically shows a block diagram of an analog-to-digital converter 100 according to an embodiment of the present application. The analog-to-digital converter 100 includes a capacitor array 110, a comparator 120, and a logic control circuit 130. The capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112; the capacitor array 110 is used for sampling and converting an analog input signal, which may be a differential input signal or a single-ended input signal. The comparator 120 includes a first input terminal and a second input terminal, at least one of the first input terminal and the second input terminal is connected to the capacitor array 110; the logic control circuit 130 is connected to the comparator 120 and the capacitor array 110.
The comparator 120 is configured to perform a comparison action on the input signals of the first input terminal and the second input terminal based on the control signal. Specifically, when the capacitor array 110 is used to sample a differential input signal, the first input terminal and the second input terminal of the comparator 120 are both connected to the first capacitor array 111 and the second capacitor array 112, and the comparator 120 is configured to compare the voltage on the capacitor plate connected to the first input terminal with the voltage on the capacitor plate connected to the second input terminal. When the capacitor array 110 is used for sampling a single-ended input signal, one of the first input terminal and the second input terminal of the comparator 120 is connected to the first capacitor array 111 and the second capacitor array 112, and the other is used for accessing a preset reference voltage. The comparator 120 is configured to compare the voltage on the connected capacitive plate with a reference voltage.
The logic control circuit 130 is configured to apply a preset reference control signal to each capacitor in the first capacitor array 111, and adjust the control signal applied to the second capacitor array 112 in the current comparison according to the result of the last comparison of the comparator 120, so as to change the signals input by the first input terminal and the second input terminal in the current comparison. The logic control circuit 130 is further configured to output an incremental digital signal based on the result of the comparing action and a preset reference digital signal. After the reference digital signal is a reference input signal sampled and converted by the capacitor array, when the logic control circuit 130 adjusts the control signal applied to the first capacitor array 111 according to the comparison action of the comparator 120, the conversion result of the analog-to-digital converter 100; the reference control signal is a control signal applied to the first capacitor array 111 and adjusted by the logic control circuit 130 during the reference digital signal generation period; the delta digital signal is a delta detection result of the analog-to-digital converter 100 based on the reference digital signal, i.e. the delta digital signal is used to characterize the difference between the currently sampled analog input signal and the reference input signal corresponding to the reference digital signal.
Alternatively, the reference digital signal may be a conversion result of the last sampling signal of the capacitor array 110, or may be a preset, fixed digital signal.
When the analog-to-digital converter 100 works, the comparator 120 compares the input signals of the first input end and the second input end for a plurality of times, the logic control circuit 130 generates corresponding code values according to the comparison result after the comparator 120 performs the comparison operation each time, and controls one capacitor in the capacitor array to turn over according to the sequence from the highest bit to the lowest bit, wherein the turning over of the capacitor refers to the control signal for adjusting the capacitor so as to change the plate voltage thereof, and thus, the voltage of the input end of the comparator changes. After the conversion from the most significant bit to the least significant bit is completed, a digital sequence comprising a plurality of code values is obtained. In this embodiment, a preset reference control signal is applied to each capacitor in the first capacitor array 111, so that the conversion result corresponding to the first capacitor array 111 partially matches with the reference digital signal, and then only the control signal of the second capacitor array 112 is adjusted when the comparator 120 performs the comparison operation. In this way, the state of the first capacitor array 111 keeps consistent with the reference state during the conversion period, so that the conversion result of the first capacitor array 111 is consistent with the reference digital sequence, and then when the second capacitor array 112 performs conversion, the control signal of each capacitor in the second capacitor array 112 is only inverted according to the difference between the current sampled signal and the reference input signal, so that the conversion result based on the second capacitor array 112 is finally approximated to the difference. In this process, the capacitance state difference possibly occurring in the first capacitor array 111 during the conversion is avoided, the accuracy of the incremental digital signal is ensured, and the conversion accuracy of the analog-to-digital converter 100 is improved.
In the embodiment of the application, the analog input signal can be a differential input signal or a single-ended input signal. And the analog input signal is a single-ended input signal, the principle of the analog-to-digital converter 100 is identical to that of the analog input signal being a differential input signal. The following embodiments are exemplified by differential input signals only. No substantial improvement over the embodiments of the present application is intended to fall within the scope of the present application.
Specifically, as shown in fig. 2, fig. 2 shows a schematic structural diagram of an analog-to-digital converter 100 according to an embodiment of the present application. The capacitor array 110 includes a first capacitor array 111 and a second capacitor array 112, wherein the first capacitor array 111 and the second capacitor array 112 are both connected to an input end of the comparator 120, and the first capacitor array 111 is a main capacitor array and the second capacitor array 112 is an incremental capacitor array. The first capacitor array 111 includes M capacitor pairs, each of which includes two capacitors, one of which is a P-terminal capacitor and the other of which is an N-terminal capacitor. The P-terminal capacitors in each pair of capacitors of the first capacitor array 111 together form a P-terminal main capacitor array Cp, and the N-terminal capacitors in each pair of capacitors together form an N-terminal main capacitor array Cn. The P-terminal main capacitor array Cp is connected to a first input terminal of the comparator 120, and the N-terminal main capacitor array Cn is connected to a second input terminal of the comparator 120, wherein the first input terminal is a non-inverting input terminal of the comparator 120, and the second input terminal is an inverting input terminal of the comparator 120. The second capacitor array 112 includes P-bit capacitor pairs, each of which also includes two capacitors, one of which is a P-terminal capacitor and the other of which is an N-terminal capacitor. The P-terminal capacitors in each pair of capacitors of the second capacitor array 112 together form a P-terminal incremental capacitor array CAp, and the N-terminal capacitors in each pair of capacitors together form an N-terminal incremental capacitor array CAn. The P-terminal increment capacitor array CAp is connected to the first input terminal of the comparator 120, and the N-terminal increment capacitor array CAn is connected to the second input terminal of the comparator 120. M and P are integers greater than or equal to 1.
One end of each capacitor in the capacitor array 110 is connected to an input end (a first input end or a second input end) of the comparator 120, and the other end selectively receives a control signal through a multi-way switch. The control signals include a first control signal Vcm, a second control signal Vref, and a third control signal Gnd. The logic control circuit 130 controls the on-off of the multi-way switch through a clock so as to switch the control signal of each capacitor among the first control signal Vcm, the second control signal Vref and the third control signal Gnd. The logic control circuit 130 is further connected to the output terminal of the comparator 120 to receive the output signal of the comparator 120 and control the control signal selected by the multi-way switch according to the output signal. The analog-to-digital converter 100 may further include a sampling switch Ks, where the sampling switch Ks is disposed at an input end of the comparator 120, and when the sampling switch Ks is closed, the capacitor array 110 may sample and convert the analog input signals Vip and Vin, wherein the P-terminal main capacitor array Cp and the P-terminal incremental capacitor array CAp sample the input signal Vip, and the N-terminal main capacitor array Cn and the N-terminal incremental capacitor array CAn sample the input signal Vin.
After the capacitor array 110 is sampled, the comparator 120 is configured to perform a comparison operation on the input signals of the first input terminal and the second input terminal of the comparator 120 based on the control signal. Specifically, the voltage between the P-side capacitor array and the N-side capacitor array in the capacitor array 110 is compared, and the logic control circuit 130 controls the one-bit capacitor pair in the capacitor array 110 to flip every time the comparator 120 compares the voltages.
During the comparison process of the comparator 120, the logic control circuit 130 sequentially controls the pairs of capacitors in the capacitor array 110 to sequentially flip from high to low. In the embodiment of the present application, the capacitance value of each capacitor pair, i.e., one capacitor in the capacitor array 110, is equal, and the capacitance value of each capacitor pair is represented as the capacitance value of the capacitor pair. The number of bits in the first capacitor array 111 decreases sequentially from the mth capacitor pair Cm to the first capacitor pair C1, with the capacitor pair Cm being the highest and the capacitor pair C1 being the lowest. In the M-bit capacitor pairs of the first capacitor array 111, the capacitance values of the first two capacitor pairs are equal, and the capacitance values of the third capacitor pair C3 to the M-th capacitor pair Cm are increased by a power of 2. The first two pairs of capacitors, namely the two pairs of low-order capacitors (the first pair of capacitors C1 and the second pair of capacitors C2). Assuming that the capacitance value of the first capacitor pair C1 is C 0, the capacitance values of the mth capacitor pair Cm to the first capacitor pair C1 according to the capacitor inversion sequence may be 2M-2C0···2i-2C0···22C0、21C0、C0、C0; in sequence, where i is the number of bits of each capacitor pair in the first capacitor array 111. Similarly, the number of bits in the second capacitor array 112 sequentially decreases from the P-th capacitor pair CAp to the first capacitor pair CA1, the capacitor pair CAp is the highest, the capacitor pair CA1 is the lowest, the capacitance values of the first two capacitor pairs in the P-bit capacitor pair of the second capacitor array 112 are equal, and the capacitance values of the third capacitor pair CA3 to the P-th capacitor pair CAp are increased by a power of 2. The first two pairs of capacitors, namely the two pairs of low-order capacitors (first pair CA1 and second pair CA 2). Assuming that the capacitance value of the first capacitor pair CA1 is C 0, the capacitance values from the P-th capacitor pair CAp to the first capacitor pair CA1 according to the capacitor inversion sequence may be 2P-2C0···2I-2C0···22C0、21C0、C0、C0; in sequence, where I is the number of bits per capacitor pair in the second capacitor array 112.
Further, during the transition of the capacitor array 110, the logic control circuit 130 adjusts the control signal applied to the capacitor pair during the current comparison operation according to the result of the last comparison operation of the comparator 120. Specifically, the comparator 120 compares the voltages on the P-side capacitor array and the N-side capacitor array after sampling, one comparison result is obtained by one comparison operation, and the logic control circuit adjusts the control signal applied to the capacitor during the next comparison operation according to the comparison result. In the embodiment of the present application, the logic control circuit 130 controls the capacitance inversion during the process of adjusting the control signal of the capacitance. The logic control circuit 130 controls the next capacitor pair to flip according to the result of each comparison operation. For example, after the comparator 120 performs the first comparison, the logic control circuit 130 controls the M-th capacitor pair Cm at the highest position in the first capacitor array 111 to be flipped according to the comparison result, and controls the M-1-th capacitor pair Cm-1 to be flipped according to the result of the second comparison. It should be noted that, after the logic control circuit 130 toggles the second bit capacitor pair C2 and the comparator again compares the signals between the two input terminals, the first bit capacitor pair C1 is not required to be flipped, that is, the first capacitor array 111 including the M bit capacitor pair needs to flip the capacitor M-1 times.
In a specific embodiment, after the comparator 120 performs the first comparison, the logic control circuit 130 generates a code value D [ M ] according to the result of the first comparison, and the logic control circuit 130 controls the M-th bit of the most significant bits in the first capacitor array 111 to flip the capacitors according to the code value D [ M ]. If dm=1, the logic control circuit 130 adjusts the control signal of the P-terminal capacitor in the mth capacitor pair to the third control signal Gnd and adjusts the control signal of the N-terminal capacitor to the second control signal Vref; if dm=0, the logic control circuit 130 adjusts the control signal of the P-side capacitor in the mth pair to the second control signal Vref and the control signal of the N-side capacitor to the third control signal Gnd. After the conversion of the first capacitor array 111 is finished, the logic control circuit 130 controls the capacitors in the first capacitor array 111 to be sequentially flipped M-1 times, and generates a digital sequence of M bits according to the output signal of the comparator 120 during the flipping process. For example, assuming that the first capacitor array 111 includes 12-bit capacitor pairs, the logic control circuit 130 controls the capacitors in the first capacitor array 111 to sequentially flip 11 times, and finally obtains a comparison result D [12 ] including 12 code values: 1].
In this embodiment, during the incremental measurement phase, the logic control circuit 130 directly applies a preset reference control signal to each capacitor in the first capacitor array 111. The reference control signal is a control signal applied to each capacitor in the first capacitor array 111 when the logic control circuit 130 controls each capacitor in the first capacitor array 111 to flip after the first capacitor array 111 samples and converts the reference input signal in the reference measurement phase of the analog-to-digital converter 100. Taking the analog-to-digital converter 100 as an example for converting a touch signal, the analog-to-digital converter 100 may sample a reference input signal at a reference measurement stage when the device is in a reference state and convert the reference input signal by turning over the capacitance of the first capacitor array 111, during the conversion process of the first capacitor array 111, the logic control circuit 130 turns over the capacitance by adjusting the control signal of each capacitance in the first capacitor array 111, and after the conversion based on the turning over of the capacitance of the first capacitor array 111 is completed, the logic control circuit 130 may obtain a conversion result, which is actually a digital sequence, that is, a reference digital signal. The reference digital signal may reflect the adjustment of the control signal on each capacitor by the logic control circuit 130 when controlling the capacitor in the first capacitor array 111 to flip, and the adjusted control signal is the reference control signal applied by the logic control circuit 130 when the comparator 120 outputs the reference digital signal.
In the first capacitor array 111 and the second capacitor array 112, the logic control circuit 130 sequentially inverts each capacitor from the high order to the low order. When the first capacitor array 111 is applied with a preset reference control signal, the logic control circuit 130 may directly obtain the conversion result of the portion of the first capacitor array 111, that is, a pre-stored reference digital signal corresponding to the reference control signal, where the reference digital signal also represents a reference measurement value when the device is in a reference state. In the embodiment of the present application, during the incremental measurement stage, since the first capacitor array 111 is already applied with the preset reference control signal, when the analog-to-digital converter 100 performs the incremental measurement, the capacitors in the first capacitor array 111 have the same inversion state as the reference state, and only the capacitors in the second capacitor array 112 need to be sequentially inverted from the high position to the low position. The flipping action of the second capacitor array 112 at this time makes the conversion result of the second capacitor array 112 represent the increment of the analog input signal sampled at present relative to the reference measurement value, that is, the increment detection result based on the reference measurement value.
In the embodiment of the application, when the analog-to-digital converter works, the conversion result of the first capacitor array part is consistent with the reference digital signal by applying the preset reference control signal to each capacitor in the first capacitor array, and the analog-to-digital converter converts the increment through the second capacitor array on the basis of the reference measured value when the device is in the reference state by only adjusting the control signal of the second capacitor array part when the comparator executes the comparison action, so that the capacitance state difference possibly occurring in the first capacitor array during the conversion period is avoided, the accuracy of the increment digital signal is ensured, and the conversion precision of the analog-to-digital converter is improved.
As shown in fig. 3, another analog-to-digital converter 200 is also provided in an embodiment of the present application. The analog-to-digital converter 200 has the same structure as the analog-to-digital converter 100 described above.
On the basis of the analog-to-digital converter 100 described above, the logic control circuit 230 in the analog-to-digital converter 200 is further configured to adjust the control signal in the first capacitor array 211 to a reference control signal according to the reference digital signal during application of a preset reference control signal to each capacitor in the first capacitor array 211. And during the generation of the reference digital signal, the control signal of each capacitor in the second capacitor array 212 is kept unchanged, and the control signal applied to the first capacitor array 211 in the current comparison is adjusted according to the result of the previous comparison.
Generally, the detection process of the analog-to-digital converter 200 includes a reference measurement phase and an incremental measurement phase. The change value between the actual measurement value and the reference measurement value, namely the increment of the detection value of the current state relative to the detection value of the reference state, is calculated by measuring the reference measurement value when the device is in the reference state in the reference measurement stage and measuring the actual measurement value of the current state in the increment measurement stage. Taking the application in touch detection as an example, the reference state can be a state when not touched, or can be a state at an earlier time in a period of time of touching, whether the user performs effective touch action can be determined by comparing the increment with a preset touch threshold value, and if the touch threshold value is reached, the system reacts to the touch.
In the present embodiment, during the reference measurement phase, the logic control circuit 230 keeps the control signal of each capacitor in the second capacitor array 212 unchanged, and in this process, the analog-to-digital converter 200 performs analog-to-digital conversion based only on the capacitance inversion of the first capacitor array 211, and the logic control circuit 230 inverts only the capacitance in the first capacitor array 211, but the capacitance in the second capacitor array 212 does not need to be inverted. Similarly, during the capacitor inversion process, the logic control circuit 230 adjusts the control signal applied to the first capacitor array 211 in the current comparison operation according to the result of the previous comparison operation. Thereafter, the logic control circuit 230 will obtain a reference conversion result, that is, a reference digital signal, which converts the sampling signal of the reference input signal according to the first capacitor array 211.
In the incremental measurement phase, the logic control circuit 230 sets the control signal in the first capacitor array 211 to the reference control signal according to the reference digital signal. In performing the measurement, the first capacitor array 211 may need to resample the signal, and during the sampling period, the capacitors in the first capacitor array 211 and the second capacitor array 212 need to be reset, for example, each capacitor is reset by accessing the first control signal Vcm. After the sampling is finished, the control signal of the first capacitor array 211 is switched to a fixed reference control signal, so that the capacitor of the first capacitor array 211 has the same overturning state as under the reference measurement in the incremental measurement stage, and further, the incremental measurement result based on the reference measurement can be directly obtained by controlling the overturning of the capacitor of the second capacitor array 212. The reference digital signal and the incremental digital signal are actually digital sequences, which each include a plurality of digital bits, and each digital bit corresponds to a code value. Further, the logic control circuit 230 is further configured to generate a comparison digital signal according to the result of the comparison operation of the comparator 220 during the output of the increment digital signal, and perform a difference operation on the least significant bits of the comparison digital signal and the reference digital signal to output the increment digital signal.
During the generation of the reference digital signal, after the least significant bit is generated, the first capacitor array 211 is converted, and the first capacitor C1 of the least significant bit does not need to be flipped. Then after the reference control signal is applied to the first capacitor array 211 in the incremental measurement phase, the first capacitor pair C1 in the first capacitor array 211 is not flipped at this time, since the flipped state of the capacitors in the first capacitor array 211 is the same as the flipped state of the reference measurement phase. After the conversion is completed, the conversion result based on the inversion of the second capacitor array 212 actually includes the comparison result of the comparator 220 for the last time during the generation of the reference digital signal. That is, the digital sequence obtained by the logic control circuit 230 according to the conversion result of the second capacitor array 212 in the reference measurement stage is the above-mentioned comparison digital signal, and the comparison digital signal includes the signal corresponding to the least significant bit of the reference digital signal, so that the difference between the comparison digital signal and the least significant bit of the reference digital signal is calculated, so that during the incremental measurement stage, the influence of the first capacitor in the first capacitor array 211 on the C1 not being flipped when the reference control signal is applied to the first capacitor array 211 is removed from the conversion result of the second capacitor array 212, thereby obtaining an accurate incremental detection result.
In some embodiments, since the second capacitor array 212 is only used for incremental conversion, the number of capacitor pairs in the second capacitor array 212 may be lower than the number of capacitor pairs in the first capacitor array 211, and compared with the conventional analog-to-digital converter, the analog-to-digital converter 200 provided in this embodiment needs to switch the capacitors in the same capacitor array twice before and after measurement, and the required switch capacitor in the incremental measurement stage is less than the required switch capacitor in the reference measurement stage, so that the clock required for controlling the switch capacitor in the incremental measurement stage is less, thereby reducing the response time of the analog-to-digital converter 200 during measurement and improving the conversion rate of the analog-to-digital converter 200. And since the second capacitor array 212 is a small capacitor array relative to the first capacitor array 211, the small capacitor array introduces smaller errors under the condition of the same matching precision, so that the analog-to-digital converter 200 can achieve higher linearity.
In the analog-to-digital converter 200 provided in this embodiment, during the incremental measurement stage, the control signal in the first capacitor array 211 is first adjusted to the reference control signal according to the reference digital signal, so that the conversion result corresponding to the first capacitor array 211 is consistent with the reference digital signal, and then only the control signal of the second capacitor array 212 is adjusted when the comparator 220 performs the comparison operation. In this way, the state of the first capacitor array 211 is kept consistent with the reference state during the conversion period, so that the conversion result of the first capacitor array 211 is consistent with the reference digital sequence, and then, when the second capacitor array 212 performs conversion, the conversion result of the final second capacitor array 212 is successively approximated to the difference value by merely reversing the control signal of each capacitor in the second capacitor array 212 according to the difference value between the current sampled signal and the reference input signal. In this process, the capacitance state difference possibly occurring in the first capacitor array 211 during the conversion is avoided, the accuracy of the incremental digital signal is ensured, and the conversion accuracy of the analog-to-digital converter 200 is improved.
The principle of the analog-to-digital converter 200 provided in the embodiment of the present application will be described below by taking a 12-bit SAR ADC as an example. Fig. 3 is a schematic structural diagram of a 12-bit SAR ADC according to an embodiment of the present application. The first capacitor array 211 comprises 12-bit capacitor pairs (C12-C1), wherein the lower plate of the P-end main capacitor array Cp samples the input signal Vip, and the upper plate receives the control signals (the first control signal Vcm/the second control signal Vref/the third control signal Gnd); the upper plate of the main capacitor array Cn at the N terminal samples the input signal Vin, and the lower plate receives the control signal (the first control signal Vcm/the second control signal Vref/the third control signal Gnd). The second capacitor array 212 comprises a 5-bit capacitor pair (CA 5-CA 1), wherein the lower plate of the P-terminal increment capacitor array CAp samples an input signal Vip, and the upper plate receives a control signal (a first control signal Vcm/a second control signal/Vref/a third control signal Gnd); the upper electrode plate of the N-terminal increment capacitor array CAn samples an input signal Vin, and the lower electrode plate receives control signals (a first control signal Vcm/a second control signal Vref/a third control signal Gnd). It should be noted that, the number of bits of the second capacitor array 212 is only 5, and may be actually increased or decreased according to design requirements, and preferably the number of bits of the second capacitor array 212 may be smaller than the number of bits of the first capacitor array 211, so as to improve linearity and response speed of the analog-to-digital converter 200. Of course, the higher the number of bits of the second capacitor array 212, the higher the accuracy of the analog-to-digital converter 200.
In this embodiment, the voltage value of the first control signal Vcm may be half of the voltage value of the second control signal Vref; the third control signal Gnd is at zero potential.
Fig. 3 and fig. 4 show a timing chart of the operation of the analog-to-digital converter 200 in the reference measurement stage according to the embodiment of the application in fig. 4. Wherein, the signal sample is the control signal of sampling switch Ks, when the signal sample is high level, sampling switch Ks is closed; when the signal Sample is low, the sampling switch Ks is turned off. The clock signal clk is an operation clock of the analog-to-digital converter 200, and data is a comparison result output from the comparator 220.
In the reference measurement phase, when the signal sample is high, the sampling switch Ks is closed, and the capacitor array 210 samples the differential analog input signals Vip and Vin; at this time, the logic control circuit 230 switches the control signal of each capacitor of the first capacitor array 211 and the second capacitor array 212 to the first control signal Vcm.
When the signal sample is turned to a low level, the sampling switch Ks is turned off, and the comparator 220 compares voltages on the P-terminal capacitor array and the N-terminal capacitor array at its input end, and during the comparison, the logic control circuit 230 controls the capacitance in the first capacitor array 211 to be inverted according to the comparison result D of each time of the comparator 220, that is, switches the control signal of the capacitance in the next comparison operation in the first capacitor array 211 according to the comparison result D of each time of the comparator 220. When the comparator 220 outputs the code value D12 after the first comparison, the logic control circuit 230 controls the twelfth capacitor pair C12 in the first capacitor array 211 to flip according to the code value D12. When the comparator 220 outputs the code value D11 after the second comparison, the logic control circuit 230 controls the eleventh capacitor pair C11 in the first capacitor array 211 to flip according to the code value D11. And so on, when the 12 th comparison of the comparator 220 is completed, the code value D [1] is output, and at this time, the first capacitor pair C1 does not need to be flipped because the 12-bit code value is obtained.
In the process of controlling the capacitor to turn over by the logic control circuit 230, if the current comparison result d=1, the logic control circuit 230 switches the control signal of the P-terminal capacitor in the next comparison to the third control signal Gnd, and switches the control signal of the N-terminal capacitor to the second control signal Vref; if the current comparison result d=0, the logic control circuit 230 switches the control signal of the P-terminal capacitor in the next comparison to the second control signal Vref and switches the control signal of the N-terminal capacitor to the third control signal VGnd.
After the conversion of the first capacitor array 211 is completed, the logic control circuit 230 outputs the result signal D [12 ] according to the comparator 220: 1] generating a reference digital signal. In this process, the logic control circuit 230 keeps the control signal of each capacitor in the second capacitor array 212 always being the first control signal Vcm, that is, does not flip the capacitor in the second capacitor array 212.
In some embodiments, a one-bit redundant capacitor pair may be inserted in the first capacitor array 211. The redundant capacitor pair may be configured between any two capacitor pairs in the first capacitor array 211, and the capacitance value of the redundant capacitor pair is equal to the capacitance value of the lower capacitor pair of the adjacent two capacitor pairs. For example, a redundant capacitor pair is inserted between the fifth capacitor pair and the sixth capacitor pair, and the capacitance value of the redundant capacitor pair is equal to the capacitance value of the fifth capacitor pair. The redundant capacitor pair can ensure that the first capacitor array 211 does not lose codes in the conversion process.
Fig. 3 and 5 show a timing chart of the operation of the analog-to-digital converter 200 in the incremental measurement stage according to the embodiment of the application in fig. 5. Wherein, the signal sample is the control signal of sampling switch Ks, when the signal sample is high level, sampling switch Ks is closed; when the signal Sample is low, the sampling switch Ks is turned off. The clock signal clk is an operation clock of the analog-to-digital converter 200, and data is a comparison result output from the comparator 220.
In the incremental measurement phase, the capacitive array 210 needs to resample the external differential analog input signals Vip and Vin. Similarly, when the signal sample is high, the sampling switch Ks is closed and the capacitor array 210 samples the analog input signals Vip and Vin; at this time, the logic control circuit 230 switches the control signal of each capacitor of the first capacitor array 211 and the second capacitor array 212 to the first control signal Vcm.
When the signal sample transitions to a low level, the sampling switch Ks is turned off. In the first clock cycle after the sampling is completed, the logic control circuit 230 generates a reference digital signal D [12 ] according to the reference measurement phase: 1, the control signal of each capacitor in the first capacitor array 211 is restored to the control signal which is the same in the conversion process of the reference measurement phase, so that the inversion state of the capacitor in the first capacitor array 211 is the same as the reference measurement phase. In this embodiment, the first clock cycle of the clock signal clk after the sampling is completed may be referred to as the voltage back-scaling stage b. After the voltage scaling stage b is completed, the comparator 220 starts to compare the voltages before the P-terminal capacitor array and the N-terminal capacitor array at the input ends thereof, and during the comparison process, the logic control circuit 230 controls the capacitance in the second capacitor array 212 to be inverted according to the comparison result DA of the comparator 220 each time, that is, switches the control signal of the capacitance in the next comparison operation in the second capacitor array 212 according to the comparison result DA of the comparator 220 each time. In this embodiment, the second capacitor array 212 is configured to include 5-bit capacitor pairs, and the logic control circuit 230 controls the capacitors in the second capacitor array 212 to sequentially flip. In the process of capacitor inversion, if the current comparison result da=1, the logic control circuit 230 switches the control signal of the P-terminal capacitor in the next comparison to the third control signal Gnd, and switches the control signal of the N-terminal capacitor to the second control signal Vref; if the current comparison result da=0, the logic control circuit 230 switches the control signal of the P-terminal capacitor in the next comparison to the second control signal Vref and switches the control signal of the N-terminal capacitor to the third control signal VGnd. After the conversion, the comparator 220 can output the signal DATA [5:1], which is the comparison digital signal. Since the first capacitor pair C1 at the lowest position in the first capacitor array 211 is not flipped during the voltage back-scaling stage, the difference between the comparison signal and the least significant bit of the reference digital signal is calculated, so as to obtain the incremental digital signal. The conversion result corresponding to the least significant bit of the reference digital signal is the code value D1 which is output by the comparator in the last comparison in the reference measuring stage. Therefore, subtracting D1 from DATA [5:1] by binary subtraction is the corresponding code value for the incremental measurement. The corresponding code value of the increment digital signal is DATA [5:1] -D [1].
It should be noted that, during the subsequent measurement period, the voltage increment may need to be measured repeatedly to ensure the measurement accuracy, and during the subsequent measurement period, since the control signal of the first capacitor array 211 is already the same as the reference measurement period, the inversion state of the capacitor in the first capacitor array 211 is already the same as the inversion state in the reference state, so that the control signal of the first capacitor array 211 may be kept unchanged, and only the capacitor in the second capacitor array 212 needs to be inverted for each subsequent measurement, thereby improving the response speed in the subsequent measurement.
In addition, the 12-bit SAR ADC needs to turn over the capacitor 11 times in the reference measurement stage and needs to turn over the capacitor 4 times in the increment measurement stage; compared with the traditional 12-bit SAR ADC which needs to be turned 11 times in the reference measurement stage and the increment measurement stage, the 12-bit SAR ADC obviously needs less clock control in the increment measurement stage, so that the response speed of the SAR ADC is improved, and the conversion rate is also improved.
The analog-to-digital converter provided by the embodiment of the application can be widely applied to the capacitor array overturning strategies such as an upper polar plate sampling capacitor structure, a lower polar plate sampling capacitor structure, a traditional capacitor array overturning strategy, a monotonic capacitor array overturning strategy and a split capacitor. The analog-to-digital converter has the advantages that a preset reference control signal is applied to each capacitor in the first capacitor array, so that the conversion result of the first capacitor array part is consistent with the reference digital signal, and the analog-to-digital converter converts the increment through the second capacitor array on the basis of the reference measured value when the equipment is in the reference state by only adjusting the control signal of the second capacitor array part when the comparator executes the comparison action, so that the capacitance state difference possibly occurring in the first capacitor array during the conversion period is avoided, the accuracy of the increment digital signal is ensured, and the conversion precision of the analog-to-digital converter is improved.
As shown in fig. 6, the embodiment of the present application further provides an analog-to-digital conversion method 300, and the method 300 can be applied to the analog-to-digital converter. The method comprises the following steps:
S1: the analog input signal is sampled and converted.
In this embodiment, the analog input signal is sampled and converted by the first capacitor array and the second capacitor array.
S2: and applying a preset reference control signal to each capacitor in the first capacitor array, and adjusting the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator.
In this embodiment, the reference control signal is a control signal applied to the first capacitor array during the generation of the reference digital signal and adjusted by the logic control circuit.
The analog-to-digital converter can convert with the first capacitor array in the reference measurement stage when the device is in the reference state, in the conversion process of the first capacitor array, the logic control circuit enables the capacitor to be turned over by adjusting the control signal of each capacitor in the first capacitor array, and after the conversion of the first capacitor array is completed, the logic control circuit can obtain a conversion result which is actually a digital sequence, namely a reference digital signal. The reference digital signal can reflect the adjustment of the control signal on each capacitor by the logic control circuit when the logic control circuit controls the capacitor in the first capacitor array to turn over, and the adjusted control signal is the reference control signal correspondingly applied by the logic control circuit when the comparator outputs the reference digital signal. .
S3: and outputting an increment digital signal according to the result of the comparison action and a preset reference digital signal.
In this embodiment, the reference digital signal is a conversion result of the analog-to-digital converter when the logic control circuit adjusts the control signal applied to the first capacitor array according to the comparison operation of the comparator after the capacitor array samples and converts the reference input signal. The increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal.
In the first capacitor array and the second capacitor array, the logic control circuit sequentially turns over the capacitors from high to low. When the first capacitor array is applied with a preset reference control signal, the logic control circuit can correspondingly directly acquire the conversion result of the first capacitor array, namely a pre-stored reference digital signal corresponding to the reference control signal, wherein the reference digital signal also represents a reference measurement value when the equipment is in a reference state. In the embodiment of the application, in the incremental measurement stage, since the first capacitor array is already applied with the preset reference control signal, when the analog-to-digital converter performs incremental measurement, the capacitors in the first capacitor array have the same overturning state as the capacitors in the reference state, and finally the capacitors in the second capacitor array are sequentially overturned from high to low. The inversion action of the second capacitor array at this time makes the conversion result of the second capacitor array represent the increment of the analog input signal sampled at present relative to the reference measurement value, namely the increment detection result based on the reference measurement value, namely the increment of the sampled analog input and signal relative to the reference input signal.
According to the analog-to-digital conversion method provided by the embodiment of the application, the conversion result of the first capacitor array part is consistent with the reference digital signal by applying the preset reference control signal to each capacitor in the first capacitor array, and the analog-to-digital converter converts the increment through the second capacitor array on the basis of the reference measured value when the device is in the reference state by only adjusting the control signal of the second capacitor array part when the comparator executes the comparison action, so that the capacitance state difference possibly occurring in the first capacitor array during the conversion period is avoided, the accuracy of the increment digital signal is ensured, and the conversion precision of the analog-to-digital converter is improved.
The present application is not limited in any way by the above preferred embodiments, and the present application has been disclosed in the above preferred embodiments, but is not limited thereto, and any person skilled in the art will appreciate that the present application can be realized without departing from the technical scope of the present application, while the above disclosure is directed to equivalent embodiments capable of being modified or altered in some ways, it is apparent that any modifications, equivalent variations and alterations made to the above embodiments according to the technical principles of the present application fall within the scope of the present application.
Claims (8)
1. An analog-to-digital converter, comprising:
The capacitive array is used for sampling and converting analog input signals and comprises a first capacitive array and a second capacitive array;
a comparator, an input end of the comparator is connected to the capacitor array, and the comparator is configured to perform a comparison action according to an input signal of the input end based on a control signal; and
The logic control circuit is connected with the comparator and the capacitor array, is configured to apply a preset reference control signal to each capacitor in the first capacitor array, adjusts the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator, and is further configured to output an incremental digital signal according to the result of the comparison action and the preset reference digital signal;
The logic control circuit is used for adjusting a conversion result of the analog-to-digital converter when the control signal applied to the first capacitor array is regulated according to the comparison action of the comparator after the reference digital signal is obtained by sampling and converting the reference input signal by the capacitor array; the reference control signal is a control signal which is applied to the first capacitor array during the generation period of the reference digital signal and is regulated by the logic control circuit; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal;
The logic control circuit is configured to set a control signal in the first capacitor array as the reference control signal according to the reference digital signal during the application of a preset reference control signal to each capacitor in the first capacitor array;
The logic control circuit is configured to maintain the control signal of each capacitor in the second capacitor array unchanged during the generation of the reference digital signal, and adjust the control signal applied to the first capacitor array in the current comparison operation according to the result of the last comparison operation of the comparator.
2. The analog-to-digital converter of claim 1, wherein said reference digital signal comprises a plurality of digital bits, wherein each of said digital bits corresponds to a result of a comparison action by said comparator.
3. An analog-to-digital converter as claimed in any one of claims 1 to 2, in which the logic control circuit is configured to generate a comparison digital signal according to the result of the comparison operation during the output of the increment digital signal, and perform a difference operation on the comparison digital signal and the least significant bit of the reference digital signal to output the increment digital signal.
4. The analog-to-digital converter of any one of claims 1-2, wherein the input of the comparator comprises a first input and a second input, the first capacitor array comprises M capacitor pairs, each capacitor pair comprises two capacitors with equal capacitance values, one capacitor is connected to the first input of the comparator, and the other capacitor is connected to the second input of the comparator;
The capacitance values of the first two capacitance pairs are equal, and the capacitance values of the third to Mth capacitance pairs are increased by the power of 2; wherein M is an integer greater than or equal to 1.
5. The analog-to-digital converter of claim 4, wherein said first capacitor array further comprises a pair of redundant capacitors disposed between any two of said pairs of M capacitors, said pair of redundant capacitors having a capacitance equal to a capacitance of a lower pair of adjacent pairs of two capacitors.
6. The analog-to-digital converter of any one of claims 1-2, wherein the second capacitor array comprises P-bit capacitor pairs, each capacitor pair comprising two capacitors having equal capacitance values, one capacitor being connected to the first input of the comparator and the other capacitor being connected to the second input of the comparator;
the capacitance values of the first two capacitor pairs are equal, and the capacitance values of the third capacitor to the P capacitor are increased by the power of 2; wherein P is an integer greater than or equal to 1.
7. An analog-to-digital converter as claimed in any one of claims 1 to 2, in which the number of capacitors in the second capacitor array is less than the number of capacitors in the first capacitor array.
8. An analog-to-digital conversion method applied to the analog-to-digital converter of any one of claims 1 to 7, comprising:
Sampling and converting an analog input signal;
applying a preset reference control signal to each capacitor in the first capacitor array, and adjusting the control signal applied to the second capacitor array in the current comparison action according to the result of the last comparison action of the comparator; and
Outputting an incremental digital signal according to the result of the comparison action and a preset reference digital signal; the reference digital signal is a conversion result of an analog-to-digital converter when the logic control circuit adjusts a control signal applied to the first capacitor array according to the comparison action of the comparator; the reference control signal is a control signal applied after the logic control circuit adjusts the control signal of the first capacitor array in the reference digital signal generation period; the increment digital signal is an increment detection result of the analog-to-digital converter based on the reference digital signal;
Setting a control signal in the first capacitor array as the reference control signal according to the reference digital signal during the application of a preset reference control signal to each capacitor in the first capacitor array;
and during the generation period of the reference digital signal, the control signal of each capacitor in the second capacitor array is kept unchanged, and the control signal applied to the first capacitor array in the current comparison action is adjusted according to the result of the last comparison action of the comparator.
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