CN111372318B

CN111372318B - Method and device for processing downlink control information

Info

Publication number: CN111372318B
Application number: CN202010172571.9A
Authority: CN
Inventors: 闫海停
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2020-03-12
Filing date: 2020-03-12
Publication date: 2023-04-07
Anticipated expiration: 2040-03-12
Also published as: CN111372318A

Abstract

The embodiment of the application provides a method and equipment for processing downlink control information, when UE detects that the number of DCI in a DCI set contained in a PDCCH is greater than a preset number threshold, corresponding DCI parsing tasks are respectively established on at least two target CPU kernels, and the corresponding DCI parsing tasks are respectively executed based on the target CPU kernels, wherein the DCI parsing tasks are respectively used for parsing the DCI in different DCI subsets of the DCI set. According to the method and the device, when the number of the DCI contained in the PDCCH is large, the time consumed by the UE for analyzing the DCI is effectively shortened, and the UE is further ensured to be capable of carrying out data transmission in time.

Description

Method and device for processing downlink control information

Technical Field

The embodiment of the present application relates to the field of communications technologies, and in particular, to a method and a device for processing Downlink Control Information (DCI).

Background

In a communication system, after being multiplexed by channels, DCI belonging to different User Equipments (UEs) are carried on a Physical Downlink Control Channel (PDCCH) together, and used for indicating scheduling information of an Uplink Physical Shared Channel (PUSCH) or a Physical Downlink Shared Channel (PDSCH) to each UE, so that each UE can transmit or receive data.

After detecting the PDCCH information, any UE needs to parse the DCI from the PDCCH, and because the UE does not know the format and location of the DCI, blind detection is required. Blind detection generally needs to be performed according to the number of Control Channel Elements (CCEs) available in a current slot (slot), the location of the CCEs, and a possible payload size (payload size) of the DCI, so that a certain time is required for the whole DCI analysis process.

At present, only after the DCI analysis is completed, the UE can transmit data according to the scheduling information indicated in the DCI of the UE, so if the number of DCI configured in the PDCCH is large, the UE inevitably consumes a long time when analyzing the DCI, and if the time point when the DCI analysis is completed is late, the UE may not be able to transmit data in time.

Disclosure of Invention

The embodiment of the application provides a method and equipment for processing downlink control information, which can solve the technical problem that in the prior art, when the number of DCIs configured in a PDCCH is large, time consumed for UE to perform DCI analysis is long.

In a first aspect, an embodiment of the present application provides a method for Processing downlink control information, where the method is applied to a UE, and the UE is provided with at least two Central Processing Unit (CPU) cores, and the method includes:

detecting a DCI set contained in the PDCCH;

when the number of DCIs in the DCI set is greater than a preset number threshold, respectively establishing corresponding DCI analysis tasks on at least two target CPU kernels; each DCI analysis task is used for analyzing DCI in different DCI subsets of the DCI set, and the union set of the DCI subsets corresponding to each DCI analysis task is the DCI set;

and executing the corresponding DCI analysis task based on the at least two target CPU kernels.

In one possible embodiment, the method further comprises:

after all target CPU kernels finish corresponding DCI analysis tasks, combining analysis results corresponding to the DCI analysis tasks to obtain analysis results corresponding to the DCI set;

and determining the target DCI corresponding to the UE according to the analysis result corresponding to the DCI set.

In a possible implementation manner, after all target CPU cores complete corresponding DCI parsing tasks, merging parsing results corresponding to each DCI parsing task includes:

when a first target CPU core completes a corresponding DCI analysis task, detecting whether the rest target CPU cores except the first target CPU core complete the corresponding DCI analysis task;

and when detecting that the rest target CPU kernels except the first target CPU kernel finish the corresponding DCI analysis tasks, combining analysis results corresponding to the DCI analysis tasks based on the first target CPU kernel.

In a possible implementation, the at least two target CPU cores are a first CPU core and a second CPU core; the respectively establishing corresponding DCI parsing tasks on at least two target CPU kernels comprises:

determining a first DCI subset and a second DCI subset in the DCI set, so as to establish a first DCI parsing task on the first CPU core and a second DCI parsing task on the second CPU core according to the first DCI subset and the second DCI subset;

the first DCI parsing task is used for parsing DCI in the first DCI subset, the second DCI parsing task is used for parsing DCI in the second DCI subset, and the union of the first DCI subset and the second DCI subset is the DCI set.

In one possible embodiment, when the number of DCIs in the DCI set is N, the determining the first DCI subset and the second DCI subset in the DCI set includes:

determining that the first DCI subset comprises M DCIs in the DCI set, and the second DCI subset comprises the rest DCIs in the DCI set except the M DCIs;

wherein M and N are both positive integers, and when N is an even number, M = N/2; when N is an odd number, M = (N-1)/2, or M = (N + 1)/2.

In a second aspect, an embodiment of the present application provides an apparatus for processing downlink control information, where the apparatus is applied to a UE, where the UE is provided with at least two CPU cores, and the apparatus includes:

a detection module, configured to detect a DCI set included in a PDCCH;

the processing module is used for respectively establishing corresponding DCI analysis tasks on at least two target CPU kernels when the number of DCIs in the DCI set is larger than a preset number threshold; each DCI analysis task is respectively used for analyzing DCI in different DCI subsets of the DCI set, and the union set of the DCI subsets corresponding to each DCI analysis task is the DCI set;

the processing module is further configured to execute the corresponding DCI parsing task based on the at least two target CPU cores.

In a possible implementation, the processing module is further configured to:

In a possible implementation, the processing module is further specifically configured to:

when a first target CPU kernel completes a corresponding DCI analysis task, detecting whether the rest target CPU kernels except the first target CPU kernel complete the corresponding DCI analysis task;

In a possible implementation, the at least two target CPU cores are a first CPU core and a second CPU core; the processing module is specifically configured to:

determining that the first DCI subset contains M DCIs in the DCI set, and the second DCI subset contains the remaining DCIs in the DCI set except the M DCIs;

In a third aspect, an embodiment of the present application provides a user equipment, including: at least one processor and a memory;

the memory stores computer execution instructions;

the at least one processor executes the computer-executable instructions stored by the memory, so that the at least one processor executes the method for processing the downlink control information provided in the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a computer-executable instruction is stored in the computer-readable storage medium, and when a processor executes the computer-executable instruction, the method for processing downlink control information as provided in the first aspect is implemented.

According to the method and the device for processing the downlink control information provided by the embodiment of the application, when the UE detects that the number of DCIs in a DCI set contained in a PDCCH is greater than a preset number threshold, corresponding DCI analysis tasks are respectively established on at least two target CPU kernels, and the corresponding DCI analysis tasks are respectively executed on the basis of the target CPU kernels, wherein the DCI analysis tasks are respectively used for analyzing the DCIs in different DCI subsets of the DCI set. According to the embodiment of the application, when the DCI number in the PDCCH is greater than the preset number threshold, the DCI in the PDCCH is divided into at least two DCI subsets, and then the DCI in the corresponding DCI subsets is analyzed in parallel based on at least two CPU cores, instead of analyzing based on a single CPU core, so that when the DCI number in the PDCCH is large, the time consumed by UE for analyzing the DCI can be effectively shortened, and the UE can be ensured to transmit data in time.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without inventive exercise.

Fig. 1 is a block diagram of a wireless communication system according to an embodiment of the present application;

fig. 2 is a first flowchart illustrating a method for processing downlink control information according to an embodiment of the present application;

fig. 3 is a flowchart illustrating a second method for processing downlink control information according to an embodiment of the present application;

fig. 4 is a third schematic flowchart of a method for processing downlink control information provided in an embodiment of the present application;

fig. 5 is a program module intent of a device for processing downlink control information provided in an embodiment of the present application;

fig. 6 is a schematic hardware structure diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort belong to the protection scope of the present application.

The embodiment of the application can be applied to various communication systems, such as: a Global System for Mobile communications (GSM) System, a Code Division Multiple Access (CDMA) System, a Wideband Code Division Multiple Access (WCDMA) System, a General Packet Radio Service (GPRS), a Long Term Evolution (Long Term Evolution, LTE) System, an Advanced Long Term Evolution (LTE-a) System, a New Radio (NR) System, an Evolution System of an NR System, an LTE (LTE-based Access to unlicensed spectrum, LTE-U) System on unlicensed spectrum, an NR (NR-based Access to unlicensed spectrum, UMTS (Universal Mobile telecommunications System), a Wireless Local Area Network (WLAN) System, a Wireless Local Area network (WiFi) System, or other Wireless Local Area communication systems.

Generally, conventional Communication systems support a limited number of connections and are easy to implement, however, with the development of Communication technologies, mobile Communication systems will support not only conventional Communication, but also, for example, device to Device (D2D) Communication, machine to Machine (M2M) Communication, machine Type Communication (MTC), and Vehicle to Vehicle (V2V) Communication, etc., and the embodiments of the present application can also be applied to these Communication systems.

Optionally, the communication system in the embodiment of the present application may be applied to a Carrier Aggregation (CA) scenario, may also be applied to a Dual Connectivity (DC) scenario, and may also be applied to an independent (SA) networking scenario.

The frequency spectrum of the application is not limited in the embodiment of the present application. For example, the embodiments of the present application may be applied to a licensed spectrum, and may also be applied to an unlicensed spectrum.

Referring to fig. 1, fig. 1 is a schematic diagram of an architecture of a wireless communication system according to an embodiment of the present disclosure. The wireless communication system provided by the present embodiment includes a UE101 and a network device 102.

Alternatively, the UE101 may refer to various forms of user equipment, access terminal, subscriber unit, subscriber station, mobile Station (MS), remote station, remote terminal, mobile device, terminal device (terminal equipment), wireless communication device, user agent, or user device. The UE may also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a Wireless Local Loop (WLL) station, a Personal Digital Assistant (PDA), a handheld device with a Wireless communication function, a computing device or other processing devices connected to a Wireless modem, a vehicle-mounted device, a wearable device, a terminal device in a future 5G Network, or a terminal device in a future evolved Public Land Mobile Network (PLMN), and the like, which is not limited in this embodiment of the application as long as the UE101 can wirelessly communicate with the Network device 102.

The UE101 is provided with at least two CPU cores, for example, the UE101 may be provided with a dual-core processor, a quad-core processor, an eight-core processor, and the like. Taking a dual-core processor as an example, the dual-core processor is a processor core that integrates two operation cores on one processor, that is, one processor based on a single semiconductor has two identical functions. Because the actual performance of the processor is the total number of instructions that the processor can process in each clock cycle, the number of executable units in each clock cycle of the processor is doubled every time one core is added, and the processing efficiency is doubled.

Optionally, the Network device 102, i.e. a public mobile communication Network device, is an interface device for the UE101 to Access the internet, and is also a form of a Radio Station, and refers to a Radio transceiver Station for performing information transmission with the UE101 in a certain Radio coverage area, and includes a Base Station (BS), which may also be referred to as a Base Station device, and is a device deployed in a Radio Access Network (RAN) to provide a wireless communication function. For example, a device providing a Base Station function in a 2G network includes a Base Transceiver Station (BTS), a device providing a Base Station function in a 3G network includes a node B (NodeB), a device providing a Base Station function in a 4G network includes an Evolved node B (eNB), and in a Wireless Local Area Network (WLAN), the device providing a Base Station function is an Access Point (AP), a device providing a Base Station function in a 5G NR, a gNB (ng-eNB) that continues to evolve, where the gNB and the UE communicate with each other by using an NR technology, and the ng-eNB and the UE communicate with each other by using an Evolved Universal Terrestrial Radio Access network (E-eNB) technology, and both the gNB and the ng-eNB may be connected to the 5G core network. The network device 102 in the embodiment of the present application also includes a device that provides a base station function in a future new communication system, and the like.

Optionally, the embodiment of the present application may be applied to various periodic services, and the network device may configure the periodic transmission resource for the UE in a Semi-Persistent Scheduling (SPS) or a Configured/pre-authorized (CG) manner.

Optionally, the embodiments of the present application may also be applied to aperiodic services.

In one possible implementation, the network device may send uplink scheduling information (UL Grant) to the UE through the DCI, indicating PUSCH transmission, in order for the UE to send data. Alternatively, the network device may also send downlink scheduling information (DL Grant) to the UE through the DCI to indicate PDSCH transmission, so that the UE receives data.

The transmission bandwidth of the PDCCH may simultaneously include DCI of multiple UEs, and before the UE receives or transmits service data, the UE needs to acquire the DCI belonging to the UE from the multiple DCIs included in the PDCCH.

For each UE, there are two Control Channel Element (CCE) search spaces carrying PDCCH, namely Common Search Space (CSS) and UE-specific search space (USS). The public search space mainly bears a PDCCH (physical Downlink control channel) for informing the UE of receiving the broadcast paging information, and all the UE is public; the UE-specific search space is allocated per UE, i.e. when a UE is scheduled, the PDCCH channel sent to it is only likely to be carried by the common search space or the CCEs belonging to its dedicated search space.

The UE knows which two DCI formats (a normal format and a fallback format) it needs to detect through the configuration of the transmission mode, but the UE does not know the aggregation level of the PDCCH carrying the DCI sent to the UE, nor the CCE starting position of the PDCCH carrying the DCI sent to the UE, so the UE generally needs to perform one-by-one blind detection on the search space by using the lengths of the two DCI formats that are already known, and if the UE detects that a Cyclic Redundancy Check (CRC) is scrambled by using a Radio Network Temporary Identifier (RNTI), the UE determines that the DCI corresponding to the Cyclic Redundancy Check is sent to the UE, and the UE obtains all fields of the corresponding DCI formats, thereby further analyzing the DCI content belonging to the UE.

At present, only after the DCI is resolved, the UE can transmit data according to the scheduling information indicated in the DCI of the UE, so that when the number of DCIs configured in the PDCCH by the network device is large, the UE is inevitable to consume a long time to resolve the DCIs. And because the starting time of the transmission resource indicated by the DCI is usually fixed, if the time point when the DCI analysis is completed is late, the UE may not be able to timely perform subsequent data transmission by using the transmission resource indicated by the DCI itself.

In order to solve the above technical problem, an embodiment of the present application provides a method for processing downlink control information, where when the number of DCIs in a DCI set included in a PDCCH is greater than a preset number threshold, corresponding DCI parsing tasks are respectively established on at least two target CPU cores, and then the target CPU cores respectively execute the corresponding DCI parsing tasks, where each DCI parsing task is used to parse the DCIs in different DCI subsets of the DCI set, so as to effectively shorten time consumed by a UE in DCI parsing. Please refer to the following embodiments of the present application:

referring to fig. 2, fig. 2 is a flowchart illustrating a method for processing downlink control information according to an embodiment of the present disclosure. As shown in fig. 2, the method includes:

s201, detecting a DCI set contained in the PDCCH.

It can be understood that the UE needs to know the DCI configured to the UE by the network device from the PDCCH before receiving or transmitting the traffic data. Because the transmission bandwidth of the PDCCH may include DCI of multiple UEs at the same time, when the UE needs to receive or transmit service data, it needs to detect a DCI set included in the PDCCH first, and then parse the DCI belonging to the UE from the detected DCI set, so as to receive or transmit the service data.

In the embodiment of the present application, when the UE needs to receive or transmit the service data, a DCI set composed of DCIs included in the PDCCH is detected, and the number of DCIs included in the DCI set is determined.

S202, when the number of DCIs in the DCI set is larger than a preset number threshold, respectively establishing corresponding DCI analysis tasks on at least two target CPU kernels; and the union set of the DCI subsets corresponding to each DCI analysis task is the DCI set.

It can be understood that after detecting a DCI set included in a PDCCH, a UE needs to parse DCI belonging to the UE from the DCI set, and since the UE does not know the format and location of the DCI, each DCI in the DCI set needs to be parsed. Therefore, when the number of the DCIs in the DCI set included in the PDCCH is larger, the UE traverses the entire DCI, and the time consumed by each parsing process is longer, so that the time for determining the DCI may be longer, and further, the UE may not timely perform subsequent data transmission by using the transmission resource indicated by the DCI.

In the embodiment of the application, in order to avoid the situation that the UE cannot timely utilize the transmission resource indicated by the DCI of the UE to perform data transmission due to the fact that the time for the UE to analyze the DCI is long when the number of DCIs contained in the PDCCH is large, when the number of the DCIs in the DCI set is larger than a preset number threshold, DCI analysis tasks are respectively established on at least two target CPU kernels, so that the DCI analysis tasks corresponding to the target CPU kernels can be correspondingly processed in parallel through the at least two target CPU kernels; and each DCI analysis task is respectively used for analyzing DCI in different DCI subsets of the DCI set.

For example, when the number of DCIs in the DCI set is greater than a preset number threshold, DCI parsing tasks are respectively established on two target CPU cores, where a DCI parsing task on a first target CPU core is used to parse DCI in a first DCI subset of the DCI set, and a DCI parsing task on a second target CPU core is used to parse DCI in a second DCI subset of the DCI set. The DCI in the first DCI subset may be a first half DCI in the DCI set, and the DCI in the second DCI subset may be a second half DCI in the DCI set.

Optionally, the preset number threshold may be determined according to a maximum parsing duration allowed when the UE parses the DCI, and an average duration consumed by the UE for parsing one DCI each time.

For example, the maximum analysis duration allowed by the UE when analyzing the DCI is a msec, and the average duration consumed by the UE when analyzing one DCI is b msec, the value of the preset number threshold k may be k = a/b; wherein k, a and b are positive integers.

And S203, executing a corresponding DCI analysis task based on the at least two target CPU kernels.

In the embodiment of the application, after the corresponding DCI parsing tasks are respectively established on at least two target CPU cores, each target CPU core synchronously starts to execute the corresponding DCI parsing task.

It can be understood that, assuming that the DCI set includes N DCIs, when a DCI analysis task of the N DCIs is established on one CPU core, it takes N milliseconds for one CPU core to complete the DCI analysis task; if the DCI parsing tasks of the N DCIs are averagely split into two DCI parsing tasks, that is, the DCI in the DCI subsets in the DCI parsing tasks are equal in number and are respectively established on the two CPU cores, each CPU core only needs to complete N/2 DCI parsing tasks, and thus each CPU core only needs N/2 milliseconds to complete its corresponding DCI parsing task. After the DCI analysis tasks of the N DCIs are split into two DCI analysis tasks and respectively established on the two CPU kernels, the time consumed in the whole DCI analysis process can be reduced by about 1/2.

For another example, if the DCI parsing task of the N DCIs is averagely split into four DCI parsing tasks and respectively established on four CPU cores, each CPU core only needs to complete N/4 DCI parsing tasks, and thus each CPU core only needs N/4 milliseconds to complete its corresponding DCI parsing task. Namely, after the DCI analysis tasks of the N DCIs are divided into four DCI analysis tasks and respectively established on four CPU cores, the time consumed in the whole DCI analysis process can be reduced by about 3/4.

It should be noted that the determination of the number of target CPU cores is determined not only by the number of DCIs in the DCI set, but also by the number of CPU cores of the UE itself.

According to the method for processing the downlink control information provided by the embodiment of the application, when the number of DCI contained in the PDCCH is greater than the preset number threshold, the DCI in the DCI set is divided into at least two DCI subsets, and then the DCI in the corresponding DCI subsets is analyzed in parallel based on at least two CPU cores, instead of analyzing based on a single CPU core, so that when the number of DCI contained in the PDCCH is large, the time consumed by UE for analyzing the DCI is effectively shortened, and the UE is further ensured to be capable of transmitting data in time.

Based on the content described in the foregoing embodiment, referring to fig. 3, fig. 3 is a schematic flow chart of a method for processing downlink control information according to an embodiment of the present application, where in another possible embodiment of the present application, the method for processing downlink control information includes:

s301, detecting a DCI set contained in the PDCCH.

S302, when the number of DCIs in the DCI set is larger than a preset number threshold, respectively establishing corresponding DCI analysis tasks on at least two target CPU kernels; and the union set of the DCI subsets corresponding to each DCI analysis task is the DCI set.

And S303, executing a corresponding DCI analysis task based on the at least two target CPU kernels.

The contents described in steps S301 to S303 are the same as the contents described in steps S201 to S203, and specific reference may be made to the description in the above embodiment, which is not repeated herein.

And S304, after all target CPU kernels finish the corresponding DCI analysis tasks, combining the analysis results corresponding to the DCI analysis tasks to obtain the analysis results corresponding to the DCI set.

S305, determining the target DCI corresponding to the UE according to the analysis result corresponding to the DCI set.

In the embodiment of the application, when each target CPU core executes a corresponding DCI analysis task, each analysis result is stored in a storage space corresponding to each target CPU core.

For example, when there are two target CPU cores, a sufficiently large storage space is determined, and then the parsing result corresponding to the first target CPU core is written from the start bit of the storage space, and the parsing result corresponding to the second target CPU core is written from the middle position of the storage space, so that it can be ensured that the parsing result of one target CPU core is not overwritten or overwritten by the parsing result of the other target CPU core in the parallel processing process of the two target CPU cores.

And after all target CPU kernels finish the corresponding DCI analysis tasks, combining the analysis results corresponding to all the target CPU kernels in the storage space to obtain the analysis results corresponding to the DCI set, and determining the target DCI corresponding to the UE according to the analysis results, so that the UE can perform data transmission in time after quickly confirming the target DCI.

Optionally, in a feasible implementation manner, after all target CPU cores complete corresponding DCI parsing tasks in step S304, merging parsing results corresponding to each DCI parsing task, specifically includes:

and when the first target CPU core completes the corresponding DCI analysis task, detecting whether the rest target CPU cores except the first target CPU core complete the corresponding DCI analysis task.

And when detecting that the rest target CPU kernels except the first target CPU kernel complete the corresponding DCI analysis tasks, combining analysis results corresponding to the DCI analysis tasks based on the first target CPU kernel.

It should be noted that DCI in the DCI set may not be evenly distributed to each DCI parsing task, that is, the establishment of the DCI parsing task may consider not only the number of DCIs in the DCI set but also the performance currently processed by each CPU in the UE (possibly, a current part of CPUs are processing other tasks). Similarly, for the determined target CPU core and each DCI parsing task, when the DCI parsing task is processed, the time for each target DCI core to process the corresponding DCI parsing task may be different due to different DCI numbers in the DCI parsing tasks and/or different performance of the target CPU cores, based on which, the target CPU core that has been processed first needs to wait for other target CPU cores that are still processing the corresponding DCI parsing task, and after detecting that all processing is completed, the target CPU core that has been processed last merges parsing results corresponding to each DCI parsing task.

In addition, further optionally, after each target CPU core completes the corresponding DCI parsing task, an operation end flag may be automatically generated. Any target CPU core can determine whether other target CPU cores finish the corresponding DCI analysis tasks by detecting whether the operation ending mark is generated in the DCI analysis tasks corresponding to other target CPU cores.

In the embodiment of the application, when any target CPU core completes the corresponding DCI analysis task, whether other target CPU cores complete the corresponding DCI analysis task or not is detected, and if the other target CPU cores complete the corresponding DCI analysis task, the analysis results corresponding to the DCI analysis tasks are combined based on the target CPU core; and if the target CPU kernels which do not finish the corresponding DCI analysis tasks exist in other target CPU kernels, the DCI analysis tasks on the target CPU kernels are finished.

In the embodiment of the application, after all target CPU cores complete corresponding DCI parsing tasks, parsing results corresponding to the DCI sets can be accurately obtained by combining parsing results corresponding to the DCI parsing tasks, and then target DCI corresponding to the UE can be accurately determined according to the parsing results.

In another possible embodiment of the present application, it is assumed that the UE is provided with a first CPU core and a second CPU core. When the UE detects that the number of DCIs in a DCI set included in the PDCCH is greater than a preset number threshold, it may determine a first DCI subset and a second DCI subset in the DCI set, so as to establish a first DCI parsing task on the first CPU core and a second DCI parsing task on the second CPU core according to the first DCI subset and the second DCI subset.

The first DCI analysis task is used for analyzing DCI in the first DCI subset, the second DCI analysis task is used for analyzing DCI in the second DCI subset, and the union set of the first DCI subset and the second DCI subset is a DCI set.

Optionally, it is determined that the first DCI subset includes M DCIs in the DCI set, and the second DCI subset includes remaining DCIs in the DCI set except for the M DCIs; wherein M and N are both positive integers, and when N is an even number, M = N/2; when N is an odd number, M = (N-1)/2, or M = (N + 1)/2.

For example, the first DCI subset includes first M DCIs in the DCI set, and the second DCI subset includes remaining DCIs in the DCI set except for the M DCIs.

In the embodiment of the present application, since the number of DCIs included in the first DCI subset is substantially the same as the number of DCIs included in the second DCI subset, the time for each target CPU core to complete a DCI analysis task can also be substantially the same, so that the time consumed by the UE in analyzing the DCI can be reduced to the greatest extent.

Based on the content described in the foregoing embodiment, in order to better understand the embodiments of the present application, referring to fig. 4, fig. 4 is a third schematic flow chart of a method for processing downlink control information provided in the embodiments of the present application, in another possible embodiment of the present application, it is assumed that a UE is provided with a first CPU core and a second CPU core, and the method for processing downlink control information includes:

s401, a DCI set contained in the PDCCH is detected.

S402, establishing a first DCI parsing TASK TASK1 on a first CPU core.

S403, determining whether the number of DCIs in the DCI set is greater than a preset number threshold by TASK1, and if not, continuing to execute the step S404; if yes, go to step S406.

And S404, executing the TASK1 based on the first CPU kernel to obtain an analysis result.

And S405, determining the target DCI corresponding to the UE according to the analysis result.

S406, the TASK1 establishes a new DCI parsing TASK TASK2 on the first CPU core, and analyzing the DCI in the first DCI subset based on the first CPU core, and establishing a second DCI analysis TASK TASK3 on the second CPU core.

And S407, executing the TASK3 based on the second CPU core to analyze the DCI in the second DCI subset.

Wherein, S406 and S407 can be executed synchronously. And the union of the first DCI subset and the second DCI subset is the DCI set.

S408, determining whether the TASK3 is finished or not when the TASK2 is finished, and if yes, continuing to execute the step S409; if not, the TASK2 ends execution.

S409 and TASK2 combine the analysis results corresponding to TASK2 and TASK3, and return to execute step S405.

S4010, determining whether the TASK2 is finished when the TASK3 is finished, if yes, continuing to execute the step S4011; if not, the TASK3 ends execution.

S4011 and TASK3 combine the analysis results corresponding to TASK2 and TASK3, and return to execute step S405.

Step S408 and step S4010 may be executed synchronously.

In the embodiment of the application, when the number of DCI contained in the PDCCH is greater than the preset number threshold, the DCI in the DCI set is divided into two DCI subsets, and then the DCI in the corresponding DCI subsets is analyzed in parallel based on the two CPU cores, rather than being analyzed based on a single CPU core, so that when the number of the DCI contained in the PDCCH is large, the time consumed by the UE for analyzing the DCI is effectively shortened, and the UE is further ensured to transmit data in time.

Based on the content described in the foregoing embodiment, an apparatus for processing downlink control information is further provided in this embodiment, and is applied to a UE, with reference to fig. 5, fig. 5 is a schematic diagram of program modules of the apparatus for processing downlink control information provided in this embodiment, where the apparatus 50 for processing downlink control information includes: a detection module 501 and a processing module 502. Wherein: a detecting module 501, configured to detect a DCI set included in a PDCCH. A processing module 502, configured to respectively establish corresponding DCI parsing tasks on at least two target CPU cores when the number of DCIs in the DCI set is greater than a preset number threshold; and the joint set of the DCI subsets corresponding to each DCI analysis task is the DCI set. The processing module 502 is further configured to execute a corresponding DCI parsing task based on the at least two target CPU cores.

In the apparatus 50 for processing downlink control information provided in this embodiment, when the DCI number included in the PDCCH is greater than the preset number threshold, the DCI in the DCI set is divided into at least two DCI subsets, and then the DCI in the corresponding DCI subset is analyzed in parallel based on at least two CPU cores, instead of analyzing based on a single CPU core, so that when the DCI number included in the PDCCH is large, time consumed by the UE in analyzing the DCI is effectively shortened, and the UE is further enabled to perform data transmission in time.

Optionally, the processing module 502 is further configured to:

after all target CPU kernels finish corresponding DCI analysis tasks, combining analysis results corresponding to the DCI analysis tasks to obtain analysis results corresponding to the DCI set; and determining the target DCI corresponding to the UE according to the analysis result corresponding to the DCI set.

Optionally, the processing module 502 is further specifically configured to:

when a first target CPU core completes a corresponding DCI analysis task, detecting whether the rest target CPU cores except the first target CPU core complete the corresponding DCI analysis task; and when detecting that the rest target CPU kernels except the first target CPU kernel finish the corresponding DCI analysis tasks, combining analysis results corresponding to the DCI analysis tasks based on the first target CPU kernel.

In the processing device 50 for downlink control information provided in this embodiment, after all target CPU cores complete corresponding DCI parsing tasks, by combining parsing results corresponding to each DCI parsing task, a parsing result corresponding to the DCI set may be accurately obtained, and then a target DCI corresponding to the UE may be accurately determined according to the parsing result.

Optionally, the at least two target CPU cores are a first CPU core and a second CPU core; the processing module 502 is specifically configured to:

determining a first DCI subset and a second DCI subset in the DCI set, so as to establish a first DCI parsing task on the first CPU core and a second DCI parsing task on the second CPU core according to the first DCI subset and the second DCI subset; the first DCI parsing task is used for parsing DCI in the first DCI subset, the second DCI parsing task is used for parsing DCI in the second DCI subset, and a union of the first DCI subset and the second DCI subset is the DCI set.

Optionally, the processing module is specifically further configured to:

determining that the first DCI subset comprises M DCIs in the DCI set, and the second DCI subset comprises the rest DCIs in the DCI set except the M DCIs; wherein M and N are both positive integers, and when N is an even number, M = N/2; when N is an odd number, M = (N-1)/2, or M = (N + 1)/2.

In the apparatus 50 for processing downlink control information provided in this embodiment, since the number of DCIs included in the first DCI subset is substantially the same as the number of DCIs included in the second DCI subset, the time for each target CPU core to complete a DCI analysis task can also be substantially the same, so that the time consumed by the UE to analyze DCI can be shortened to the greatest extent.

It can be understood that the implementation principle and the implementation manner of the apparatus 50 for processing downlink control information are the same as those of the method for processing downlink control information described in fig. 2, and reference may be made to the description of each embodiment of the method for processing downlink control information applied to the UE, and details are not repeated here.

Further, based on the content described in the foregoing embodiments, an embodiment of the present application also provides a user equipment, where the user equipment includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes computer-executable instructions stored in the memory to implement the content described in the embodiments of the method for processing downlink control information applied to the UE.

The user equipment provided in this embodiment may be configured to execute the technical solution of the method embodiment, and the implementation principle and the technical effect are similar, which are not described herein again.

For better understanding of the embodiment of the present application, referring to fig. 6, fig. 6 is a schematic diagram of a hardware structure of an electronic device provided in the embodiment of the present application. The electronic device may be the user device described above.

As shown in fig. 6, the electronic device 60 of the present embodiment includes: a processor 601 and a memory 602; wherein

A memory 602 for storing computer-executable instructions;

the processor 601 is configured to execute the computer executable instructions stored in the memory to implement the steps performed by the user equipment in the above embodiments.

Alternatively, the processor 601 is configured to execute computer-executable instructions stored in the memory to implement the steps performed by the network device in the foregoing embodiments.

Reference may be made in particular to the description relating to the method embodiments described above.

Alternatively, the memory 602 may be separate or integrated with the processor 601.

When the memory 602 is provided separately, the device further comprises a bus 603 for connecting said memory 602 and the processor 601.

Embodiments of the present application further provide a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when a processor executes the computer-executable instructions, the steps performed by the user equipment in the above embodiments are implemented.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, functional modules in the embodiments of the present application may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware mode, and can also be realized in a mode of hardware and a software functional unit.

The integrated module implemented in the form of a software functional module may be stored in a computer-readable storage medium. The software functional module is stored in a storage medium and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device) or a processor (processor) to execute some steps of the methods according to the embodiments of the present application.

It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in the incorporated application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in the processor.

The memory may comprise a high speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one magnetic disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, or the like.

The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.

The storage medium may be implemented by any type or combination of volatile and non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the storage medium may reside as discrete components in an electronic device or host device.

Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for processing downlink control information is applied to User Equipment (UE), wherein the UE is provided with at least two Central Processing Unit (CPU) cores, and the method comprises the following steps:

detecting a Downlink Control Information (DCI) set contained in a downlink control channel (PDCCH);

when the number of DCIs in the DCI set is greater than a preset number threshold, respectively establishing corresponding DCI analysis tasks on at least two target CPU kernels; each DCI analysis task is respectively used for analyzing DCI in different DCI subsets of the DCI set, and the union set of the DCI subsets corresponding to each DCI analysis task is the DCI set;

executing the corresponding DCI analysis task based on the at least two target CPU kernels;

2. The method of claim 1, wherein the at least two target CPU cores are a first CPU core and a second CPU core; the establishing of the corresponding DCI parsing tasks on the at least two target CPU kernels respectively comprises the following steps:

the first DCI parsing task is used for parsing DCI in the first DCI subset, the second DCI parsing task is used for parsing DCI in the second DCI subset, and a union of the first DCI subset and the second DCI subset is the DCI set.

3. The method of claim 2, wherein when the number of DCIs in the set of DCIs is N, the determining the first subset of DCIs and the second subset of DCIs in the set of DCIs comprises:

4. A processing device of downlink control information is applied to User Equipment (UE), wherein at least two Central Processing Unit (CPU) kernels are arranged in the UE, and the device comprises:

a detection module, configured to detect a downlink control information DCI set included in a downlink control channel PDCCH;

the processing module is further configured to execute the corresponding DCI parsing task based on the at least two target CPU cores;

the processing module is specifically further configured to:

5. The apparatus of claim 4, wherein the at least two target CPU cores are a first CPU core and a second CPU core; the processing module is specifically configured to:

6. The apparatus of claim 5, wherein when the number of DCIs in the DCI set is N, the processing module is further specifically configured to:

7. A user device, comprising: at least one processor and a memory;

the memory stores computer-executable instructions;

the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the method of processing downlink control information according to any one of claims 1 to 3.

8. A computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the method for processing downlink control information according to any one of claims 1 to 3 is implemented.