CN111370038B - Circuit for controlling voltage of drain terminal - Google Patents
Circuit for controlling voltage of drain terminal Download PDFInfo
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- CN111370038B CN111370038B CN201811595589.9A CN201811595589A CN111370038B CN 111370038 B CN111370038 B CN 111370038B CN 201811595589 A CN201811595589 A CN 201811595589A CN 111370038 B CN111370038 B CN 111370038B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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Abstract
The invention relates to a circuit for controlling the voltage of a drain terminal, which relates to the field of nonvolatile memories and comprises: the leakage end charge pump module is respectively connected with the comparison voltage module, the filtering regulation module and the modulation voltage module, the comparison voltage module is respectively connected with the leakage end charge pump module and the filtering regulation module, the filtering regulation module is respectively connected with the leakage end charge pump module, the comparison voltage module and the modulation voltage module, and the modulation voltage module is respectively connected with the filtering regulation module and the leakage end charge pump module. According to the circuit for controlling the voltage of the drain terminal, the PMOS tube is conducted in the interval time of the write operation switching, the input voltage of the clock circuit is increased, the frequency of the clock circuit is reduced, and therefore the purposes that the voltage of the drain terminal does not continue to be pumped and the current voltage is kept are achieved.
Description
Technical Field
The invention relates to the field of nonvolatile memories, in particular to a circuit for controlling drain terminal voltage.
Background
Currently, the nonvolatile memory is basically provided with a working voltage meeting the operation requirement by a charge pump, the charge pump is a switched capacitor voltage converter, the direct current converter which utilizes a so-called 'fast' or 'pumping' capacitor instead of an inductor or a transformer to store energy can increase or decrease the input power voltage, and can also be used for generating negative voltage, and a MOS switch array in the direct current converter can control the charging and discharging of the fast capacitor in a certain mode, so that the input voltage is multiplied or decreased by a certain factor (1/2,2 or 3) to obtain the required output voltage.
In the prior art, a programming operation is performed on a nonvolatile memory, that is, a write operation is performed on a memory array cell in the nonvolatile memory, and the write operation is performed on the memory array cell by applying a voltage (for example, 4V) to a drain terminal and applying a high voltage (for example, 9V) to a gate control terminal of each memory cell in the memory array cell, and the voltage applied to the drain terminal is generated by a charge pump circuit, which supplies a voltage to the memory array cell to be written, thereby generating a current.
The charge pump circuit of the existing nonvolatile memory is shown as figure 1 in the attached drawing of the specification, and the working principle is as follows: when the nonvolatile memory is programmed, the output voltage VOUT of the charge pump circuit 13 is connected in series through the resistor R0 and the resistor R1 to generate the comparison voltage V1 as the "+" input terminal of the voltage comparator 10, the reference voltage Vref is used as the "-" input terminal, the voltage V1 is initially smaller than the Vref voltage, according to the characteristics of the voltage comparator 10, the output voltage is low, the voltage is filtered by the filter adjusting circuit 11 to generate the relatively stable voltage Vp, the filter adjusting circuit includes the resistor R3 and the capacitor C1, wherein one end of the capacitor C1 is connected to the output terminal of the charge pump circuit 13, the voltage Vp is used as the trigger voltage of the clock circuit 12, since the voltage Vp is low, the frequency of the clock circuit 12 is high, the frequency is higher, the voltage VOUT output by the charge pump circuit 13 can reach a higher value rapidly, the comparison voltage V1 also rises gradually with the gradual rise of VOUT, the output of the voltage comparator 10 also rises gradually, the voltage Vp also gradually increases, so that the frequency of the clock circuit 12 becomes lower, which causes the output voltage VOUT of the charge pump 13 to increase slowly, when the VOUT voltage increases to a voltage that meets the drain requirement of the memory cell 14 for programming operation, V1 is greater than Vref, and due to the slew rate limitation of the voltage comparator 10 itself, the response to the V1 voltage cannot meet the rate of switching the memory cell operation, so that the value of the voltage Vp increases to the maximum value after a certain time, although the VOUT charge is discharged by the resistors connected in series with R0, R1 and R2, the discharge current is extremely small, so that the VOUT voltage does not decrease quickly, therefore the voltage Vp often reaches the maximum value yet, the programming operation of the next memory cell is already performed, and if the current value required by the next memory cell for programming is smaller than the previous one, but the VOUT voltage value does not yet decrease to the corresponding voltage value, in this case, the damage to the memory cell is large, and weak write effect is caused, which may seriously affect the reliability of the memory cell in the nonvolatile memory.
The existing method for inhibiting voltage overshoot of a drain terminal during writing operation by continuous switching is as follows: the first is that increasing the capacitor C3 inevitably leads to an increase in area, which is not favorable for the requirement of reducing cost in the industry, and the larger the capacitor C3, the easier the misoperation is, i.e. the oversensitivity makes the clock change too fast, which leads to too large jitter of the output voltage of the charge pump, and on the contrary, the voltage is unstable when writing the array unit, and the speed of the comparator inevitably increases the current, which is also not preferable, and even if the current is increased, the comparator also has a response speed limit, so the two methods can not solve the problem of voltage overshoot of the drain terminal during the address writing operation of the continuously switched address.
Disclosure of Invention
In view of the above problems, the present invention provides a circuit for controlling drain voltage, which solves the problem of overshoot of drain voltage during the continuous address-switching write operation in the prior art.
The embodiment of the invention provides a circuit for controlling drain terminal voltage, which comprises:
the device comprises a drain terminal charge pump module, a comparison voltage module, a filtering regulation module and a modulation voltage module;
the drain terminal charge pump module is respectively connected with the comparison voltage module, the filtering regulation module and the modulation voltage module and is used for generating drain terminal voltage;
the comparison voltage module is respectively connected with the drain terminal charge pump module and the filtering regulation module and is used for providing input voltage for the filtering regulation circuit;
the filtering adjusting module is respectively connected with the drain terminal charge pump module, the comparison voltage module and the modulation voltage module, and is used for responding to the change of the drain terminal voltage to adjust the frequency of a clock circuit in the drain terminal charge pump module and transmitting the output voltage of the comparison voltage module to the clock circuit after filtering;
and the modulation voltage module is respectively connected with the filtering regulation module and the drain terminal charge pump module and is used for controlling the drain terminal voltage output by the drain terminal charge pump module.
Optionally, the drain-side voltage charge pump module includes: a clock circuit and a charge pump;
the output end of the clock circuit is connected with the input end of the charge pump and is used for providing a clock signal for the charge pump;
and the output end of the charge pump is connected with the storage unit and used for providing a drain end voltage for the storage unit.
Optionally, the circuit for controlling the drain terminal voltage is applied to a memory, and the memory further comprises a control module;
the control module is connected with the modulation voltage module and used for sending a work enabling signal and a programming operation enabling signal to the control modulation voltage module, and the work enabling signal and the programming operation enabling signal are used for controlling the modulation voltage module to increase the output voltage of the voltage comparator.
Optionally, the comparing voltage module includes: a voltage comparator and a comparison voltage circuit;
the voltage comparator comprises a reference voltage connecting end, a comparison voltage connecting end and an output end;
the reference voltage connection end is connected with reference voltage, the comparison voltage connection end is connected with the comparison voltage circuit, and the output end of the voltage comparator is connected with the input end of the filtering regulation module and used for providing input voltage for the filtering regulation module;
the comparison voltage circuit is connected with a comparison voltage connecting end of the voltage comparator, is used for detecting the output voltage of the charge pump, is compared with the reference voltage, and provides comparison voltage for the voltage comparator;
the voltage comparison circuit comprises a first resistor, a second resistor and a third resistor, the three resistors are connected in series, the first end of the first resistor is connected with the output end of the drain terminal charge pump module, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is connected with the comparison voltage connecting end of the voltage comparator and the first end of the third resistor, and the second end of the third resistor is grounded.
Optionally, the filtering adjustment module includes: a first capacitor and a fourth resistor;
the first end of the first capacitor is connected with the output end of the drain terminal charge pump module, and the second end of the first capacitor is respectively connected with the first end of the fourth resistor and the modulation voltage module;
and the second end of the fourth resistor is connected with the output end of the voltage comparator.
Optionally, the modulation voltage module includes: the delay circuit comprises a first NAND gate, a first inverter, a second inverter, a first NOR gate, a PMOS (P-channel metal oxide semiconductor) tube and a delay inverter module;
the two input signals of the first NAND gate are the work enabling signal and the programming operation enabling signal respectively;
the output end of the first NAND gate is connected with the input end of the first inverter;
the output end of the first inverter is respectively connected with one input end of the first NOR gate and the input end of the delay inverter module;
the output end of the delay phase inverter module is connected with the input end of the first NOR gate;
the output end of the first NOR gate is connected with the input end of the second inverter;
the output end of the second inverter is connected with the grid electrode of the PMOS tube;
the source electrode of the PMOS tube is connected with a power supply;
and the drain electrode of the PMOS tube is connected with the filtering regulation module and the clock circuit respectively, and the drain electrode of the PMOS tube is the output end of the modulation voltage module.
Optionally, the delay inverter module comprises: the odd inverters are connected in series and used for generating any delay time, so that the conduction time of the PMOS tube is less than or equal to the time from the end of the first programming operation to the start of the second programming operation;
the input end of a third inverter in the odd inverters is connected with the output end of the first inverter;
the output end of the odd number of inverters in series combination is connected with the input end of the first NOR gate.
Optionally, the control module sends a high-level working enable signal and a programming operation enable signal to the modulation voltage module within a first programming operation time, and the working enable signal and the programming operation enable signal cause the PMOS transistor to be turned off within the first programming operation time;
the control module sends a high-level work enabling signal and a low-level programming operation enabling signal to the modulation voltage module within the time from the end of a first programming operation to the start of a second programming operation, and the work enabling signal and the programming operation enabling signal enable the PMOS tube to be conducted within the time from the end of the first programming operation to the start of the second programming operation;
and the control module sends a high-level work enabling signal and a programming operation enabling signal to the modulation voltage module within a second programming operation time, and the work enabling signal and the programming operation enabling signal enable the PMOS tube to be turned off within a second programming operation period.
Compared with the prior art, the circuit for controlling the drain voltage provided by the invention has the advantages that when the address writing operation is continuously switched on the nonvolatile memory, the modulation voltage module controls the drain voltage to be increased in the operation switching interval time according to the enable signal and the programming operation enable signal, the drain voltage is increased, the frequency of a clock circuit in the drain voltage charge pump module is reduced due to the increase of the drain voltage, the output of a charge pump is reduced, the purposes that the drain voltage does not continue to be pumped and the current voltage is kept are achieved, the circuit is simple in structure, fewer electric elements are used, and the volume of the nonvolatile memory is not additionally increased.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a circuit diagram of a prior art drain-side voltage charge pump;
FIG. 2 is a block diagram of a drain-side voltage control circuit according to the present invention;
FIG. 3 is a circuit diagram for controlling the drain terminal voltage according to the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the invention, but do not limit the invention to only some, but not all embodiments.
Referring to fig. 2, a schematic diagram of a module of a drain terminal voltage control circuit is shown, which may specifically include:
a drain voltage charge pump module 20, a modulation voltage module 30, a comparison voltage module 40, and a filtering adjustment module 50.
The drain voltage charge pump module 20 is respectively connected to the comparison voltage module 40, the filtering adjustment module 50, and the modulation voltage module 30, and the drain voltage charge pump module 20 is configured to provide a working voltage for a load.
The comparison voltage module 40 is connected to the drain charge pump module 20 and the filtering adjustment module 50, respectively, and is configured to provide an input voltage for the filtering adjustment circuit 30.
The filtering and adjusting module 50 is respectively connected to the drain charge pump module 20, the comparison voltage module 40, and the modulation voltage module 30, and is configured to adjust the frequency of the clock circuit in the drain charge pump module 20 in response to the change of the drain voltage, and to transmit the filtered output voltage of the comparison voltage module 40 to the clock circuit.
The modulation voltage module 30 is respectively connected to the filtering adjustment module 50 and the drain charge pump module 20, and is configured to control the drain voltage output by the drain charge pump module 20.
Alternatively, referring to fig. 3, the drain voltage charge pump module 20 in the circuit of the present invention includes: the load of the memory cell 70 is the load of the clock circuit 201, the charge pump 202, and the drain voltage charge pump module.
The input end of the clock circuit 201 is connected with the filtering adjusting module 50, and the output end of the clock circuit 201 is connected with the input end of the charge pump 202, and is used for providing a clock signal for the charge pump 202.
The charge pump 202 may output a voltage according to the clock signal of the clock circuit 201 to provide the drain voltage for the memory cell 70.
Optionally, referring to fig. 3, the comparing voltage module 40 in the circuit of the present invention includes: a voltage comparator 401 and a comparison voltage circuit 402.
The voltage comparator 401 comprises a reference voltage connection end, a comparison voltage connection end and an output end, wherein the reference voltage connection end is connected with a reference voltage Vref, the comparison voltage connection end is connected with a comparison voltage circuit 402, the output end of the voltage comparator 401 is respectively connected with the input end of the filtering and adjusting module 50 and the modulation voltage module 30 and is used for providing a trigger voltage Vp for the clock circuit 201, the trigger voltage Vp is the voltage of the voltage comparator 401 after the voltage is filtered by the filtering and adjusting module 50, and the voltage output by the voltage comparator 401 changes between a power supply voltage and a grounding voltage.
The comparison voltage circuit 402 includes a first resistor R0, a second resistor R1, and a third resistor R2, which are connected in series, a first end of the first resistor R0 is connected to the output terminal of the charge pump 202, a second end of the first resistor R1 is connected to the first end of the second resistor R1, a second end of the third resistor R2 and a comparison voltage connection terminal of the voltage comparator 401 are respectively connected to the first end of the third resistor R2, a second end of the third resistor R2 is grounded, the comparison voltage circuit 402 is configured to detect an output voltage of the charge pump 202, provide the comparison voltage to the voltage comparator 401, and further configured to quickly discharge the output voltage VOUT when the charge pump 202 stops operating.
Optionally, referring to fig. 3, the circuit of the present invention is applied to a nonvolatile memory, the memory has a control module 60, the control module 60 is connected to the modulation voltage module 30, and the control module 60 is configured to send an operation enable signal EN and a programming operation enable signal WR _ EN to the modulation voltage module 30, where the operation enable signal and the programming operation enable signal are used to control the modulation voltage module 30 to increase the output voltage of the voltage comparator 401.
Alternatively, referring to fig. 3, the filtering adjustment module 50 in the circuit of the present invention includes: a first capacitor C1 and a fourth resistor R3.
The first end of the first capacitor C1 is connected to the output end of the charge pump 202, the second end of the first capacitor C1 is connected to the first end of the fourth resistor R2 and the modulation voltage module 30, and the second end of the fourth resistor R2 is connected to the output end of the voltage comparator 401.
Alternatively, referring to fig. 3, the modulation voltage module 30 in the circuit of the present invention includes: the delay circuit comprises a first NAND gate nand1, a first NOR gate nor1, a first inverter inv1, a second inverter inv2, a PMOS tube 301 and a delay inverter module 302.
Two input signals of the first nand gate nand1 are respectively an operation enable signal EN and a programming operation enable signal WR _ EN, an output end of the first nand gate nand1 is connected with an input end of the first inverter inv1, an output end of the first inverter inv1 is respectively connected with one input end of the first nor gate nor1 and an input end of the delay inverter module 302, an output end of the delay inverter module 302 is connected with an input end of the first nor gate nor1, an output end of the first nor gate nor1 is connected with an input end of the second inverter inv2, an output end of the second inverter inv2 is connected with a gate of the PMOS transistor 301, a source of the PMOS transistor 301 is connected with a power supply, a drain of the PMOS transistor 301 is respectively connected with the filtering and adjusting module 50 and the clock circuit 202, and a drain of the PMOS transistor 301 is an output end of the modulating voltage module 30.
The delay inverter module 302 may include an odd number of inverters, wherein the odd number of inverters are connected in series, one end of the odd number of inverters is connected to the first inverter, and the other end of the odd number of inverters is connected to the output end of the first nor gate, so as to generate any delay time, and the required delay time may be adjusted according to the number of the inverters. The voltage modulation module in the above embodiments may also be composed of circuits formed by other electrical components, and the embodiments of the present invention are not limited thereto, and any circuit that can achieve the above functions falls within the scope of the present invention.
When programming operation is performed on the nonvolatile memory, generally, addresses are continuously switched, and writing operation is performed on memory cells of different addresses, when programming is started, when the memory cell of the first address is programmed from the beginning to the end, the operation enable signal EN is always at a high level, the programming operation enable signal WR _ EN changes from a low level to a high level, the PMOS transistor 301 in the modulation voltage module 30 is in an off state at this time, and the voltage Vp is the voltage filtered by the voltage comparator 401 through the filtering regulation module 50.
During the time from the programming of the memory cell at the first address to the programming of the memory cell at the second address, the operation enable signal EN is always at a high level, the programming operation enable signal WR _ EN changes from the high level to a low level, the PMOS transistor 301 in the modulation voltage module 30 is in a conducting state during the time due to the delay effect of the delay inverter module 302, the delay time can be adjusted according to the number of inverters in the delay inverter module 302, so that the delay time is equal to the time from the programming of the memory cell at the first address to the programming of the memory cell at the second address, and the voltage value of Vp floats between the power voltage minus the threshold voltage of the PMOS transistor 301, that is, the voltage of Vp is increased during the time, and the voltage of Vp is increased, so that the frequency of the clock circuit 201 is lowered, and the output voltage VOUT of the charge pump 202 is lowered, i.e., without overshooting the drain voltage of the memory cell 70, and without causing a weak write effect.
When the programming of the memory cell at the second address starts to the programming of the memory cell at the second address ends, the operation enable signal EN is always at a high level, the programming operation enable signal WR _ EN changes from a low level to a high level again, the PMOS transistor 301 in the modulation voltage module 30 is in an off state during this time, and the voltage Vp is the voltage filtered by the voltage comparator 201 through the filtering adjustment module 50.
In summary, comparing fig. 3 with the prior art circuit, the working principle of the circuit of the present invention is: when the nonvolatile memory needs to be programmed, when the first memory cell is programmed, the charge pump 202 starts to work, the control module 60 of the nonvolatile memory sends out a work enable signal EN and a programming operation enable signal WR _ EN, the work enable signal EN is at a high level, the programming operation enable signal WR _ EN is also at a high level, the duration of the whole programming is from the beginning to the completion, when the programming operation is finished, the programming operation enable signal WR _ EN is at a high level, the two signals are both sent to the first nand gate nand1, the "-" terminal voltage in the two input ends of the voltage comparator 401 is a preset reference voltage Vref, the voltage of the "+" end is a comparison voltage V1 generated by the serial voltage division of the output voltage of the charge pump 202 through the first resistor R0 and the second resistor R1, and the value of the comparison voltage V1 is smaller than the voltage Vref, according to the function of the voltage comparator 401, the output voltage of the voltage comparator 401 is low, the low voltage enables the clock circuit 201 to generate a high frequency signal, the high frequency signal is output to the charge pump 202, the charge pump 202 outputs a high voltage VOUT for being provided to the drain of the memory cell 70 for programming operation, meanwhile, the operation enable signal EN and the programming operation enable signal WR _ EN generate a high level signal through the modulation voltage module 30, the high level signal enables the PMOS transistor 301 to be in an off state, the output voltage of the voltage comparator 401 gradually increases along with the increase of the VOUT voltage, the output voltage Vp also gradually increases after being filtered by the filtering and adjusting module 50, the frequency of the clock circuit 201 also gradually decreases until the VOUT output voltage meets the drain voltage required for programming operation, and at this time, the output voltage VOUT is discharged and reduced by the resistors R0, R1 and R2, however, since the discharging current is very small, when the second memory cell programming operation is to be performed, the current generated by the VOUT voltage may be much larger than the programming current required by the memory cell 70, after the first memory cell programming operation is completed, the control module 60 sends a low level programming operation enable signal WR _ EN to the modulation voltage module 30, at this time, the operation enable signal EN and the programming operation enable signal WR _ EN generate a low level signal through the modulation voltage module 30, the low level signal enables the PMOS transistor 301 to be in a conducting state, when the PMOS transistor 301 is conducting, the voltage Vp is pulled up to about the voltage value obtained by subtracting the threshold voltage of the PMOS transistor 301 from the power voltage, at this time, the frequency of the clock circuit 201 is reduced to the lowest, the output voltage VOUT of the charge pump 202 is reduced to meet the current required by the next memory cell programming operation, the conducting time of the PMOS transistor 301 is the period from the end of the first memory cell programming operation to the beginning of the second memory cell programming operation, when the second memory cell is programmed, the operation enable signal EN is at a high level, and the programming operation enable signal WR _ EN is at a high level, at this time, the operation enable signal EN and the programming operation enable signal WR _ EN generate a high level signal through the modulation voltage module 30, and the high level signal enables the PMOS transistor 301 to be in an off state again, and the above process is repeated until the programming operation is finished.
It should be noted that if the drain voltage required for the programming operation of the second memory cell is the same as or higher than that of the first memory cell, the voltage generated by the charge pump 202 will be reduced and then increased. Generally, the voltage is too high, the current is too large, the loss of the storage unit in the nonvolatile memory is great, the programming operation of the nonvolatile memory is rather longer in consideration of the service life of the nonvolatile memory element, and the voltage on the storage unit cannot be too large.
The voltage modulation module 30 used in the embodiment of the present invention has a simple overall circuit structure and uses fewer electrical components, so that the reliability of the circuit is higher, and the voltage control during the continuous switching programming operation is better.
Through the embodiment, when a user carries out continuous address switching write operation on the nonvolatile memory, the PMOS tube is conducted within the operation switching interval time, the input voltage of the clock circuit is increased, the frequency of the clock circuit is reduced, the purposes that the voltage at the drain end does not continue to be pumped up and the current voltage is kept are achieved, and the service life of the memory unit is ensured.
While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.
The above detailed description of the circuit for controlling the drain terminal voltage provided by the present invention has been presented, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (7)
1. A circuit for controlling a drain terminal voltage, the circuit comprising:
the device comprises a drain terminal charge pump module, a comparison voltage module, a filtering regulation module and a modulation voltage module;
the drain terminal charge pump module is respectively connected with the comparison voltage module, the filtering regulation module and the modulation voltage module and is used for generating drain terminal voltage;
the comparison voltage module is respectively connected with the drain terminal charge pump module and the filtering regulation module and is used for providing input voltage for the filtering regulation circuit; a voltage comparator is arranged in the voltage comparison module;
the filtering adjusting module is respectively connected with the drain terminal charge pump module, the comparison voltage module and the modulation voltage module, and is used for responding to the change of the drain terminal voltage to adjust the frequency of a clock circuit in the drain terminal charge pump module and transmitting the output voltage of the comparison voltage module to the clock circuit after filtering;
the modulation voltage module is respectively connected with the filtering regulation module and the drain terminal charge pump module and is used for controlling the drain terminal voltage output by the drain terminal charge pump module;
the circuit for controlling the voltage of the drain terminal is applied to a memory, and the memory further comprises a control module;
the control module is connected with the modulation voltage module and used for sending a work enabling signal and a programming operation enabling signal to the modulation voltage module, and the work enabling signal and the programming operation enabling signal are used for controlling the modulation voltage module to increase the output voltage of the voltage comparator.
2. The circuit of claim 1, wherein the drain voltage charge pump module comprises: a clock circuit and a charge pump;
the output end of the clock circuit is connected with the input end of the charge pump and is used for providing a clock signal for the charge pump;
and the output end of the charge pump is connected with the storage unit and used for providing a drain end voltage for the storage unit.
3. The circuit of claim 1, wherein the comparison voltage module comprises a comparison voltage circuit;
the voltage comparator comprises a reference voltage connecting end, a comparison voltage connecting end and an output end;
the reference voltage connection end is connected with reference voltage, the comparison voltage connection end is connected with the comparison voltage circuit, and the output end of the voltage comparator is connected with the input end of the filtering regulation module and used for providing input voltage for the filtering regulation module;
the comparison voltage circuit is connected with a comparison voltage connecting end of the voltage comparator, is used for detecting the output voltage of the charge pump, is compared with the reference voltage, and provides comparison voltage for the voltage comparator;
the voltage comparison circuit comprises a first resistor, a second resistor and a third resistor, the three resistors are connected in series, the first end of the first resistor is connected with the output end of the drain terminal charge pump module, the second end of the first resistor is connected with the first end of the second resistor, the second end of the second resistor is connected with the comparison voltage connecting end of the voltage comparator and the first end of the third resistor, and the second end of the third resistor is grounded.
4. The circuit of claim 1, wherein the filter adjustment module comprises: a first capacitor and a fourth resistor;
the first end of the first capacitor is connected with the output end of the drain terminal charge pump module, and the second end of the first capacitor is respectively connected with the first end of the fourth resistor and the modulation voltage module;
and the second end of the fourth resistor is connected with the output end of the voltage comparator.
5. The circuit of claim 1, wherein the modulation voltage module comprises: the delay circuit comprises a first NAND gate, a first inverter, a second inverter, a first NOR gate, a PMOS (P-channel metal oxide semiconductor) tube and a delay inverter module;
the two input signals of the first NAND gate are the work enabling signal and the programming operation enabling signal respectively;
the output end of the first NAND gate is connected with the input end of the first inverter;
the output end of the first inverter is respectively connected with one input end of the first NOR gate and the input end of the delay inverter module;
the output end of the delay phase inverter module is connected with the input end of the first NOR gate;
the output end of the first NOR gate is connected with the input end of the second inverter;
the output end of the second inverter is connected with the grid electrode of the PMOS tube;
the source electrode of the PMOS tube is connected with a power supply;
and the drain electrode of the PMOS tube is connected with the filtering regulation module and the clock circuit respectively, and the drain electrode of the PMOS tube is the output end of the modulation voltage module.
6. The circuit of claim 5, wherein the delay inverter module comprises: the odd inverters are connected in series and used for generating any delay time, so that the conduction time of the PMOS tube is less than or equal to the time from the end of the first programming operation to the start of the second programming operation;
the input end of a third inverter in the odd inverters is connected with the output end of the first inverter;
the output end of the odd number of inverters in series combination is connected with the input end of the first NOR gate.
7. The circuit of claim 5, wherein the control module sends a high-level operation enable signal and a programming operation enable signal to the modulation voltage module during a first programming operation time, and the operation enable signal and the programming operation enable signal cause the PMOS transistor to be turned off during the first programming operation time;
the control module sends a high-level work enabling signal and a low-level programming operation enabling signal to the modulation voltage module within the time from the end of a first programming operation to the start of a second programming operation, and the work enabling signal and the programming operation enabling signal enable the PMOS tube to be conducted within the time from the end of the first programming operation to the start of the second programming operation;
and the control module sends a high-level work enabling signal and a programming operation enabling signal to the modulation voltage module within a second programming operation time, and the work enabling signal and the programming operation enabling signal enable the PMOS tube to be turned off within a second programming operation period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811595589.9A CN111370038B (en) | 2018-12-25 | 2018-12-25 | Circuit for controlling voltage of drain terminal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811595589.9A CN111370038B (en) | 2018-12-25 | 2018-12-25 | Circuit for controlling voltage of drain terminal |
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| Publication Number | Publication Date |
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| CN111370038A CN111370038A (en) | 2020-07-03 |
| CN111370038B true CN111370038B (en) | 2022-05-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE60028030T2 (en) * | 2000-08-22 | 2006-12-14 | Stmicroelectronics S.R.L., Agrate Brianza | Highly efficient electronic circuit for generating and regulating a supply voltage |
| JP4812085B2 (en) * | 2005-12-28 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
| CN101667774B (en) * | 2008-09-02 | 2012-05-16 | 北京兆易创新科技有限公司 | Closed-loop control charge pump circuit |
| JP6083269B2 (en) * | 2013-03-18 | 2017-02-22 | 株式会社ソシオネクスト | Power supply circuit and semiconductor device |
| CN207625442U (en) * | 2017-09-04 | 2018-07-17 | 合肥格易集成电路有限公司 | A kind of charge pump circuit and memory |
| CN108320762B (en) * | 2018-04-12 | 2019-02-22 | 武汉新芯集成电路制造有限公司 | Charge pump drive circuit |
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| CN111370038A (en) | 2020-07-03 |
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Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Patentee after: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. Patentee before: HEFEI GEYI INTEGRATED CIRCUIT Co.,Ltd. |
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