CN111352019A - Test machine delay compensation method and system and test machine - Google Patents
Test machine delay compensation method and system and test machine Download PDFInfo
- Publication number
- CN111352019A CN111352019A CN202010117178.XA CN202010117178A CN111352019A CN 111352019 A CN111352019 A CN 111352019A CN 202010117178 A CN202010117178 A CN 202010117178A CN 111352019 A CN111352019 A CN 111352019A
- Authority
- CN
- China
- Prior art keywords
- signal
- test
- delay
- tester
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/18—Complex mathematical operations for evaluating statistical data, e.g. average values, frequency distributions, probability functions, regression analysis
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Data Mining & Analysis (AREA)
- General Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Operations Research (AREA)
- Probability & Statistics with Applications (AREA)
- Evolutionary Biology (AREA)
- Algebra (AREA)
- Bioinformatics & Computational Biology (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- Bioinformatics & Cheminformatics (AREA)
- Life Sciences & Earth Sciences (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a test machine delay compensation method, a test machine delay compensation system and a test machine. Wherein, each signal pin for external connection in the tester is in an open circuit state; each signal pin is electrically connected with one chip pin of the tester chip through the signal wire where the signal pin is located; the delay compensation method comprises the following steps: the chip of the tester sends a test signal to the signal pin; after the test signal is transmitted to the signal pin, the test signal is reflected back to the test machine chip along the opposite direction; the chip of the testing machine receives a testing reflection signal reflected by the signal pin; the tester chip obtains the transmission delay of the signal pin according to the test signal and the test reflection signal; the chip of the tester selects the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference; the tester chip compensates the signal delay of each signal pin according to the delay reference. The invention ensures the delay of the chip output to each signal pin (the connection part of the tester and the test board) in the tester, and has the same time sequence.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a delay compensation method and system for a testing machine and the testing machine.
Background
In the production process of the chip, various functions of the chip are ensured to meet the design requirements through a testing means. Chip testing can be divided into two types of testing, the first type is testing before wafer packaging, and the second type is testing after wafer packaging. The first type of test requires a probe card (probe) for testing, and the second type of test requires a carrier board (loadboard) for testing. Both the two test boards need to be tested by using a test machine board card;
because the number of the test machine boards is large, the number of signals on each board is also large, and the large number of signals is difficult to ensure that the routing delays are consistent, but signals of the same type are required to have the same delay time in the timing sequence of the test machine, that is, the signals output by the test machine are required to have the same timing relationship at the connection part of the test machine and the test board, that is, the signals output by the internal chip of the test machine to the connection part of the test machine and the test board are ensured to have the same delay.
Disclosure of Invention
The invention provides a delay compensation method, a delay compensation system and a tester for a tester, which are used for solving the problem of delay of chips in the tester output to the connection part of the tester and a test board, so that signals output by the tester have the same time sequence at the connection part of the tester and the test board. Specifically, the technical scheme of the invention is as follows:
in a first aspect, the invention discloses a test machine delay compensation method, which is applied to a test machine, wherein each signal pin for external connection in the test machine is in an open circuit state; each signal pin is electrically connected with one chip pin of the tester chip through the signal wire where the signal pin is located; the delay compensation method for the tester comprises the following steps: the chip of the tester sends a test signal to the signal pin; after the test signal is transmitted to the signal pin through a signal wire, the test signal is reflected back to the tester chip along the opposite direction; the chip of the testing machine receives a testing reflection signal reflected by the signal pin; the tester chip obtains the transmission delay of the signal pin according to the test signal and the test reflection signal; after the tester chip obtains the transmission delays of all the signal pins, selecting the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference; and the tester chip compensates the signal delay of each signal pin according to the delay reference.
Preferably, the test signal is a sine wave signal or a cosine wave signal.
Preferably, the obtaining the transmission delay of the signal pin according to the test signal and the test reflection signal specifically includes: acquiring phase and frequency information of the test signal; counting the phase information of the test reflection signal reflected by the signal pin; calculating the phase difference between the test reflection signal of the signal pin and the test signal; calculating the transmission rate of the test signal in the signal line; (ii) a And calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire.
Preferably, the calculation formula of the transmission rate C of the test signal in the signal line is: c/e ^ (1/2); the calculation formula of the transmission delay Y of the test signal sent to the signal pin is as follows: y ═ C (m-n)/(f × 2 ×); wherein: c represents the transmission rate of the test signal in the signal line; c represents the propagation speed of the electromagnetic wave in vacuum; e is expressed as an effective dielectric constant of the PCB of the tester on which the signal lines are arranged; m represents the phase of the test signal; n represents the phase of the test reflection signal reflected back by the signal pin; f represents the frequency of the test signal.
Preferably, according to the delay reference, the compensating the signal delay of each signal pin specifically includes: calculating the compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay; and when the test machine chip outputs signals, compensating corresponding time delay for each signal pin according to the compensation delay of each signal pin.
In a second aspect, the present invention also discloses a test machine delay compensation system, including: the test machine chip is used for externally connecting each signal pin; each signal pin is in an open circuit, and each signal pin is electrically connected with one chip pin of the tester chip through a signal wire where the signal pin is located; the tester chip includes: the device comprises a driver, a receiver and a control module; the driver and the receiver are electrically connected with chip pins of the tester chip; the driver and the receiver are also electrically connected with the control module; wherein: a driver of the tester chip sends a test signal to a signal pin; after the test signal is transmitted to the signal pin through a signal wire, the test signal is reflected back to the tester chip along the opposite direction; a receiver of the tester chip receives a test reflection signal reflected by the signal pin; the control module acquires the transmission delay of the signal pin according to the test signal and the test reflection signal; the control module selects the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference; and the control module compensates the signal delay of each signal pin according to the delay reference.
Preferably, the test signal is a sine wave signal or a cosine wave signal.
Preferably, the control module comprises: the statistic acquisition submodule is used for acquiring phase and frequency information of the test signal; counting the phase information of the test reflection signal reflected by the signal pin; the calculation submodule is used for calculating the phase difference between the test reflection signal of the signal pin and the test signal; the signal line is also used for calculating the transmission rate of the test signal in the signal line; (ii) a The test signal receiving circuit is also used for calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire; the calculation submodule is also used for calculating the compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay; and the compensation submodule is used for compensating corresponding time delay for each signal pin according to the compensation delay of each signal pin when the test machine chip outputs signals.
Preferably, the calculation formula of the transmission rate C of the test signal in the signal line is: c/e ^ (1/2); the calculation formula of the transmission delay Y of the test signal sent to the signal pin is as follows: y ═ C (m-n)/(f × 2 ×); wherein: c represents the transmission rate of the test signal in the signal line; c represents the propagation speed of the electromagnetic wave in vacuum; e is expressed as an effective dielectric constant of the PCB of the tester on which the signal lines are arranged; m represents the phase of the test signal; n represents the phase of the test reflection signal reflected back by the signal pin; f represents the frequency of the test signal.
In a third aspect, the invention also discloses a tester, which comprises the tester delay compensation system.
In the delay compensation method of the tester, the reference time delay can be selected by collecting and calculating the transmission delay of each signal pin, and then the reference time delay is taken as a standard, and the respective transmission delays are combined, so that the corresponding delay compensation can be carried out on each signal pin when the chip of the tester sends out signals, thereby ensuring that the time sequence on the output of multi-path signal wires is kept consistent when the tester carries out testing, and also ensuring the testing consistency of the chip. In addition, better, because the sine wave interference killing feature is very strong, if adopt the sine wave as test signal, then the signal delay of gathering is more accurate and effective, and then improves subsequent delay compensation's accuracy and validity greatly.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a flow chart of one embodiment of a tester delay compensation method of the present invention;
FIG. 2 is a flow chart of another embodiment of a tester delay compensation method of the present invention;
FIG. 3 is a diagram illustrating test signal transmission according to another embodiment of the testing machine delay compensation method of the present invention;
FIG. 4 is a diagram illustrating delay compensation in another embodiment of the tester delay compensation method according to the present invention;
FIG. 5 is a block diagram of one embodiment of a tester delay compensation system of the present invention;
FIG. 6 is a block diagram of a tester delay compensation system according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a test machine delay compensation method, which is particularly applied to a test machine, wherein each signal pin for external connection in the test machine is in an open circuit state; generally, a tester performs information transmission with a test board through signal pins, where the signal pins are located, that is, at a connection point with the test board. Each signal pin is electrically connected with one chip pin of the tester chip through the signal wire where the signal pin is located; the signal line is generally arranged on the PCB of the tester, and the delay compensation method of the invention requires that the tester is not provided with a test board, thereby ensuring the open circuit state of the signal pin at the connection position. A flow diagram of one embodiment of a tester delay compensation method is shown in fig. 1, and includes:
s101, the tester chip sends a test signal to a signal pin; specifically, for example, a sine wave signal or a cosine wave signal is sent, and particularly, because the sine wave signal has very strong anti-interference capability, if the sine wave signal is used as a test signal, subsequent signal delay acquisition calculation is facilitated, and a more accurate and effective basis is provided.
S102, after the test signal is transmitted to the signal pin through the signal wire, the test signal is reflected back to the tester chip along the opposite direction; specifically, when a test signal is transmitted to a signal pin along with a signal trace, that is, a connection point with the test board card, the test signal is reflected back to the test machine chip in the opposite direction due to the open circuit of the signal pin at the connection point.
S103, the chip of the testing machine receives a testing reflection signal reflected by the signal pin; after the test signal is reflected back, the test reflected signal is received by the test machine chip.
S104, the tester chip obtains the transmission delay of the signal pin according to the test signal and the test reflection signal; specifically, the phase difference between the test signal and the test reflection signal can be obtained according to the test signal and the test reflection signal, and the transmission delay of the signal pin corresponding to the test reflection signal can be further obtained by calculating the transmission rate of the test signal on the test machine PCB (signal routing).
S105, after the tester chip obtains the transmission delays of all the signal pins, selecting the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference; similarly, the transmission delay of the rest signal pins on the chip of the tester can be calculated by adopting the steps S101-S104; after the transmission delay of each signal pin is obtained, the transmission delay with the longest time can be selected as a delay reference.
And S106, the tester chip compensates the signal delay of each signal pin according to the delay reference. Specifically, after the delay reference is obtained, corresponding compensation can be performed according to the transmission delay of the specific signal pin. For example, the delay reference is 5ns, and if the transmission delay of the signal pin a is 2ns, the transmission delay of the signal pin B is 3 ns; then, when the chip of the tester performs test work and outputs a signal, 3ns delay is added to the signal pin A, and 2ns delay is added to the signal pin B; the time sequence of the signal transmitted to all signal pins is ensured to be consistent, so that the signals of the same type required on the time sequence of the tester have the same delay time.
By adopting the method of the embodiment, the time sequence on the multi-path signal routing output can be kept consistent when the test machine performs the test, and the consistency of the chip test can be ensured. In addition, better, because the anti-jamming capability of sine wave is very strong, if adopt the sine wave as test signal, the signal delay of the mode collection through this embodiment is more accurate and effective.
Another embodiment of the method of the present invention, as shown in fig. 2, comprises:
s201, the tester chip sends a test signal to a signal pin;
s202, after the test signal is transmitted to the signal pin through the signal wire, the test signal is reflected back to the tester chip along the opposite direction;
s203, the chip of the testing machine receives the testing reflection signal reflected by the signal pin; after the test signal is reflected back, the test reflected signal is received by the chip of the test machine;
s204, acquiring phase and frequency information of the test signal; specifically, for example, the test signal is a sine wave signal, the phase of which is n, and the frequency of which is f;
s205, counting the phase information of the test reflection signal reflected by the signal pin; supposing that the phase of a test reflection signal received by a certain signal pin is m;
s206, calculating the phase difference between the test reflection signal of the signal pin and the test signal; specifically, the phase difference between the test reflection signal and the test signal at the signal pin is: m-n;
s207, calculating the transmission rate of the test signal in the signal line; (ii) a Specifically, if the dielectric constant of the PCB of the tester is e, and the transmission rate of the sine wave signal in vacuum is c, the propagation rate of the test signal on the tester is: c/e ^ (1/2);
generally, c represents the propagation speed of electromagnetic wave in vacuum, which is a substantially constant value, and the transmission rate of the test signal on the PCB board of the tester (the signal line is arranged on the PCB board) is affected by the PCB board material, assuming that the effective dielectric constant of the signal propagation path on the PCB is e, the propagation speed of the signal is: c/e ^ (1/2); wherein c represents the propagation speed of the electromagnetic wave in vacuum; e is expressed as the effective dielectric constant of the tester PCB board where the signal lines are arranged.
And S208, calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire. Specifically, the transmission delay of the test signal sent to the signal pin is: c (m-n)/(f 2 pi); wherein C represents a transmission rate of the test signal in the signal line; m represents the phase of the test signal; n represents the phase of the test reflection signal reflected back by the signal pin; f represents the frequency of the test signal.
S209, selecting the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference;
and S210, compensating the signal delay of each signal pin according to the delay reference.
Preferably, the step S210 of compensating the signal delay of each signal pin according to the delay reference specifically includes:
s211, calculating the compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay;
s212, when the test machine chip outputs signals, corresponding time delay is compensated for each signal pin according to the compensation delay of each signal pin.
Another embodiment of the method of the present invention provides a new method for calculating tester delay, as shown in fig. 3 and 4, a chip pin used on a board card of a tester is an I/O interface, and the pin includes a driver and a receiver inside, and the specific compensation method is described as follows,
(1) the test machine is not provided with a test board, so as to ensure the open circuit state of the signal pin at the joint
(2) The pin of the chip of the tester sends a continuous sine wave signal with the frequency of f to the signal routing path. Since the tester chip counts the phase information of the sine wave, for example, n.
(3) The sine wave signal is transmitted to the connection and is reflected back to the tester chip in the opposite direction due to the open pin at the connection.
(4) The tester chip receives the reflected sine wave signal, and the tester chip counts the phase information of the sine wave, for example, m.
(5) The tester calculates the phase difference m-n of the sine wave.
(6) The dielectric constant of the PCB of the tester is e, the transmission rate of the sine wave signal in vacuum is c, the propagation rate of the signal on the tester is as follows: c/e ^ (1/2), then the transmission delay of the signal: y ═ C (m-n)/(f × 2 ×) by weight.
(7) The test machine will collect the propagation delays of other signal lines in the same way and select the longest signal line among these signals as the reference, i.e. select the transmission delay with the longest time among the transmission delays of the signal pins as the reference delay. Further, the delay of other signals is compensated for at the time of output. For example, the propagation delay of signal pin 1 is 1ns, the propagation delay of signal pin 2 is 2ns, and a 1ns delay is added to signal pin 1 when the tester chip outputs, that is, it is ensured that the added delay of 1ns plus the own delay of 1ns is equal to the propagation delay of 2ns of signal pin 2.
By adopting the delay compensation method of the tester of the embodiment, the consistency of the time sequence on the multi-path signal output can be ensured, and the consistency of the chip test can also be ensured. In addition, because the sine wave has very strong anti-interference capability, the signal delay acquired by adopting the method is more accurate and effective.
Based on the same technical concept, the present invention further provides a tester delay compensation system, and an embodiment of the system is shown in fig. 5, where the system includes: a tester chip 100 for externally connecting signal pins (A, B, C, D, E, F pin in the figure); and each signal pin is in open circuit, each chip pin (pins 1, 2, 3, 4, 5 and 6 in the figure) of the tester chip is electrically connected with each signal pin in a one-to-one way through different signal lines; the tester chip 100 includes: driver 110, receiver 120, control module 130; the driver 110 and the receiver 120 are electrically connected to chip pins of the tester chip 100; and the driver 110 and the receiver 120 are also electrically connected with the control module 130; wherein:
the driver 110 of the tester chip 100 sends a test signal to a signal pin; specifically, the test signal is a periodic signal, preferably a sine wave signal or a cosine wave signal, and particularly, because the sine wave signal has very strong anti-interference capability, the sine wave signal is used as the test signal, which is more favorable for subsequent signal delay acquisition and calculation and provides more accurate and effective basis.
After the test signal is transmitted to the signal pin through the signal line, the test signal is reflected back to the tester chip 100 along the opposite direction; specifically, when a test signal is transmitted to a signal pin along with a signal trace, that is, a connection point with the test board card, the test signal is reflected back to the test machine chip in the opposite direction due to the open circuit of the signal pin at the connection point.
The receiver 120 of the tester chip 100 receives the test reflection signal reflected by the signal pin; after the test signal is reflected back, the test reflection signal is received by the tester chip 100.
The control module 130 obtains the transmission delay of the signal pin according to the test signal and the test reflection signal; specifically, according to the phase information of the test signal and the test reflection signal, the phase difference between the test signal and the test reflection signal can be obtained, and then the transmission delay of the signal pin corresponding to the test reflection signal can be further obtained by calculating the transmission rate of the test signal on the test machine PCB (signal routing).
The control module 130 selects the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference; the transmission delay of all signal pins on the chip of the tester can be obtained by adopting the mode; after the transmission delay of each signal pin is obtained, the transmission delay with the longest time can be selected as a delay reference.
The control module 130 compensates for signal delay of each signal pin according to the delay reference. Specifically, after the delay reference is obtained, corresponding compensation can be performed according to the transmission delay of the specific signal pin. For example, the delay reference is 5ns, and if the transmission delay of the signal pin a is 2ns, the transmission delay of the signal pin B is 3 ns; then, when the chip of the tester performs test work and outputs a signal, 3ns delay is added to the signal pin A, and 2ns delay is added to the signal pin B; the time sequence of the signal transmitted to all signal pins is ensured to be consistent, so that the signals of the same type required on the time sequence of the tester have the same delay time.
By adopting the delay compensation system of the tester, the time sequence of the multi-path signal routing output can be kept consistent when the tester tests, and the consistency of chip testing can be ensured. In addition, better, because the anti-jamming capability of sine wave is very strong, if adopt the sine wave as test signal, the signal delay of the mode collection through this embodiment is more accurate and effective.
Another embodiment of the system of the present invention, as shown in FIG. 6, is based on the above-mentioned system embodiment
The control module 130 includes:
a statistic obtaining submodule 131, configured to obtain phase and frequency information of the test signal; counting the phase information of the test reflection signal reflected by the signal pin; specifically, for example, the test signal is a sine wave signal, the phase of which is n, and the frequency of which is f; the phase of the test reflection signal received from a certain signal pin is m;
the calculation submodule 132:
the phase difference of the test reflection signal of the signal pin and the test signal is calculated; the phase difference between the test reflection signal and the test signal of the signal pin is as follows: m-n;
the signal line is also used for calculating the transmission rate of the test signal in the signal line; (ii) a Specifically, the dielectric constant of the PCB of the tester is e, the transmission rate of the sine wave signal in vacuum is c, and the propagation rate of the test signal on the tester is: c/e ^ (1/2); c represents the propagation speed of the electromagnetic wave in vacuum; e is expressed as the effective dielectric constant of the tester PCB board where the signal lines are arranged.
The test signal receiving circuit is also used for calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire; specifically, the transmission delay of the test signal to the signal pin is: y ═ C (m-n)/(f × 2 ×); wherein C represents a transmission rate of the test signal in the signal line; m represents the phase of the test signal; n represents the phase of the test reflection signal reflected back by the signal pin; f represents the frequency of the test signal.
The calculating submodule 132 is further configured to calculate a compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay; specifically, the test machine collects propagation delays of other signal wires in the same manner, and selects the longest signal wire among the signal wires as a reference, that is, selects the longest transmission delay among the signal pins as a delay reference, so as to compensate the delays of other signals during output. For example, the propagation delay of signal pin 1 is 1ns, the propagation delay of signal pin 2 is 3ns, and when the tester chip outputs, 2ns delay is added to signal pin 1, that is, it is ensured that the added delay of 2ns plus the self delay of 1ns of signal pin 1 is equal to the propagation delay of 3ns of signal pin 2.
The compensation submodule 133 is configured to compensate for a corresponding time delay for each signal pin according to the compensation delay of each signal pin when the test machine chip outputs a signal.
In a third aspect, the invention also discloses a tester, which comprises the tester delay compensation system. That is to say, the tester of the present invention has a delay compensation function, and can adopt the delay compensation method in any of the embodiments of the tester delay compensation method to obtain the reference delay, and based on this, when the tester chip transmits a signal, corresponding delays are added to other signal pins according to the difference between the reference delay and its own transmission delay, so as to ensure that the signals output by the tester have the same timing sequence at the connection between the tester and the test board (at each signal pin).
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A delay compensation method for a tester is characterized in that each signal pin for external connection in the tester is in an open circuit state; each signal pin is electrically connected with one chip pin of the tester chip through the signal wire where the signal pin is located; the delay compensation method for the tester comprises the following steps:
the chip of the tester sends a test signal to the signal pin;
after the test signal is transmitted to the signal pin through a signal wire, the test signal is reflected back to the tester chip along the opposite direction;
the chip of the testing machine receives a testing reflection signal reflected by the signal pin;
the tester chip obtains the transmission delay of the signal pin according to the test signal and the test reflection signal;
after the tester chip obtains the transmission delays of all the signal pins, selecting the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference;
and the tester chip compensates the signal delay of each signal pin according to the delay reference.
2. The method as claimed in claim 1, wherein the test signal is a sine wave signal or a cosine wave signal.
3. The delay compensation method of the testing machine according to claim 1 or 2, wherein the obtaining the transmission delay of the signal pin according to the test signal and the test reflection signal specifically comprises:
acquiring phase and frequency information of the test signal;
counting the phase information of the test reflection signal reflected by the signal pin;
calculating the phase difference between the test reflection signal of the signal pin and the test signal;
calculating the transmission rate of the test signal in the signal line; (ii) a
And calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire.
4. The tester delay compensation method of claim 3,
the calculation formula of the transmission rate C of the test signal in the signal line is as follows: c/e ^ (1/2);
the calculation formula of the transmission delay Y of the test signal sent to the signal pin is as follows: y ═ C (m-n)/(f × 2 ×); wherein:
c represents the transmission rate of the test signal in the signal line;
c represents the propagation speed of the electromagnetic wave in vacuum;
e is expressed as an effective dielectric constant of the PCB of the tester on which the signal lines are arranged;
m represents the phase of the test signal;
n represents the phase of the test reflection signal reflected back by the signal pin;
f represents the frequency of the test signal.
5. The method of claim 1, wherein compensating for the signal delay of each signal pin according to the delay reference specifically comprises:
calculating the compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay;
and when the test machine chip outputs signals, compensating corresponding time delay for each signal pin according to the compensation delay of each signal pin.
6. A test machine delay compensation system, comprising: the test machine chip is used for externally connecting each signal pin; each signal pin is in an open circuit, and each signal pin is electrically connected with one chip pin of the tester chip through a signal wire where the signal pin is located; the tester chip includes: the device comprises a driver, a receiver and a control module; the driver and the receiver are electrically connected with chip pins of the tester chip; the driver and the receiver are also electrically connected with the control module; wherein:
a driver of the tester chip sends a test signal to a signal pin;
after the test signal is transmitted to the signal pin through a signal wire, the test signal is reflected back to the tester chip along the opposite direction;
a receiver of the tester chip receives a test reflection signal reflected by the signal pin;
the control module acquires the transmission delay of the signal pin according to the test signal and the test reflection signal;
the control module selects the transmission delay with the longest time from the transmission delay data of each signal pin as a delay reference;
and the control module compensates the signal delay of each signal pin according to the delay reference.
7. The tester delay compensation system of claim 5, wherein the test signal is a sine wave signal or a cosine wave signal.
8. The tester delay compensation system of claim 5 or 6, wherein the control module comprises:
the statistic acquisition submodule is used for acquiring phase and frequency information of the test signal; counting the phase information of the test reflection signal reflected by the signal pin;
the calculation submodule is used for calculating the phase difference between the test reflection signal of the signal pin and the test signal; the signal line is also used for calculating the transmission rate of the test signal in the signal line; (ii) a The test signal receiving circuit is also used for calculating the transmission delay of the test signal sent to the signal pin according to the phase difference between the test reflection signal and the test signal, the frequency information of the test signal and the transmission rate of the test signal in the signal wire;
the calculation submodule is also used for calculating the compensation delay of each signal pin according to the delay reference and the transmission delay of each signal pin; the compensation delay is a difference between the delay reference and the transmission delay;
and the compensation submodule is used for compensating corresponding time delay for each signal pin according to the compensation delay of each signal pin when the test machine chip outputs signals.
9. The tester delay compensation system of claim 7,
the calculation formula of the transmission rate C of the test signal in the signal line is as follows: c/e ^ (1/2);
the calculation formula of the transmission delay Y of the test signal sent to the signal pin is as follows: y ═ C (m-n)/(f × 2 ×); wherein:
c represents the transmission rate of the test signal in the signal line;
c represents the propagation speed of the electromagnetic wave in vacuum;
e is expressed as an effective dielectric constant of the PCB of the tester on which the signal lines are arranged;
m represents the phase of the test signal;
n represents the phase of the test reflection signal reflected back by the signal pin;
f represents the frequency of the test signal.
10. A testing machine comprising the testing machine delay compensation system of any of claims 6-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010117178.XA CN111352019A (en) | 2020-02-25 | 2020-02-25 | Test machine delay compensation method and system and test machine |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010117178.XA CN111352019A (en) | 2020-02-25 | 2020-02-25 | Test machine delay compensation method and system and test machine |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111352019A true CN111352019A (en) | 2020-06-30 |
Family
ID=71192371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010117178.XA Pending CN111352019A (en) | 2020-02-25 | 2020-02-25 | Test machine delay compensation method and system and test machine |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111352019A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024078164A1 (en) * | 2022-10-09 | 2024-04-18 | 苏州华兴源创科技股份有限公司 | Method and apparatus for measuring signal delay of chip tester, and computer device |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212399A (en) * | 1997-08-04 | 1999-03-31 | 松下电器产业株式会社 | Delay time adjuster and adjusting method between multiple transmission lines |
| US20080046771A1 (en) * | 2006-08-16 | 2008-02-21 | Chi-Chun Hsu | Adjustable delay compensation circuit |
| CN101727412A (en) * | 2008-10-30 | 2010-06-09 | 恩益禧电子股份有限公司 | Memory interface and operating method of memory interface |
| CN103176167A (en) * | 2013-03-21 | 2013-06-26 | 徐华中 | Phase-locked-amplifier-based sound location method under strong disturbance |
| CN103414980A (en) * | 2013-07-30 | 2013-11-27 | 浙江中科电声研发中心 | Method for compensating delay and frequency response characteristics of multi-output channel sound system |
| CN108151641A (en) * | 2017-12-14 | 2018-06-12 | 北京无线电计量测试研究所 | The length measurement method and equipment of a kind of radio-frequency transmission line |
| CN108241586A (en) * | 2016-12-27 | 2018-07-03 | 慧荣科技股份有限公司 | Controller circuit and estimated delay compensation method |
| CN109683658A (en) * | 2018-12-30 | 2019-04-26 | 广东大普通信技术有限公司 | A kind of clock signal phase control device and method |
-
2020
- 2020-02-25 CN CN202010117178.XA patent/CN111352019A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1212399A (en) * | 1997-08-04 | 1999-03-31 | 松下电器产业株式会社 | Delay time adjuster and adjusting method between multiple transmission lines |
| US20080046771A1 (en) * | 2006-08-16 | 2008-02-21 | Chi-Chun Hsu | Adjustable delay compensation circuit |
| CN101727412A (en) * | 2008-10-30 | 2010-06-09 | 恩益禧电子股份有限公司 | Memory interface and operating method of memory interface |
| CN103176167A (en) * | 2013-03-21 | 2013-06-26 | 徐华中 | Phase-locked-amplifier-based sound location method under strong disturbance |
| CN103414980A (en) * | 2013-07-30 | 2013-11-27 | 浙江中科电声研发中心 | Method for compensating delay and frequency response characteristics of multi-output channel sound system |
| CN108241586A (en) * | 2016-12-27 | 2018-07-03 | 慧荣科技股份有限公司 | Controller circuit and estimated delay compensation method |
| CN108151641A (en) * | 2017-12-14 | 2018-06-12 | 北京无线电计量测试研究所 | The length measurement method and equipment of a kind of radio-frequency transmission line |
| CN109683658A (en) * | 2018-12-30 | 2019-04-26 | 广东大普通信技术有限公司 | A kind of clock signal phase control device and method |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024078164A1 (en) * | 2022-10-09 | 2024-04-18 | 苏州华兴源创科技股份有限公司 | Method and apparatus for measuring signal delay of chip tester, and computer device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4200135B2 (en) | Multi-static sensor device for short-range radar measurement and driving method of the sensor device | |
| EP2142936B1 (en) | Chip tester and method for providing timing information | |
| CN109632044A (en) | Article position measuring device with multiple radar chips | |
| US20040122607A1 (en) | System and method of measuring a signal propagation delay | |
| KR101329594B1 (en) | Calibration device | |
| US5256964A (en) | Tester calibration verification device | |
| CN101682431B (en) | Calibrating jitter | |
| KR100233471B1 (en) | Transmission path structure for measuring propagation delay time thereof | |
| CN111352019A (en) | Test machine delay compensation method and system and test machine | |
| US6107807A (en) | Method and circuit for locating a short circuit or cable break in a bus system | |
| CN101533067A (en) | A method, device and system to realize trip point location in the integrated circuit card | |
| CN105137196A (en) | Simple SAS and SATA signal routing impedance test method | |
| US20020095633A1 (en) | Electronic component, a test configuration and a method for testing connections of electronic components on a printed circuit board | |
| WO2002025299A1 (en) | Electronic circuit and method for testing a line | |
| US6828799B2 (en) | Propagation delay time measuring method and testing apparatus | |
| US11598803B1 (en) | System and method for compensating for power loss due to a radio frequency (RF) signal probe mismatch in conductive signal testing | |
| CN110888114A (en) | Simulation evaluation method for control system of radar receiver | |
| CN109583029B (en) | Method and device for eliminating slope value of signal edge influenced by edge | |
| KR102179063B1 (en) | SoC test apparatus calculating signal line length | |
| CN112654082B (en) | Timing device, base station, positioning system, calibration method and positioning method | |
| CN117783842B (en) | Delay correction processing method, system and platform for boundary scan test | |
| CN118607443A (en) | Method, device, equipment and storage medium for determining signal transmission delay | |
| CN117407346B (en) | Sampling point adjusting system and method for FLASH outside vehicle-gauge chip | |
| US11855707B2 (en) | System and method for measuring path loss of a conductive radio frequency (RF) test signal path | |
| CN110311722A (en) | A kind of satellite repeater local frequency calibration test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200630 |
|
| RJ01 | Rejection of invention patent application after publication |