CN111354775B

CN111354775B - Display substrate, manufacturing method thereof and display device

Info

Publication number: CN111354775B
Application number: CN202010209990.5A
Authority: CN
Inventors: 王国英; 宋振
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-03-23
Filing date: 2020-03-23
Publication date: 2022-10-21
Anticipated expiration: 2040-03-23
Also published as: CN111354775A

Abstract

The disclosure relates to a display substrate, a manufacturing method thereof and a display device, and belongs to the field of displays. The display substrate is provided with a plurality of sub-pixel areas which are arranged in an array, and each sub-pixel area comprises a storage capacitor, a driving transistor and an organic light emitting diode; the grid electrode of the driving transistor is electrically connected with the first polar plate of the storage capacitor, and the first polar plate of the storage capacitor is positioned on any one of the layer where the active layer of the driving transistor is positioned, the layer where the grid electrode of the driving transistor is positioned and the layer where the source drain electrode of the driving transistor is positioned; the source electrode of the driving transistor is electrically connected with the power line; the drain electrode of the driving transistor is electrically connected with the anode of the organic light emitting diode, the second polar plate of the storage capacitor is on the same layer as the anode of the organic light emitting diode, and an insulating layer is arranged between the first polar plate and the second polar plate.

Description

Display substrate, manufacturing method thereof and display device

Technical Field

The disclosure relates to the field of displays, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

As display devices have been developed, people have increasingly demanded higher display effects of the display devices. The number of pixel cells Per Inch of the display device, i.e. the pixel density (PPI), is an important measure for the display effect. The larger the PPI value is, the higher the resolution of the display device is, the clearer the image displayed by the display device is, and the better the display effect is.

The display substrate of the display device comprises a display area and a peripheral area arranged around the display area, wherein pixel units are distributed in the display area in an array mode, and a driving circuit is arranged in the peripheral area. Each pixel unit is provided with a storage capacitor and a Thin Film Transistor (TFT), a driving circuit supplies electric energy to the storage capacitor through a power signal (VDD) line, the VDD line is arranged in a source drain layer, the TFT is supplied with electric energy after the storage capacitor is charged, and the voltage of the pixel unit is kept, so that the display device can continuously display images. In the related art, two capacitor plates of the storage capacitor are respectively located in the gate layer and the source/drain layer, and an Interlayer Dielectric (ILD) layer is located between the gate layer and the source/drain layer.

When the PPI of the display device is larger, the number of pixel cells in the display device is larger, and the VDD line needs to supply more pixel cells with electric energy, i.e. needs to deliver more current. In order to enable the VDD line to carry a larger current, the thickness of the VDD line is increased, i.e., the thickness of the source and drain layers is increased. The thickness of the ILD is generally proportional to the thickness of the source and drain layers, so as the thickness of the source and drain layers increases, the ILD layer becomes thicker. The ILD layer becomes thicker, so that the distance between the two capacitor plates of the storage capacitor becomes larger, the capacitance of the storage capacitor becomes smaller, and sufficient electric energy cannot be provided for the TFT, thereby affecting the display effect of the display device.

Disclosure of Invention

The embodiment of the disclosure provides a display substrate, a manufacturing method thereof and a display device, which can increase the capacitance of a storage capacitor. The technical scheme is as follows:

in one aspect, the present disclosure provides a display substrate having a plurality of sub-pixel regions arranged in an array, each of the sub-pixel regions including a storage capacitor, a driving transistor, and an organic light emitting diode;

the grid electrode of the driving transistor is electrically connected with the first polar plate of the storage capacitor, and the first polar plate of the storage capacitor is positioned on any one of the layer where the active layer of the driving transistor is positioned, the layer where the grid electrode of the driving transistor is positioned and the layer where the source and drain electrodes of the driving transistor are positioned;

the source electrode of the driving transistor is electrically connected with a power line;

the drain electrode of the driving transistor is electrically connected with the anode of the organic light emitting diode, the second polar plate of the storage capacitor is on the same layer as the anode of the organic light emitting diode, and an insulating layer is arranged between the first polar plate and the second polar plate.

In one implementation manner of the embodiment of the present disclosure, the sub-pixel region includes a light emitting region and a light shielding region, and the storage capacitor is located in the light emitting region.

In one implementation of the embodiments of the present disclosure, the active layer and the anode layer in the light emitting region are both transparent.

In one implementation of the embodiment of the disclosure, the first plate is located on a layer where an active layer of the driving transistor is located.

In an implementation manner of the embodiment of the present disclosure, two sides of the light emitting region are provided with light blocking structures, the light blocking structures and the source and drain electrodes of the organic light emitting diode are in the same layer, and the light blocking structures are located on two sides of the light emitting region along the row direction of the sub-pixel region.

In one implementation manner of the embodiment of the present disclosure, the gate of the driving transistor is electrically connected to the first plate of the storage capacitor through the light blocking structure.

In one implementation manner of the embodiment of the present disclosure, the light-shielding region includes a substrate, an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a source drain layer, an insulating layer, and an anode layer, which are sequentially stacked;

the light emitting region includes the base substrate, the active layer, the insulating layer, and the anode layer, which are sequentially stacked.

In one implementation manner of the embodiment of the present disclosure, the display substrate further includes an organic light emitting layer and a cathode layer sequentially stacked on the anode layer;

the cathode layer is configured to reflect light of the organic light emitting layer and to emit the light from the substrate.

In an implementation manner of the embodiment of the present disclosure, the display substrate further includes a color film layer located between the substrate and the active layer, the color film layer includes a plurality of color filters and a light blocking sheet, the color filters are located in the light emitting areas, and the light blocking sheet is located in the light blocking area.

In another aspect, the present disclosure provides a method for manufacturing a display substrate, the method including:

providing a substrate base plate;

forming sub-pixel regions on the substrate, each of the sub-pixel regions including a storage capacitor, a driving transistor, and an organic light emitting diode;

In another aspect, the present disclosure provides a display device comprising the display substrate of any one of the preceding claims.

The technical scheme provided by the embodiment of the disclosure has the following beneficial effects:

in the embodiment of the present disclosure, the storage capacitor and the driving transistor of the sub-pixel region control the organic light emitting diode to emit light together, so that the sub-pixel region displays color. The gate of the driving transistor supplies a voltage to the first plate of the storage capacitor, and the anode of the organic light emitting diode supplies a voltage to the second plate of the storage capacitor. The first polar plate of the storage capacitor is positioned on any one of the layer where the active layer of the driving transistor is positioned, the layer where the grid electrode of the driving transistor is positioned and the layer where the source drain electrode of the driving transistor is positioned, and the second polar plate of the storage capacitor is positioned on the same layer as the anode of the organic light-emitting diode. An insulating layer is arranged between the first polar plate and the second polar plate at intervals, the thickness of the insulating layer is not influenced by the source drain layer, and the insulating layer can be made thinner under the condition that the source drain layer is thickened, so that the distance between the first polar plate and the second polar plate is shortened, the capacitance of the storage capacitor is increased, enough electric energy can be provided for the driving transistor, and the display effect of the display device is prevented from being influenced.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

Fig. 1 is a top view of a display substrate provided by an embodiment of the present disclosure;

fig. 2 is a cross-sectional view of a display substrate provided by an embodiment of the present disclosure;

FIG. 3 is an equivalent diagram of a storage capacitor provided by an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a pixel region according to an embodiment of the disclosure;

FIG. 5 is an electrical connection diagram of a sub-pixel region provided by an embodiment of the present disclosure;

fig. 6 is a flowchart illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 7 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 8 is a flowchart illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 9 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 10 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 11 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 12 is a diagram of a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 13 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 14 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 15 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 16 is a diagram of a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 17 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 18 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 19 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 20 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 21 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 22 is a diagram of a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 23 is a diagram illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 24 is a diagram illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 25 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 26 is a diagram of a process for manufacturing a display substrate according to an embodiment of the disclosure;

fig. 27 is a diagram illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 28 is a diagram illustrating a manufacturing process of a display substrate according to an embodiment of the disclosure;

fig. 29 is a manufacturing process diagram of a display substrate according to an embodiment of the disclosure.

Detailed Description

To make the objects, technical solutions and advantages of the present disclosure more apparent, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Fig. 1 is a top view of a display substrate provided by an embodiment of the present disclosure, and referring to fig. 1, the display substrate has a plurality of sub-pixel regions 400 arranged in an array.

Fig. 2 is a cross-sectional view of a display substrate provided in an embodiment of the disclosure. Referring to fig. 2, each of the sub-pixel regions 400 includes a storage capacitor 10, a driving transistor T1, and an organic light emitting diode 30. The driving transistor T1 is connected to a peripheral driving circuit, the driving circuit charges the storage capacitor 10 through the driving transistor T1, and the storage capacitor 10 supplies power to the driving transistor T1 after charging, so as to maintain the voltage of the organic light emitting diode 30, and thus the sub-pixel region 400 displays a picture. The driving transistor T1 is a TFT.

Referring again to fig. 2, the gate 21 of the driving transistor T1 is electrically connected to the first plate 101 of the storage capacitor 10, and the first plate 101 of the storage capacitor 10 is located at any one of the layer where the active layer 201 of the driving transistor T1 is located, the layer where the gate 21 of the driving transistor T1 is located, and the layer where the source drain of the driving transistor T1 is located. The source 22 (not shown in fig. 2, see fig. 4 and 5) of the driving transistor T1 is electrically connected to a power line, the drain 23 of the driving transistor T1 is electrically connected to the anode 31 of the organic light emitting diode 30, the second plate 102 of the storage capacitor 10 is in the same layer as the anode 31 of the organic light emitting diode 30, and an insulating layer 200 is interposed between the first plate 101 and the second plate 102.

In this implementation, the storage capacitor 10 and the driving transistor T1 of the sub-pixel region 400 control the organic light emitting diode 30 to emit light in common, so that the sub-pixel region 400 displays colors. The gate electrode 21 of the driving transistor T1 supplies a voltage to the first plate 101 of the storage capacitor 10, and the anode electrode 31 of the organic light emitting diode 30 supplies a voltage to the second plate 102 of the storage capacitor 10. The first plate 101 of the storage capacitor 10 is located in any one of the layer where the active layer of the driving transistor T1 is located, the layer where the gate electrode 21 of the driving transistor T1 is located, and the layer where the source drain electrode of the driving transistor T1 is located, and the second plate 102 of the storage capacitor 10 is located in the same layer as the anode 31 of the organic light emitting diode 30. The insulating layer 200 is arranged between the first electrode plate 101 and the second electrode plate 102, the thickness of the insulating layer 200 is not affected by the source drain electrode layer, and under the condition that the source drain electrode layer is thickened, the insulating layer 200 can also be made thinner, so that the distance between the first electrode plate 101 and the second electrode plate 102 is shortened, the capacitance of the storage capacitor 10 is increased, sufficient electric energy can be provided for the driving transistor T1, and the display effect of the display device is prevented from being affected.

The structure of the display substrate will be described with reference to the first plate 101 of the storage capacitor 10 being located at the layer where the active layer 201 of the driving transistor T1 is located.

Referring again to fig. 2, the pixel region includes a light emitting region 1 and a light blocking region 2, and the storage capacitor 10 is located in the light emitting region 1.

In the related art, the first and

second plates

101 and 102 are arranged in the light-shielding region 2, and light cannot be emitted from the light-shielding region 2. The first plate 101 and the second plate 102 occupy a certain area in the light-shielding region 2, which increases the area of the light-shielding region 2 and decreases the area of the light-emitting region 1, resulting in a decrease in the aperture ratio of the display panel.

In the embodiment of the present disclosure, the first electrode plate 101 and the second electrode plate 102 are both located in the light emitting region 1, and the area of the light shielding region 2 can be reduced, so that the light emitting region 1 can be arranged to be larger, thereby improving the aperture ratio of the display panel. The display substrate can be used for large-sized high PPI display devices.

Referring again to fig. 2, the first plate 101 of the storage capacitor 10 is located at the layer where the active layer 201 of the driving transistor T1 is located.

In this implementation, when the first plate 101 of the storage capacitor 10 is on the same layer as the active layer of the driving transistor T1, the display substrate may be used in a top-emission or bottom-emission display panel. For a bottom emission display panel, the active layer may be arranged as a transparent active layer, so as to avoid affecting the display effect of the sub-pixel region 400.

In other implementations, the first plate 101 is located at the layer where the gate electrode 21 of the driving transistor T1 is located.

In this implementation, when the first plate 101 of the storage capacitor 10 and the gate 21 of the driving transistor T1 are in the same layer, the gate layer is generally a metal layer, which blocks light in the sub-pixel region 400, so the display substrate is used in a top emission display panel. The gate layer may be made transparent, and the display substrate may be used in a bottom emission display panel.

In other implementations, the first plate 101 is located at a layer where the source and drain of the driving transistor T1 are located.

In this implementation manner, the first electrode plate 101 is located in the source drain layer of the driving transistor T1, and when the source drain is a metal layer, the display substrate is used in a top-emission display panel, and when the source drain layer is a transparent source drain layer, the display substrate may also be used in a bottom-emission display panel.

Here, the bottom emission display panel means that light of the display panel is irradiated from a side of the base substrate 40, and the top emission display panel means that light of the display panel is irradiated from a side of the display substrate opposite to the base substrate 40.

In one implementation of the disclosed embodiment, both the active layer 201 and the anode layer 301 within the light emitting region 1 are transparent.

In this implementation, the display substrate may be a bottom emission display substrate, light of the display substrate is emitted from the substrate 40 through the anode layer 301 and the active layer 201, and the active layer 201 and the anode layer 301 are configured to be transparent, so that the first electrode plate 101 located in the active layer 201 and the second electrode plate 102 located in the anode layer 301 are also transparent, that is, a transparent storage capacitor may be formed. The first electrode plate 101 and the second electrode plate 102 are prevented from blocking light from being emitted from the substrate base plate 40, thereby affecting the display effect of the display base plate.

Illustratively, the active layer 201 and the anode layer 301 may be Transparent Conductive Oxide (TCO) layers, which ensure light transmittance of the active layer 201 and the anode layer 301.

Illustratively, the material for forming the active layer 201 may be any one of Indium Gallium Zinc Oxide (IGZO), AZO compound (AZO), indium Zinc Oxide (IZO), amorphous Indium Gallium Zinc Oxide (a-IGZO), indium Zinc Tin Oxide (IZTO), zinc oxynitride (ZnON), amorphous Silicon (a-Si), polysilicon (p-Si), hexathiophene, and polythiophene. The material has good light transmittance, and ensures the light transmittance of the active layer 201.

Illustratively, the anode layer 301 may be an Indium Tin Oxide (ITO) layer. The indium tin oxide has a small resistivity, which prevents the anode 31 from consuming a large amount of electric power, and has a good light transmittance, which prevents the anode layer 301 from affecting the light irradiation.

Referring to fig. 2 again, the light-shielding region 2 includes a substrate 40, an Active (Act) layer 201, a Gate Insulator (GI) layer 202, a Gate (Gate) layer 203, an interlayer dielectric layer 204, a Source Drain (SD) layer 205, an insulating (PVX) layer 200, and an anode layer 301, which are sequentially stacked, and the light-emitting region 1 includes the substrate 40, the Active layer 201, the insulating layer 200, and the anode layer 301, which are sequentially stacked.

In the embodiment of the present disclosure, the gate insulating layer 202 is located between the active layer 201 and the gate layer 203, and the active layer 201 and the gate layer 203 are separated by the gate insulating layer 202, so that the active layer 201 and the gate layer 203 are separated from each other to enable independent signal transmission. The interlayer dielectric layer 204 is located between the gate layer 203 and the source drain layer 205, and ensures that signals can be transmitted between the gate layer 203 and the source drain layer 205 independently. An insulating layer 200 is arranged between the source drain layer 205 and the anode layer 301, so that signals can be transmitted between the source drain layer 205 and the anode layer 301 independently.

In the embodiment of the present disclosure, the substrate 40 may be a transparent substrate, so as to ensure the light transmittance of the substrate 40.

The substrate base plate 40 may be a base plate manufactured based on an oxidation (english) technology, a silicon technology, and an organic technology, for example. For example, a vitreous silica substrate, ensures strength and light transmittance of the base substrate 40.

Illustratively, the gate insulating layer 202 and the interlayer dielectric layer 204 may be inorganic insulating layers such as silicon nitride (chemical formula: siN) layers or silicon oxynitride (chemical formula: siON) layers, or may be organic insulating layers such as ring-shaped resin insulating layers. The insulation between the silicon nitride and the ring-shaped resin is good, and the insulation between the gate insulating layer 202 and the interlayer dielectric layer 204 is ensured. The gate insulating layer 202 and the interlayer dielectric layer 204 may be the same or different in material.

In the embodiment of the present disclosure, the insulating layer 200 may be a silicon nitride insulating layer. The insulation property of the silicon nitride is good, so that the first polar plate 101 and the second polar plate 102 can be separated, the light transmittance of the silicon nitride is good, and the insulating layer 200 is prevented from influencing the irradiation of light.

In the embodiment of the present disclosure, the gate layer 203 and the source drain layer 205 may be a metal layer or an Indium Tin Oxide (ITO) layer. The stability of the electrical signal transmission of the gate layer 203 and the source-drain layer 205 is ensured.

For example, when the gate layer 203 is a metal layer, the metal material may be a metal such as molybdenum (Mo), aluminum (Al), titanium (Ti), gold (Au), copper (Cu), hafnium (Hf), tantalum (Ta), or the like, or the material of the gate layer 203 may be a composite material such as magnesium/silver (Mg/Ag), calcium/silver (Ca/Ag), samarium/silver (Sm/Ag), aluminum/silver (Al/Ag), barium/silver (Ba/Ag), or the like, or the gate layer 203 may be a stack of neodymium molybdenum alloy/copper/neodymium molybdenum alloy (MoNd/Cu/MoNd). The effectiveness of the electrical signal transmission of the gate layer 203 is ensured.

Referring again to fig. 2, the active layer 201 includes the active portion 25 of the driving transistor T1 and the first plate 101 of the storage capacitor 10, the gate layer 203 includes the gate electrode 21 of the driving transistor T1, and the anode layer 301 includes the anode electrode 31 and the second plate 102 of the storage capacitor 10.

In this implementation, the active portion 25 of the driving transistor T1 and the first plate 101 of the storage capacitor 10 are both disposed in the active layer 201, and the second plate 102 of the storage capacitor 10 is disposed in the anode layer 301. The storage capacitor 10 is located in the light emitting region 1, and the gate insulating layer 202, the gate layer 203, the interlayer dielectric layer 204, the source-drain layer 205, and the like are not arranged in the light emitting region 1, i.e., only one insulating layer 200 is interposed between the first plate 101 and the second plate 102. Therefore, the distance between the first plate 101 and the second plate 102 is reduced, so that the capacitance of the storage capacitor 10 is increased, and the driving transistor T1 can be supplied with sufficient power to avoid affecting the display effect of the display device.

Fig. 3 is an equivalent diagram of a storage capacitor provided in an embodiment of the present disclosure. Referring to fig. 3, the first electrode plate 101 is positioned on the active layer 201, the second electrode plate 102 is positioned on the anode layer 301, and the insulating layer 200 separates the first electrode plate 101 and the second electrode plate 102. The calculation of capacitance is as follows:

in equation (1):

c-capacitance, unit: farad (F);

ε -dielectric constant, unit: meters per farad (F/m);

s-area of the plate, unit: square meter (m) ² )；

d-distance between two polar plates, unit: and (m) rice.

As can be seen from the capacitance calculation formula (1), for the same capacitor plates, the smaller the distance d between the capacitor plates, the larger the capacitance.

In the embodiment of the present disclosure, the distance between the first plate 101 and the second plate 102 becomes smaller, and the capacitance of the storage capacitor 10 can be increased.

In the embodiment of the present disclosure, the active portion 25 in the active layer 201 is a conventional active layer, and the first plate 101 is a conductive active layer, that is, an active layer after metallization processing is performed, so that the first plate 101 and the second plate 102 can form a storage capacitor therebetween.

Illustratively, the active layer may be treated with plasma of argon (Ar) gas and helium (He) gas to form a conductible active layer, i.e., to form the first plate 101.

Referring to fig. 2 again, the active layer 201 of the light-shielding region 2 includes a channel region 211 and a Lightly Doped Drain (LDD) region 212, the channel region 211 corresponds to the gate electrode 21, and the Lightly Doped Drain region 212 is electrically connected to the Drain 23.

In the embodiment of the present disclosure, the active layer 201 of the light-shielding region 2 may further include a lightly doped source region 213, and the lightly doped source region 213 is electrically connected to the source (not shown in fig. 2).

In this implementation, the channel region 211 is the active portion 25, and a lightly doped drain region 212 and a lightly doped source region 213 are disposed in the channel region 211 near the drain 23, so that the lightly doped drain region 212 and the lightly doped source region 213 also bear partial voltage, the voltage borne by the drain 23 and the source is reduced, and the source layer 205 is prevented from being damaged due to overheating caused by overhigh voltage of the drain 23 and the source.

In the embodiment of the present disclosure, the lightly doped drain region 212 and the lightly doped source region 213 may also be conductive active layers, and the lightly doped drain region 212, the lightly doped source region 213 and the first plate 101 may be fabricated by the same method.

As shown in fig. 2, a first Via (Via) 241 is disposed on the inter-layer dielectric layer 204, and the lightly doped drain region 212 is electrically connected to the drain 23 through the first Via 241.

As shown in fig. 2, a second via 2001 is disposed on the insulating layer 200, and the anode 31 is electrically connected to the drain 23 through the second via 2001.

Fig. 4 is a schematic structural diagram of a pixel region according to an embodiment of the disclosure. Referring to fig. 4, the display substrate includes a plurality of power lines 11, a plurality of data lines 12, and a plurality of gate lines 13, the plurality of data lines 12 and the plurality of gate lines crossing to define a plurality of sub-pixel regions. Fig. 4 shows sub-pixel regions of 4 colors, red, white, blue and green, respectively, from left to right.

In order to reduce the resistance of the source drain layer, in the embodiment of the present disclosure, an insulating layer and a metal layer are sequentially fabricated on the source drain layer, and the metal layer is electrically connected to the source drain layer through the via hole 14 shown in fig. 4, which is equivalent to increase the thickness of the source drain layer, thereby reducing the resistance of the source drain layer and reducing the power consumed by the source drain layer.

The sub-pixel regions of 4 colors shown in fig. 4 are all of a 3T1C pixel structure, T representing a TFT, and C representing a storage capacitor. That is, the sub-pixel region 400 includes 3 TFTs (T1, T2, and T3, respectively) and 1 storage capacitor. In other implementations, the sub-pixel region may be a 2T1C or 7T1C pixel structure, or the sub-pixel region includes other numbers of TFTs and storage capacitors, which is not limited in this disclosure.

It should be noted that, in fig. 4, one pixel region includes four sub-pixel regions for example, in other embodiments, one pixel region may also include three sub-pixel regions, and the three sub-pixel regions correspond to red, blue, and green sub-pixels, respectively.

Fig. 5 is an electrical connection diagram of a sub-pixel region provided in an embodiment of the present disclosure. Referring to fig. 5, the sub-pixel region has a 3T1C pixel structure.

Referring to fig. 4 and 5, the gate electrode of the driving transistor T1 is electrically connected to the first plate, the drain electrode of the driving transistor T1 is electrically connected to the second plate and the anode, the source electrode of the driving transistor T1 is electrically connected to the power line (VDD) 11, the gate electrodes of the first transistor T2 and the second transistor T3 are electrically connected to the gate line 13, and the source electrode of the first transistor T2 is electrically connected to the data line (Vdata) 12. The source of the second transistor T3 is electrically connected to a Sense (Sense) line 15, and the drain of the second transistor T3 is connected between the anode of the OLED and the drain of the driving transistor T1.

In the display stage, the gate line 13 controls the first transistor T2 to be turned on, the data line 12 charges the storage capacitor 10, when the gate voltage of the driving transistor T1 reaches a certain level, the driving transistor T1 is turned on, the power line 11 supplies a driving current to the OLED 30, and the OLED 30 emits light. When the first transistor T2 is turned on, the second transistor T3 is also turned on, the driving integrated circuit connected to the sensing line 15 extracts the current of the OLED 30 or the driving transistor T1, the driving integrated circuit determines the compensation voltage based on the sensed current, and writes the compensation voltage into the storage capacitor 10 through the sensing line 15 for compensation, thereby optimizing the display effect.

Referring again to fig. 2, the display substrate further includes an organic light emitting layer 302 and a Cathode (english: cathode) layer 303 sequentially stacked on the anode layer 301. The cathode layer 303 is configured to reflect light of the Organic Electro Luminescence (OEL) layer 302 and emit the light from the base substrate 40.

In the embodiment of the disclosure, light emitted by the organic light emitting layer 302 may be reflected back in the process of propagation, and the light emitted by the organic light emitting layer 302 also irradiates the cathode layer 303, and the cathode layer 303 reflects the light of the organic light emitting layer 302 and emits the light from the substrate 40, so as to improve the utilization rate of the light, thereby improving the display effect of the display substrate.

Illustratively, the cathode layer 303 may be made of a metal material such as silver (Ag), aluminum (Al), or an alloy thereof, which ensures reflectivity of the cathode layer 303.

Referring to fig. 2 again, the display substrate further includes a Color Filter (CF) layer 50 located between the substrate 40 and the active layer 201, the Color Filter layer 50 includes a plurality of Color filters 501 and a light blocking sheet 502, the Color filters 501 are located in the light emitting region 1, and the light blocking sheet 502 is located in the light blocking region 2.

In this implementation, the color film layer 50 is located between the substrate 40 and the active layer 201, light emitted from the organic light emitting layer 302 sequentially passes through the anode layer 301, the insulating layer 200, and the active layer 201 to reach the color film layer 50, and the light passes through the color filter 501 located in the light emitting region 1 to display color, and finally, the display color is emitted from the substrate 40. The color film layer 50 is disposed on a layer close to the substrate base plate 40, so that the color film layer 50 is more flat, and the display effect of the display base plate is improved.

In the embodiment of the present disclosure, the light blocking sheet 502 plays a role of blocking light. In the related art, the color film layer 50 is disposed on the anode layer 301 for the bottom emission display panel, so that a light shielding layer, which may be called a protection (shield) layer, needs to be formed between the substrate 40 and the active layer 201 to prevent ambient light from passing through the substrate 40 and being irradiated onto the active layer 201, which may affect the performance and the service life of the driving transistor T1. However, the light-shielding layer is generally a metal layer, and in order to avoid voltage generation by the metal layer, the metal layer is electrically connected to the source located in the source drain layer 205, and the source is low voltage, that is, the voltage generated by the metal layer is small, which does not affect the display of the display substrate, so that a via hole needs to be formed in the film layer between the metal layer and the source drain layer 205 to form a trepanning structure, which increases the difficulty in manufacturing. In the embodiment of the present disclosure, the color film layer 50 is located between the substrate 40 and the active layer 201, and when the ambient light passes through the substrate 40 and irradiates to the light blocking sheet 502, the ambient light is absorbed by the light blocking sheet 502, so as to prevent the ambient light from irradiating the active layer 201, and it is not necessary to arrange a light shielding layer to reduce the thickness of the display substrate. And the light blocking sheet 502 is made of an insulating material, and no voltage exists, so that a via hole does not need to be formed, the manufacturing difficulty is reduced, and the production yield of the display substrate is improved.

It should be noted that the intensity of the ambient light is much weaker than the intensity of the light emitted from the organic light emitting layer 302, so the light emitted from the organic light emitting layer 302 passes through the color filter 501, and the ambient light is absorbed by the light blocking sheet 502.

In the embodiment of the present disclosure, filters of 3 colors may be arranged in the light emitting region 1. Respectively as follows: red (R), green (G) and Blue (B) filters. The filters of these 3 colors form pixel units of 3 colors, respectively.

In other implementations, an RGBW pixel unit may be formed, where W represents White (W), and since the display substrate emits White light, when the pixel unit is a White pixel unit, no filter may be disposed in the sub-pixel region 400.

In the embodiment of the present disclosure, the light blocking sheet 502 may be a stack of any one of the red filter, the green filter, and the blue filter, or at least two color filters.

For example, the light blocking sheet 502 may be a red filter, or may be a stack of a red filter, a green filter, and a blue filter.

As shown in fig. 2, the organic light emitting layer 302 is closer to the substrate 40 and the color film layer 50, so as to prevent light from being absorbed by other film layers between the organic light emitting layer 302 and the color film layer 50 during the transmission process, thereby improving the light emitting efficiency of the organic light emitting layer 302, i.e., improving the light utilization rate.

As shown in fig. 2, light blocking structures 24 are disposed on two sides of the light emitting region 1, the light blocking structures 24 are on the same layer as the source and drain electrodes of the driving transistor T1, and the light blocking structures 24 are disposed on two sides of the light emitting region 1 along the row direction of the sub-pixel region 400.

In this implementation, the light blocking structure 24 blocks two sides of the sub-pixel region 400, so that the light leakage problem between the sub-pixel regions is improved, and the display effect of the display substrate is improved.

In the fourth embodiment of the present disclosure, the direction of the rows of the sub-pixel region 400 is the same as the extending direction of the gate lines.

Referring again to fig. 2, the gate electrode 21 of the driving transistor T1 is electrically connected to the first plate 101 of the storage capacitor 10 through the light blocking structure 24.

In this implementation, the gate electrode 21 and the first plate 101 are electrically connected through the light blocking structure 24, a voltage is provided to the first plate 101, and the light blocking structure 24 is multiplexed, thereby reducing the manufacturing processes.

As shown in fig. 2, a third via 242 is further disposed on the interlayer dielectric layer 204, and the light blocking structure 24 may be electrically connected to the gate electrode 21 through the third via 242, so that the gate electrode 21 provides a voltage to the first plate 101.

It should be noted that the light blocking structure 24 is not shown in the schematic structural diagram of the pixel region shown in fig. 4.

Referring again to fig. 2, the display substrate further includes a Pixel Definition Layer (PDL) 60, and the Pixel Definition Layer 60 is located between the anode Layer 301 of the light-shielding region 2 and the organic light-emitting Layer 302.

In the embodiment of the present disclosure, the pixel defining layer 60 is used to separate each pixel unit (i.e., the opening region) of the organic light emitting display, that is, the pixel defining layer 60 forms a plurality of opening regions in the light emitting region 1 by its own groove structure.

An organic light emitting display unit is formed in the groove of the pixel defining layer 60, and includes an anode layer 301, a hole transport layer, an organic light emitting layer 302, and electron transport and cathode layers 303 disposed in the groove of the pixel defining layer 60.

In one implementation manner of the embodiment of the present disclosure, orthographic projections of the first electrode plate 101 and the second electrode plate 102 on the substrate 40 are located in orthographic projections of the opening regions on the substrate 40, and it is ensured that the first electrode plate 101 and the second electrode plate 102 are arranged in the opening regions, so that the area of the opening regions is increased, the light-emitting area is increased, and the display effect is improved.

Referring again to fig. 2, the display substrate further includes a Buffer layer 70, and the Buffer layer 70 is disposed between the color film layer 50 and the active layer 201.

In this implementation, the buffer layer 70 separates the color film layer 50 from the active layer 201, so as to prevent the color film layer 50 from affecting the operation of the active layer 201, and facilitate the fabrication of the driving transistor T1.

Illustratively, the buffer layer 70 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, which ensures the insulating effect of the buffer layer 70 and can separate the color film layer 50 from the active layer 201.

Referring again to fig. 2, the display substrate further includes a first Planarization (PLN) layer 80, and the first Planarization layer 80 is located between the insulating layer 200 and the anode layer 301 in the light-shielding region 2.

In this implementation, the first planarization layer 80 can make the film layer of the light-shielding region 2 more planar, and the anode layer 301 can be more easily fabricated. Meanwhile, the first flat layer 80 has insulation property, so that adjacent film layers can be separated, and the effectiveness of electric signal transmission is ensured.

Illustratively, the first planarization layer 80 may be a Resin (english: resin) layer, a Silicon-on-Glass (english: silicon-on-Glass, abbreviated as SOG) layer, or other organic film layer.

For example, the first planarization layer 80 may be a benzocyclobutene (BCB) resin layer.

As shown in fig. 2, a fourth via 801 is disposed on the first planarization layer 80, the fourth via 801 is communicated with the second via 2001, and the anode 31 is electrically connected to the drain 23 through the second via 2001 and the fourth via 801, so as to ensure that the anode 31 and the drain 23 can transmit electrical signals.

Referring again to fig. 2, the display substrate further includes a second planarization layer 90, the second planarization layer 90 being located on the cathode layer 303.

In this implementation, the second planarization layer 90 may make the display substrate more planar, facilitating subsequent packaging of the panel. Meanwhile, the second flat layer 90 has insulation, so that the cathode layer 303 can be separated from other film layers, and the effectiveness of electrical signal transmission of the cathode layer 303 is ensured.

Referring again to fig. 2, the display substrate further includes an encapsulation layer 100, the encapsulation layer 100 being disposed on the second planar layer 90.

In this implementation, the encapsulation layer 100 encapsulates the display substrate, protecting the internal structure of the display substrate.

For example, the packaging method may be a Thin-Film Encapsulation (TFE) method to ensure the packaging effect.

Fig. 6 is a manufacturing flow chart of a display substrate according to an embodiment of the disclosure. Referring to fig. 6, the method includes:

in step S101, a substrate is provided.

Fig. 7 is a manufacturing process diagram of a display substrate according to an embodiment of the disclosure. Referring to fig. 7, a substrate base plate 40 is provided. The base substrate 40 may be a transparent base substrate, so as to ensure the light transmittance of the base substrate 40. The substrate base plate 40 may be manufactured using oxidation technology, silicon technology, and organic technology.

In step S102, forming sub-pixel regions on a substrate, each sub-pixel region including a storage capacitor, a driving transistor, and an organic light emitting diode; the grid electrode of the driving transistor is electrically connected with the first polar plate of the storage capacitor, and the first polar plate of the storage capacitor is positioned on the film layer between the layer where the source and drain electrodes of the driving transistor are positioned and the substrate; the source electrode of the driving transistor is electrically connected with a power line; the drain electrode of the driving transistor is electrically connected with the anode of the organic light emitting diode, the second polar plate of the storage capacitor is electrically connected with the anode of the organic light emitting diode, and the second polar plate of the storage capacitor is on the same layer as the anode of the organic light emitting diode.

In this implementation, the storage capacitor and the driving transistor of the sub-pixel region control the organic light emitting diode to emit light together, so that the sub-pixel region displays color. The gate of the driving transistor supplies a voltage to the first plate of the storage capacitor, and the anode of the organic light emitting diode supplies a voltage to the second plate of the storage capacitor. The first polar plate of the storage capacitor is positioned on any one of the layer where the active layer of the driving transistor is positioned, the layer where the grid electrode of the driving transistor is positioned and the layer where the source drain electrode of the driving transistor is positioned, and the second polar plate of the storage capacitor is positioned on the same layer as the anode of the organic light-emitting diode. The distance between the first polar plate and the second polar plate is reduced, the capacitance of the storage capacitor is increased, enough electric energy can be provided for the driving transistor, and the display effect of the display device is prevented from being influenced.

The following describes a manufacturing process of the display substrate, taking the layer where the first plate of the storage capacitor is located on the active layer of the driving transistor as an example.

Fig. 8 is a manufacturing flow chart of a display substrate according to an embodiment of the disclosure. Referring to fig. 8, the method includes:

in step S201: a substrate is provided.

In step S202: and manufacturing a color film layer on the substrate base plate.

Referring to fig. 9, a color film layer 50 is fabricated on the substrate base plate 40. The color film layer 50 includes a plurality of color filters 501 and light-blocking sheets 502, wherein the color filters 501 are located in the light-emitting area, and the light-blocking sheets 502 are located in the light-blocking area.

Illustratively, red, blue and green filters may be sequentially formed on the base substrate 40 by a deposition method. For example, the optical filter may be formed by evaporation or printing.

Illustratively, the light blocking sheet 502 may be any one of a red filter, a green filter, a blue filter, or a stack of at least two color filters.

In step S203: and manufacturing a buffer layer on the color film layer.

Referring to fig. 10, a buffer layer 70 is formed on the color film layer 50.

Illustratively, the buffer layer 70 may be formed on the color film layer 50 by an evaporation method. The buffer layer 70 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

In step S204: and manufacturing an active layer on the buffer layer.

Referring to fig. 11, an active layer film 2011 is formed on the buffer layer 70.

The active layer film 2011 may be formed on the buffer layer 70 by evaporation, for example. The active layer film 2011 may be an indium gallium zinc oxide layer film.

Referring to fig. 12, the active layer film 2011 is patterned to obtain an active portion 25 and an active block 26 to be processed, and an active layer 201 is formed.

Illustratively, the active layer film 2011 may be etched by wet etching to form the active layer 201. The etched active layer thin film 2011 may be referred to as an active island.

In step S205: a gate insulating layer and a gate electrode layer are formed on the active layer to cover the active portion.

Referring to fig. 13, a gate insulating film 221 is formed on the active layer 201, and then a gate layer film 231 is formed on the gate insulating film 221.

Referring to fig. 14, the gate insulating layer film 221 and the gate layer film 231 are subjected to patterning processing, resulting in the gate insulating layer 202 and the gate layer 203 covering the active portion 25.

For example, a photoresist may be coated on the gate layer film 231, and then a mask may be coated on the gate layer film 231, and then the gate insulating layer film 221 and the gate layer film 231 may be patterned by wet etching and then dry etching to form the gate insulating layer 202 and the gate layer 203.

Here, covering the active portion means that the active portion is located above the active portion, and an orthogonal projection of the gate insulating layer 202 and the gate layer 203 on the base substrate completely overlaps with a projection of the active portion on the base substrate.

Illustratively, the gate insulating layer 202 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

Illustratively, the gate layer 203 may be a metal layer, the metal material may be a metal such as molybdenum, aluminum, titanium, gold, copper, hafnium, tantalum, or the like, or the material of the gate layer 203 may also be a composite material such as magnesium/silver, calcium/silver, samarium/silver, aluminum/silver, barium/silver, or the like, or the gate layer 203 may also be a stack of a neodymium molybdenum alloy/copper/neodymium molybdenum alloy.

In step S200: and conducting treatment is carried out on the active block to be treated.

Referring to fig. 15, the active block 26 to be processed is subjected to a conductimerization process.

Illustratively, the active mass 26 may be treated with a plasma of argon and helium to form a conductive active layer, i.e., to form the first plate 101. The LDD region 212 and the lightly doped source region 213 may be formed on the active layer 201 in the same manner.

In step S207: an interlayer dielectric layer is formed on the active layer.

Referring to fig. 16, an interlayer dielectric layer 204 is fabricated on the active layer 201.

Illustratively, the interlayer dielectric layer 204 may be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The interlayer dielectric layer 204 may be formed by evaporation.

Referring to fig. 17, the interlayer dielectric layer 204 is patterned to expose the active layer of the light-shielding region, and a third via hole 242 corresponding to the gate electrode 21 is formed on the interlayer dielectric layer 204.

Illustratively, the interlayer dielectric layer 204 of the display region may be removed by photolithography, and the third via 242 may be formed on the interlayer dielectric layer 204. While a first via 241 may be fabricated on the inter-level dielectric layer 204.

In step S208: and manufacturing a source drain layer on the interlayer dielectric layer.

Referring to fig. 18, a source drain layer 205 is formed on the interlayer dielectric layer 204, and the light blocking structure 24 is electrically connected to the gate electrode 21 through a third via 242. The drain 23 is electrically connected to the lightly doped drain region 212 through the first via 241.

Illustratively, the source drain layer 205 may be a metal layer or an ito layer. The material of the metal layer may be the same as or different from the metal material of the gate layer 203. Source and drain layers 205 may be deposited or sputtered on interlayer dielectric layer 204.

Referring to fig. 19, the source-drain layer 205 is patterned to expose the active layer 201 of the light emitting region.

Illustratively, the source/drain layer 205 may be patterned by etching.

In step S209: and manufacturing an insulating layer on the source drain layer.

Referring to fig. 20, an insulating layer 200 is fabricated on the source drain layer 205.

Illustratively, the insulating layer 200 may be a silicon nitride insulating layer. The insulating layer 200 may be formed on the source/drain layer 205 by evaporation.

Referring to fig. 21, a second via 2001 corresponding to the drain 23 is opened on the insulating layer 200.

The second via 2001 may be formed by laser drilling or etching, for example.

In step S210: a first planarization layer is formed on the insulating layer.

Referring to fig. 22, a first planarization layer 80 is fabricated on the insulating layer 200.

Illustratively, the material of the first planarization layer 80 may be a resin layer or other organic film layer. The first planarization layer 80 can be formed on the insulating layer 200 by evaporation.

Referring to fig. 23, the first planarization layer 80 is patterned to expose the insulating layer 200 of the display region. A fourth via 801 corresponding to the drain 23 is opened in the first planarization layer 80.

Illustratively, the first planarization layer 80 may be patterned by etching. The fourth via 801 corresponds to the second via 2001.

In step S211: an anode layer is fabricated on the first planar layer.

Referring to fig. 24, an anode layer 301 is fabricated on the first planarization layer 80, and an anode of the anode layer 301 is electrically connected to the drain electrode 23 through the second via 2001 and the fourth via 801.

Illustratively, the anode layer 301 may be an indium tin oxide layer. Anode layer 301 may be formed on first planar layer 80 by sputtering or evaporation.

In step S212: a pixel defining layer is fabricated over the anode layer.

Referring to fig. 25, a pixel defining layer 60 is fabricated on the anode layer 301.

Illustratively, the pixel defining layer 60 may be fabricated on the anode layer 301 by evaporation.

Referring to fig. 26, the pixel defining layer 60 is patterned to expose the anode layer 301 of the light emitting region.

Illustratively, the patterning of the pixel defining layer 60 may be performed by etching.

In step S213: and manufacturing an organic light emitting layer on the pixel defining layer.

Referring to fig. 27, an organic light emitting layer 302 is fabricated on the pixel defining layer 60.

Illustratively, the organic light emitting layer 302 may be formed on the pixel defining layer 60 by evaporation.

In step S214: and sequentially manufacturing a cathode layer, a second flat layer and a packaging layer on the organic light-emitting layer.

Referring to fig. 28, a cathode layer 303 is fabricated on the organic light emitting layer 302.

Illustratively, the material of the cathode layer 303 may be a metal material such as silver, aluminum, or an alloy thereof. The cathode layer 303 may be formed by sputtering.

Referring to fig. 29, a second planarization layer 90 is fabricated on the cathode layer 303.

Illustratively, the material of the second planarization layer 90 may be a resin layer or other organic film layer. The second flat layer 90 can be formed by evaporation.

Finally, packaging is performed, and the display substrate shown in fig. 3 can be obtained after the packaging layer 100 is formed.

The embodiment of the disclosure also provides a display device, which includes the display substrate shown in any one of the above figures.

In specific implementation, the display device provided in the embodiments of the present disclosure may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator.

The above description is intended to be exemplary only and not to limit the present disclosure, and any modification, equivalent replacement, or improvement made without departing from the spirit and scope of the present disclosure is to be considered as the same as the present disclosure.

Claims

1. A display substrate having a plurality of sub-pixel regions (400) arranged in an array, each sub-pixel region (400) comprising a storage capacitor (10), a drive transistor (T1) and an organic light emitting diode (30);

the grid electrode (21) of the driving transistor (T1) is electrically connected with the first polar plate (101) of the storage capacitor (10), and the first polar plate (101) of the storage capacitor (10) is located on any one of the layer where the active layer (201) of the driving transistor (T1) is located, the layer where the grid electrode (21) of the driving transistor (T1) is located and the layer where the source drain electrode of the driving transistor (T1) is located;

the source (22) of the driving transistor (T1) is electrically connected with a power line;

the drain electrode (23) of the driving transistor (T1) is electrically connected with the anode (31) of the organic light emitting diode (30), the second plate (102) of the storage capacitor (10) is in the same layer with the anode (31) of the organic light emitting diode (30), and an insulating layer (200) is arranged between the first plate (101) and the second plate (102);

the sub-pixel region (400) comprises a light emitting region (1) and a light shielding region (2), the storage capacitor (10) is located in the light emitting region (1), light shielding structures (24) are arranged on two sides of the light emitting region (1), and a gate (21) of the driving transistor (T1) is electrically connected with a first electrode plate (101) of the storage capacitor (10) through the light shielding structures (24).

2. A display substrate according to claim 1, wherein the active layer (201) and the anode layer (301) in the light emitting area (1) are both transparent.

3. A display substrate according to claim 1, wherein the first plate (101) is located at a layer where an active layer (201) of the drive transistor (T1) is located.

4. The display substrate according to claim 1, wherein the light blocking structure (24) is in the same layer as the source and drain electrodes of the driving transistor (T1), and the light blocking structure (24) is located on two sides of the light emitting region (1) along the row direction of the sub-pixel region (400).

5. The display substrate according to any of claims 1 to 4, wherein the light-shielding region (2) comprises a base substrate (40), the active layer (201), a gate insulating layer (202), a gate layer (203), an interlayer dielectric layer (204), a source drain layer (205), the insulating layer (200), and an anode layer (301) stacked in this order;

the light emitting region (1) includes the substrate base plate (40), the active layer (201), the insulating layer (200), and the anode layer (301) which are sequentially stacked.

6. A display substrate according to claim 5, further comprising an organic light emitting layer (302) and a cathode layer (303) sequentially stacked on the anode layer (301);

the cathode layer (303) is configured to reflect light of the organic light-emitting layer (302) and to emit the light from the base substrate (40).

7. The display substrate according to claim 5, wherein the display substrate further comprises a color film layer (50) located between the substrate (40) and the active layer (201), the color film layer (50) comprises a plurality of color filters (501) and light blocking sheets (502), the color filters (501) are located in the light emitting region (1), and the light blocking sheets (502) are located in the light blocking region (2).

8. A method for manufacturing a display substrate, the method comprising:

providing a substrate base plate;

the drain electrode of the driving transistor is electrically connected with the anode of the organic light emitting diode, the second polar plate of the storage capacitor is on the same layer as the anode of the organic light emitting diode, and an insulating layer is arranged between the first polar plate and the second polar plate; the sub-pixel region (400) comprises a light emitting region (1) and a light shielding region (2), the storage capacitor (10) is located in the light emitting region (1), light shielding structures (24) are arranged on two sides of the light emitting region (1), and a gate (21) of the driving transistor (T1) is electrically connected with a first electrode plate (101) of the storage capacitor (10) through the light shielding structures (24).

9. A display device comprising the display substrate according to any one of claims 1 to 7.