CN111313739B - Linear nonlinear control-based interleaved parallel magnetic integrated electric spark pulse power supply - Google Patents
Linear nonlinear control-based interleaved parallel magnetic integrated electric spark pulse power supply Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/53—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback
- H03K3/57—Generators characterised by the type of circuit or by the means used for producing pulses by the use of an energy-accumulating element discharged through the load by a switching device controlled by an external signal and not incorporating positive feedback the switching device being a semiconductor device
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0045—Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The invention discloses a staggered parallel magnetic integration electric spark pulse power supply based on linear nonlinear control, which comprises a direct current input power supply, a pulse power supply main circuit, a gap voltage detection circuit, a gap current detection circuit, a driving circuit and an FPGA (field programmable gate array) controller, wherein the direct current power supply is used for supplying power to the pulse power supply main circuit; the pulse power supply main circuit is used for providing discharge energy; the voltage detection circuit and the current detection circuit are used for sampling the gap voltage and the gap discharge current; the FPGA controller generates a plurality of paths of PWM signals according to the voltage and current sampling signals; the driving circuit is used for filtering and amplifying the PWM signal and controlling the on-off of a switching tube in the pulse power supply main circuit, a linear and nonlinear control method is specifically adopted, a traditional average current method is adopted in a linear control part, and a saturated duty ratio is adopted in a nonlinear control part for output. The invention improves the dynamic response capability of the power supply, reduces the output current ripple and realizes the controllability of the discharge energy.
Description
Technical Field
The invention relates to an electric spark forming processing pulse power supply, in particular to a staggered parallel magnetic integration electric spark pulse power supply based on linear nonlinear control.
Background
Electro-discharge machining is a non-conventional machining technique for removing a material to be machined by forming a spark discharge between a tool electrode and a workpiece with controlled electrical energy. The method is commonly used for processing holes and cavities in mold production and plays an indispensable role in the field of micro-finishing. Most of the existing pulse power supplies are resistance type pulse power supplies, discharge energy is controlled mainly by controlling the size of a resistor and discharge frequency, controllable parameters are too few, and current waveform change is limited. The defects of poor current controllability, low processing efficiency, low electric energy utilization rate, poor dynamic response performance and the like exist.
Disclosure of Invention
The invention aims to provide a staggered parallel magnetic integration electric spark pulse power supply based on linear nonlinear control and a working method thereof.
The technical solution for realizing the purpose of the invention is as follows: a staggered parallel magnetic integration electric spark pulse power supply based on linear nonlinear control comprises a direct current input power supply, a pulse power supply main circuit, a gap voltage detection circuit, a gap current detection circuit, a driving circuit and an FPGA controller, wherein the direct current power supply is used for supplying power to the pulse power supply main circuit; the pulse power supply main circuit is used for providing discharge energy; the voltage detection circuit and the current detection circuit are used for sampling the gap voltage and the gap discharge current; the FPGA controller generates a plurality of paths of PWM signals according to the voltage and current sampling signals; the driving circuit is used for filtering and amplifying the PWM signal and controlling the on-off of a switch tube in the main circuit of the pulse power supply.
Furthermore, the pulse power supply main circuit comprises a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a first inductor, a second inductor, a third inductor, a fourth inductor, a first capacitor, a first output diode, a second output diode, a third output diode and a fourth output diode, wherein the first switch tube, the second switch tube, the first inductor and the first output diode form a first path of synchronous rectification Buck circuit; the third switching tube, the fourth switching tube, the second inductor and the second output diode form a second path of synchronous rectification Buck circuit; a fifth switching tube, a sixth switching tube, a third inductor and a third output diode form a third synchronous rectification Buck circuit; a seventh switching tube, an eighth switching tube, a fourth inductor and a fourth output diode form a fourth synchronous rectification Buck circuit; one end of an upper tube of the four-path synchronous rectification Buck circuit is connected to the anode of an input direct-current power supply, and the other end of the upper tube is connected with an inductor in series; one end of a lower tube of the four-path synchronous rectification Buck circuit is connected to a series point between the inductor and the upper tube, and the other end of the lower tube is connected to the negative pole of the input direct-current power supply, namely the lower tube is grounded; the positive pole of the output diode of the four-way synchronous rectification Buck circuit is connected with the other end of the inductor, and the negative pole of the output diode is connected with the positive pole of the gap; one end of each of the four inductors is connected with a common point of the upper and lower tubes, and the other ends of the four inductors are connected together and connected with the anode of the output diode, wherein the first inductor is reversely coupled with the second inductor, and the third inductor is reversely coupled with the fourth inductor; the first capacitor is connected in parallel with the input DC power supply.
Furthermore, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube adopt metal-oxide semiconductor field effect transistors.
Furthermore, the first output diode, the second output diode, the third output diode and the fourth output diode are all schottky diodes.
Further, the gap voltage detection circuit selects a resistance voltage division circuit.
Further, the gap current detection circuit selects a current hall sensor.
Furthermore, the FPGA controller selects an AX4010 series development board.
Furthermore, the driving circuit adopts a driving chip with isolated high-side and low-side dual-output.
A working method based on the electric spark pulse power supply comprises the following steps:
the method comprises the following steps: in the breakdown delay stage, the FPGA controller generates a PWM signal to control the first switch tube to be switched on, the other switch tubes are switched off, and at the moment, the first switch tube and the second switch tube form a single-path synchronous rectification Buck circuit to provide positive input voltage for the gap so that the gap can be broken down to form a discharge channel;
step two: after the gap is broken down, a discharge channel is formed, a gap discharge stage is started, the gap sampling voltage is lower than the upper limit of the threshold voltage, the FPGA controller generates PWM signals with saturated duty ratio to control the first switch tube, the third switch tube, the fifth switch tube and the seventh switch tube to be switched on; the second switching tube, the fourth switching tube, the sixth switching tube and the eighth switching tube are turned off, namely nonlinear control is carried out, at the moment, the inductor is in a coupling state, the equivalent inductor is minimum, and the gap current rapidly rises;
step three: when the discharge current reaches a current set value, the FPGA controller outputs a plurality of paths of PWM signals according to error signals of gap sampling current and the current set value during steady-state operation to control four paths of synchronous rectification Buck circuits to work in a staggered mode, the phase shift time among four paths of driving signals is equal, the total phase shift time is equal to the switching period in an adding mode, and therefore linear control is achieved; in the machining process, if abnormal discharge phenomena such as short circuit or arc discharge occur, the gap sampling voltage is lower than the lower limit V of the voltage threshold value L The FPGA controller generates a PWM signal with a saturated duty ratio to control the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube to be switched off, namely, the first switch tube, the second switch tube, the third switch tube, the fourth switch tube, the fifth switch tube, the sixth switch tube, the seventh switch tube and the eighth switch tube are subjected to nonlinear control, the discharge current is rapidly reduced, and the damage of abnormal discharge to the pulse power supply is reduced to the minimum;
step four: when the discharge duration reaches a time set value, the FPGA controller generates a PWM signal with a saturation duty ratio to control the second switching tube, the fourth switching tube, the sixth switching tube and the eighth switching tube to be switched on; the first switch tube, the third switch tube, the fifth switch tube and the seventh switch tube are turned off, namely, the nonlinear control is carried out. Entering a discharge tailing stage;
step five: after the gap current is reduced to zero, the FPGA controller controls all the switching tubes to be switched off, and the switching tubes enter a circuit deionization stage to prepare for discharging in the next period;
step six: and repeating the five steps to realize the cycle of the processing period.
Compared with the prior art, the invention has the following remarkable advantages: 1) the switching frequency of the circuit is equivalently improved by adopting a staggered parallel topological structure, the output current ripple is reduced, and the power density of the pulse power supply is improved; 2) the coupling inductor is adopted to replace the original independent inductor, and the reverse coupling mode reduces the equivalent inductance and improves the dynamic response capability and the energy efficiency of the system; 3) by adopting a linear and nonlinear control method, in one processing period, the FPGA controller flexibly switches linear control and nonlinear control, and the nonlinear control improves the dynamic response capability when the load suddenly changes; when the device operates in a steady state, the discharge current waveform is controllable through linear control, and the discharge energy is flexibly controlled.
Drawings
FIG. 1 is a block diagram of the interleaved parallel magnetic integrated spark pulse power supply system of the present invention.
FIG. 2 is a schematic view of a topology of the interleaved parallel magnetically integrated spark pulse power supply of the present invention.
FIG. 3 is a schematic diagram of a typical discharge waveform of the interleaved parallel magnetically integrated spark pulse power supply system of the present invention.
Fig. 4 is a schematic diagram of a current hall sensor of the present invention.
Fig. 5 is a schematic diagram of a driving circuit of the present invention.
Detailed Description
The invention is described in further detail below with reference to the accompanying drawings.
As shown in fig. 1, the interleaved parallel magnetic integrated electric spark pulse power supply based on linear nonlinear control provided by the invention comprises a direct current input power supply, a pulse power supply main circuit, a gap voltage detection circuit, a gap current detection circuit, a driving circuit and an FPGA controller, wherein the direct current power supply is used for supplying power to the pulse power supply main circuit; the pulse power supply main circuit is used for providing discharge energy; the voltage detection circuit and the current detection circuit are used for sampling the gap voltage and the gap discharge current; the FPGA controller generates a plurality of paths of PWM signals according to the voltage and current sampling signals; the driving circuit is used for filtering and amplifying the PWM signal and controlling the on and off of a switching tube in the pulse power supply main circuit.
As shown in FIG. 2, the proposed linearly nonlinear controlled interleaved parallel magnetic integrated spark pulse power supply topology comprises a first switch tube Q 1 A second switch tube Q 2 And a third switching tube Q 3 And a fourth switching tube Q 4 The fifth switch tube Q 5 And a sixth switching tube Q 6 Seventh switch tube Q 7 The eighth switch tube Q 8 A first inductor L 1 A second inductor L 2 A third inductor L 3 A fourth inductor L 4 A first capacitor C p1 A first output diode D 1 A second output diode D 2 A third output diode D 3 A fourth output diode D 4 Wherein the first switch tube Q 1 A second switch tube Q 2 A first inductor L 1 A first output diode D 1 Forming a first path of synchronous rectification Buck circuit; third switch tube Q 3 And a fourth switching tube Q 4 A second inductor L 2 A second output diode D 2 Forming a second path of synchronous rectification Buck circuit; fifth switch tube Q 5 And a sixth switching tube Q 6 A third inductor L 3 A third output diode D 3 Forming a third synchronous rectification Buck circuit; seventh switch tube Q 7 The eighth switch tube Q 8 A fourth inductor L 4 A fourth output diode D 4 Forming a fourth path of synchronous rectification Buck circuit; one end of an upper tube of the four-path synchronous rectification Buck circuit is connected to the anode of an input direct-current power supply, and the other end of the upper tube is connected with an inductor in series; one end of a lower tube of the four-path synchronous rectification Buck circuit is connected to a series point between the inductor and the upper tube, and the other end of the lower tube is connected to the negative pole of the input direct-current power supply, namely the lower tube is grounded; the positive pole of the output diode of the four-way synchronous rectification Buck circuit is connected with the other end of the inductor, and the negative pole of the output diode is connected with the positive pole of the gap; four inductors L 1 、L 2 、L 3 And L 4 One end of the first inductor is connected with the common point of the upper and lower tubes, and the other end is connected with the anode of the output diode, wherein the first inductor L 1 And a second inductance L 2 Reverse coupling, third inductance L 3 And a fourth inductance L 4 Reverse coupling; a first capacitor C p1 And is connected in parallel with the input dc power supply.
First switch tube Q in pulse power supply main circuit 1 A second switch tube Q 2 And a third switching tube Q 3 And a fourth switching tube Q 4 The fifth switch tube Q 5 The first stepSix switch tube Q 6 Seventh switch tube Q 7 And an eighth switching tube Q 8 The metal-oxide semiconductor field effect transistor is adopted, and particularly an N-channel MOSFET with the model number of IPP60R074C6 and the withstand voltage V of the N-channel MOSFET is selected from Infineon company DS Up to 600V, current capacity I D At 57.7A, the on-resistance is low, and the switching and on-losses are low. The device is suitable for application occasions of medium and high power with high frequency and large current. First output diode D 1 A second output diode D 2 A third output diode D 3 A fourth output diode D 4 The method adopts a Schottky diode, specifically adopts the Schottky diode of the model FFP30S60S of ON Semiconductor company, and the reverse repeat peak voltage V thereof RRM Up to 600V, average forward current I F(AV) At 30A, the switching speed is less than 40ns, and its low stored charge and ultra-fast soft recovery weaken the electrical noise in the circuit and reduce power consumption.
In order to accurately sample the gap current and the gap voltage in real time, a proper current and voltage detection circuit is also needed. The current sampling circuit selects a current Hall sensor which is provided by Allegro company and has the model number of ACS732KLATR-40AB-T, and FIG. 3 is a typical application schematic diagram of the current Hall sensor. The maximum current range of the detection can reach plus-minus 40A, the bandwidth is 1MHz, the sensitivity of the detection current is 50mV/A, the linearity is very good, the primary on-resistance is 1m omega, and the loss is low. And the chip also contains overcurrent protection and programmable functions. The voltage detection circuit adopts a traditional resistance voltage division circuit, and is simple and reliable.
The digital control module is realized by a field programmable gate array FPGA. The logic operation is realized through the hardware description language, the biggest characteristic is that the logic operation can be carried out in parallel, and the industrial application is very wide. And an FPGA integrated development module AX4010 of ALINX company is selected by comprehensively considering resource requirements. The corresponding sampling module is an ALINX9226 module matched with an FPGA development board of an AX4010 model by ALINX company. The FPGA-based multi-channel PWM control circuit comprises two sampling channels, sampling signals pass through an SMA interface, data after digital-to-analog conversion are obtained through a high-speed AD sampling chip and are finally transmitted to an FPGA control module, the FPGA completes corresponding algorithm design according to power supply and processing requirements, a plurality of paths of PWM control signals are output to a driving circuit, and then the switching-on and switching-off of a switching tube in the circuit are controlled.
The driver circuit may be selected from a high-side and low-side dual-output driver chip with isolation, and fig. 4 is a schematic diagram of an application of the driver circuit in the present invention, which uses a gate driver IC chip model UCC21521 from Texas Instruments with a bandwidth of up to 5MHz, and may be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time. All supply voltage pins have under-voltage lockout protection. The chip also contains an enable pin for turning off the output as a fail-safe measure. These excellent characteristics allow high efficiency, high power density and robustness in power module applications.
In conclusion, the interleaved parallel magnetic integrated spark pulse power supply topology provided by the invention adopts the coupling inductor to replace the discrete inductor, and selects the reverse coupling mode, so that the equivalent inductor is reduced, and the dynamic response speed of the converter is improved; the multi-path staggered parallel topology structure can equivalently improve the switching frequency, properly increase the bandwidth of the converter, and effectively reduce the output current ripple by staggered superposition of the multi-path inductive current.
Fig. 5 is a typical gap voltage and current waveform diagram for a complete machining cycle of spark forming, which is divided into three phases: breakdown delay period t delay And a discharge stage t on And a deionization phase t off . In the breakdown delay stage, the gap is in an insulation state, the gap current is 0, and the gap voltage is equal to the open-circuit voltage v open (ii) a After the gap breakdown, the discharge stage is entered, and the gap voltage is reduced from the original open circuit voltage to the maintaining voltage v dis At this time, the peak value of the discharge current is I d_peak (ii) a After the discharge is finished, the deionization stage is started, and the gap voltage and the gap current are both reduced to 0.
In a complete processing period, the FPGA controller flexibly switches linear control and nonlinear control, and the nonlinear control improves the dynamic response capability when the load suddenly changes; when the device operates in a steady state, the discharge current waveform is controllable through linear control, and the discharge energy is flexibly controlled. The specific implementation process is as follows:
the method comprises the following steps: in the breakdown delay stage, the FPGA controller generates a PWM signal to control the first switch tube Q 1 Is switched on, the other switch tubes are switched off, and then the switch tube is switched off by Q 1 、Q 2 A single-path synchronous rectification Buck circuit is formed to provide a forward input voltage to the gap so that the gap can break down to form a discharge channel.
Step two: when the gap is broken down, a discharge channel is formed and enters a gap discharge stage, and the gap sampling voltage is lower than the upper limit V of the voltage threshold value H The FPGA controller generates a PWM signal with a saturation duty ratio (the duty ratio is equal to 1) to control the first switching tube Q 1 And a third switching tube Q 3 The fifth switch tube Q 5 Seventh switch tube Q 7 Opening; second switch tube Q 2 And a fourth switching tube Q 4 And a sixth switching tube Q 6 The eighth switch tube Q 8 And (4) turning off, namely nonlinear control. At the moment, the inductor is in a coupling state, the equivalent inductor is minimum, and the gap current rapidly rises.
Step three: when the discharge current reaches the current set value I d_peak In time, the FPGA controller samples current and current set value I according to the interval during steady-state operation d_peak The error signal output multi-channel PWM signal controls the four-channel synchronous rectification Buck circuit to work in a staggered mode, the phase shift time among the four driving signals is equal, the total phase shift time is equal to the switching period in an adding mode, and therefore linear control is achieved. In the machining process, if abnormal discharge phenomena such as short circuit or arc discharge occur, the gap sampling voltage is lower than the lower limit V of the voltage threshold value L The FPGA controller generates a PWM signal with a saturation duty ratio (the duty ratio is equal to 0) to control the first switching tube Q 1 A second switch tube Q 2 And a third switching tube Q 3 And a fourth switching tube Q 4 The fifth switch tube Q 5 And a sixth switching tube Q 6 Seventh switch tube Q 7 The eighth switch tube Q 8 And (4) turning off, namely nonlinear control. The discharge current drops rapidly, minimizing the damage to the pulsed power supply from abnormal discharges.
Step four: when the discharge is continuedTime t s (pulse width) reaching the time set value t L In time, the FPGA controller generates a PWM signal with a saturation duty ratio (the duty ratio is equal to 0) to control the second switch tube Q 2 And a fourth switching tube Q 4 And a sixth switching tube Q 6 The eighth switch tube Q 8 Opening; first switch tube Q 1 And a third switching tube Q 3 The fifth switch tube Q 5 Seventh switch tube Q 7 And (4) turning off, namely nonlinear control. At this point the discharge tail phase is entered.
Step five: since the electrolyte insulation in the spark forming process is high, external deionization is not required. After the gap current is reduced to zero, the FPGA controller controls all the switching tubes to be switched off, and the circuit enters a deionization stage to prepare for discharging in the next period.
Step six: and repeating the five steps to realize the cycle of the processing period.
In summary, the voltage v is sampled according to the gap in different stages of a machining cycle in combination with the load characteristics of the electric discharge machining d Current i is sampled at intervals d And a pulse width count value t s And the FPGA controller flexibly selects linear control and nonlinear control. When the load suddenly changes, the converter is switched to the nonlinear control, and the optimal dynamic response of the converter can be realized. In the steady-state operation stage, the linear control is switched to, so that the steady-state performance of the pulse power supply main circuit can be improved, the flexible conversion of the discharge pulse width and the discharge current waveform is realized, and the controllability of the discharge energy is realized. The multi-path interleaving parallel circuit structure equivalently improves the switching frequency of the circuit, effectively reduces output current ripples, and reduces the capacity of an output filter.
Claims (7)
1. The staggered parallel magnetic integration electric spark pulse power supply based on linear nonlinear control is characterized by comprising a direct current input power supply, a pulse power supply main circuit, a gap voltage detection circuit, a gap current detection circuit, a driving circuit and an FPGA controller, wherein the direct current input power supply is used for supplying power to the pulse power supply main circuit; the pulse power supply main circuit is used for providing discharge energy; the voltage detection circuit and the current detection circuit are used for sampling the gap voltage and the gap discharge current to obtain voltage and current sampling signals; the FPGA controller generates a plurality of paths of PWM signals according to the voltage and current sampling signals; the driving circuit is used for filtering and amplifying the PWM signal and controlling the on-off of a switching tube in the pulse power supply main circuit;
the pulse power supply main circuit comprises a first switch tube (Q) 1 ) A second switch tube (Q) 2 ) And a third switching tube (Q) 3 ) And a fourth switching tube (Q) 4 ) And a fifth switching tube (Q) 5 ) And a sixth switching tube (Q) 6 ) A seventh switching tube (Q) 7 ) An eighth switching tube (Q) 8 ) A first inductor (L) 1 ) A second inductor (L) 2 ) A third inductor (L) 3 ) A fourth inductor (L) 4 ) A first capacitor (C) p1 ) A first output diode (D) 1 ) A second output diode (D) 2 ) A third output diode (D) 3 ) And a fourth output diode (D) 4 ) Wherein the first switch tube (Q) 1 ) A second switch tube (Q) 2 ) A first inductor (L) 1 ) A first output diode (D) 1 ) Forming a first path of synchronous rectification Buck circuit; third switch tube (Q) 3 ) And a fourth switching tube (Q) 4 ) A second inductor (L) 2 ) A second output diode (D) 2 ) Forming a second path of synchronous rectification Buck circuit; fifth switch tube (Q) 5 ) And a sixth switching tube (Q) 6 ) A third inductor (L) 3 ) A third output diode (D) 3 ) Forming a third synchronous rectification Buck circuit; seventh switch tube (Q) 7 ) And an eighth switching tube (Q) 8 ) A fourth inductor (L) 4 ) And a fourth output diode (D) 4 ) Forming a fourth path of synchronous rectification Buck circuit; one end of an upper tube of the four-path synchronous rectification Buck circuit is connected to the anode of an input direct-current power supply, and the other end of the upper tube is connected with an inductor in series; one end of a lower tube of the four-path synchronous rectification Buck circuit is connected to a series point between the inductor and the upper tube, and the other end of the lower tube is connected to the negative pole of the direct-current input power supply, namely the lower tube is grounded; the positive pole of the output diode of the four-way synchronous rectification Buck circuit is connected with the other end of the inductor, and the negative pole of the output diode is connected with the positive pole of the gap; one end of each inductor is connected with the common point of the upper and lower tubes, the other end is connected with the anode of the output diode,wherein the first inductance (L) 1 ) And a second inductance (L) 2 ) Reverse coupled, third inductance (L) 3 ) And a fourth inductance (L) 4 ) Reverse coupling; a first capacitor (C) p1 ) The DC input power supply is connected in parallel;
the working method of the electric spark pulse power supply comprises the following steps:
the method comprises the following steps: in the breakdown delay stage, the FPGA controller generates a PWM signal to control the first switch tube (Q) 1 ) The other switch tubes are switched on and switched off, and the first switch tube (Q) is used for switching on and switching off the other switch tubes 1 ) A second switch tube (Q) 2 ) A single-path synchronous rectification Buck circuit is formed to provide positive input voltage for the gap, so that the gap can be broken down to form a discharge channel;
step two: when the gap is broken down, a discharge channel is formed and enters a gap discharge stage, and the gap sampling voltage is lower than the upper limit of the threshold voltage (V) H ) The FPGA controller generates a PWM signal with a saturated duty ratio to control the first switch tube (Q) 1 ) And a third switching tube (Q) 3 ) And a fifth switching tube (Q) 5 ) And a seventh switching tube (Q) 7 ) Opening; second switch tube (Q) 2 ) And a fourth switching tube (Q) 4 ) And a sixth switching tube (Q) 6 ) And an eighth switching tube (Q) 8 ) Turning off, namely nonlinear control, wherein the first inductor, the second inductor, the third inductor, the fourth inductor and the fourth inductor are in a coupling state, the equivalent inductance is minimum, and the gap current rapidly rises;
step three: when the discharge current reaches the current set value (I) d_peak ) In time, the FPGA controller samples the current and the current set value (I) according to the interval during steady-state operation d_peak ) The error signal output multi-channel PWM signal controls four-channel synchronous rectification Buck circuit to work in a staggered mode, phase shift time among four driving signals is equal, total phase shift time is equal to a switching period, and if short circuit or abnormal arc discharge occurs in the machining process, gap sampling voltage is lower than a lower voltage threshold limit (V) L ) The FPGA controller generates a PWM signal with a saturated duty ratio to control the first switch tube (Q) 1 ) A second switch tube (Q) 2 ) And a third switching tube (Q) 3 ) And a fourth switching tube (Q) 4 ) And a fifth switching tube (Q) 5 ) The first stepSix switch tubes (Q) 6 ) And a seventh switching tube (Q) 7 ) And an eighth switching tube (Q) 8 ) The power supply is turned off, the discharge current is rapidly reduced, and the damage of abnormal discharge to the pulse power supply is reduced to the minimum;
step four: when discharge duration (t) s ) Reach the set time value (t) L ) The FPGA controller generates a PWM signal with saturated duty ratio to control a second switch tube (Q) 2 ) And a fourth switching tube (Q) 4 ) And a sixth switching tube (Q) 6 ) And an eighth switching tube (Q) 8 ) Opening; first switch tube (Q) 1 ) And a third switching tube (Q) 3 ) And a fifth switch tube (Q) 5 ) And a seventh switching tube (Q) 7 ) Turning off, namely, performing nonlinear control and entering a discharge tailing stage;
step five: after the gap current is reduced to zero, the FPGA controller controls all the switching tubes to be switched off, and the switching tubes enter a circuit deionization stage to prepare for discharging in the next period;
step six: and repeating the steps from one to five to realize the circulation of the processing period.
2. Linearly non-linearly controlled interleaved magnetically integrated spark-pulse power supply according to claim 1 characterized in that said first switching tube (Q) 1 ) A second switch tube (Q) 2 ) And a third switching tube (Q) 3 ) And a fourth switching tube (Q) 4 ) And a fifth switching tube (Q) 5 ) And a sixth switching tube (Q) 6 ) And a seventh switching tube (Q) 7 ) And an eighth switching tube (Q) 8 ) A metal-oxide semiconductor field effect transistor is used.
3. Linearly non-linearly controlled interleaved magnetically integrated spark pulse power supply according to claim 1 characterized in that said first output diode (D) is connected to said first output diode (D) 1 ) A second output diode (D) 2 ) A third output diode (D) 3 ) And a fourth output diode (D) 4 ) Schottky diodes are used.
4. The linearly nonlinear-controlled interleaved magnetically integrated spark pulse power supply of claim 1 wherein said gap voltage detection circuit selects a resistive divider circuit.
5. The linearly nonlinear-controlled interleaved magnetically integrated spark pulse power supply of claim 1 wherein said gap current sensing circuit selects a current hall sensor.
6. The linearly nonlinear-controlled interleaved parallel magnetically integrated spark pulse power supply of claim 1 wherein said FPGA controller is selected from an AX4010 series development board.
7. The linear nonlinear control interleaved magnetic integrated spark pulse power supply as claimed in claim 1, wherein the driving circuit employs a driving chip with isolated high-side and low-side dual output.
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| CN113472233A (en) * | 2021-06-25 | 2021-10-01 | 中国电子科技集团公司第十八研究所 | Magnetic integration high-power pulse current source |
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