CN111312171B - Pixel driving circuit, OLED display panel and display device - Google Patents
Pixel driving circuit, OLED display panel and display device Download PDFInfo
- Publication number
- CN111312171B CN111312171B CN202010135394.7A CN202010135394A CN111312171B CN 111312171 B CN111312171 B CN 111312171B CN 202010135394 A CN202010135394 A CN 202010135394A CN 111312171 B CN111312171 B CN 111312171B
- Authority
- CN
- China
- Prior art keywords
- thin film
- film transistor
- node
- electrically connected
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of El Displays (AREA)
Abstract
The application discloses a pixel driving circuit, an OLED display panel and a display device. The pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode. According to the embodiment of the application, the data voltage of the AMOLED panel can be remarkably reduced through the novel 4T2C pixel driving circuit structure, so that the dynamic power consumption is reduced, and the purpose of reducing the total power consumption is finally achieved.
Description
Technical Field
The application relates to the technical field of display, in particular to a pixel driving circuit, an OLED display panel and a display device.
Background
Since the performance of an OLED device and a Thin Film Transistor (TFT) device is closely related to the temperature of the panel, if the device characteristics change, the display screen is easily abnormal. Therefore, it is very important to reduce the overall power consumption of the panel.
Since the 2T1C pixel circuit of the general-purpose organic light emitting diode has a high data signal voltage, the dynamic power consumption of the panel is large, which is not favorable for the practical use of the display panel. The invention provides a pixel circuit which can remarkably reduce the data voltage of an organic light-emitting diode panel, thereby reducing the dynamic power consumption and finally achieving the purpose of reducing the total power consumption.
Disclosure of Invention
The embodiment of the application provides a pixel driving circuit, an OLED display panel and a display device, which can remarkably reduce the data voltage of the OLED panel, thereby reducing the dynamic power consumption and finally achieving the purpose of reducing the total power consumption.
The embodiment of the application provides a pixel driving circuit, which comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source thereof is electrically connected to the anode of the organic light emitting diode, and the drain thereof is electrically connected to a positive power supply Voltage (VDD); the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node; the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with a power supply negative Voltage (VSS), and the drain electrode of the third thin film transistor is electrically connected to a second node; a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal; one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node; the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire.
In some embodiments, the timing of the second row scan signal WR2 is different from the timing of the first row scan signal WR1, but the number of the peripheral driving signals is not increased, and only one of the traces of the previous row scan signal is pulled to control the timing of the driving signals by the respective switches when the pixel is wired.
In some embodiments, the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are low-temperature polysilicon thin film transistors, and the low-temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
In some embodiments, the operation of the pixel driving circuit switching from the low gray level to the high gray level is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V1 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V1, at this time, the potential of the first node is raised by (V1-V2) × C2/(C1+ C2), becoming: v1+ [ (V1-V2) × C2/(C1+ C2) ], wherein V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the high gray scale, the data voltage of the second node is increased from V1 to V3, and the potential of the first node is increased by (V3-V1) C2/(C1+ C2) to become V1+ [ (V1-V2) C2/(C1+ C2) ] + [ (V3-V1) C2/(C1+ C2) ].
In some embodiments, the operation of the pixel driving circuit switching from the high gray level to the low gray level is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are reset to be V3 and V2 respectively.
When the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V3, at this time, the potential of the first node is raised by (V3-V2) × C2/(C1+ C2), and becomes: [ (V3-V2) × C2/(C1+ C2) ] + V3, wherein V3-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the low gray scale, the data voltage of the second node is reduced from V3 to V1, and the potential of the first node is reduced by (V3-V1) C2/(C1+ C2) to [ (V3-V2) C2/(C1+ C2) ] + V3- [ (V3-V1) C2/(C1+ C2) ].
Therefore, the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the purpose of reducing the total power consumption.
The embodiment of the application also provides an OLED display panel, which comprises a pixel driving circuit, wherein the pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source thereof is electrically connected to the anode of the organic light emitting diode, and the drain thereof is electrically connected to a positive power supply Voltage (VDD); the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node; the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with a power supply negative Voltage (VSS), and the drain electrode of the third thin film transistor is electrically connected to a second node; a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal; one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node; the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire; the second row of scanning signals and the first row of scanning signals have different time sequences, but the number of peripheral driving signals is not increased additionally, and only one of the wires is pulled to control the time sequence of the driving signals through individual switches from the wires of the scanning signals of the previous row when pixel wiring is carried out.
In some embodiments, the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor of the OLED display panel are low-temperature polysilicon thin film transistors, and the low-temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
In some embodiments, the operation of switching the pixel driving circuit of the OLED display panel from a low gray scale to a high gray scale is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V1 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V1, at this time, the potential of the first node is raised by (V1-V2) × C2/(C1+ C2), becoming: v1+ [ (V1-V2) × C2/(C1+ C2) ], wherein V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the high gray scale, the data voltage of the second node is increased from V1 to V3, and the potential of the first node is increased by (V3-V1) C2/(C1+ C2) to become V1+ [ (V1-V2) C2/(C1+ C2) ] + [ (V3-V1) C2/(C1+ C2) ].
In some embodiments, the operation of switching the pixel driving circuit of the OLED display panel from a high gray scale to a low gray scale is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V3 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V3, at this time, the potential of the first node is raised by (V3-V2) × C2/(C1+ C2), and becomes: [ (V3-V2) × C2/(C1+ C2) ] + V3, wherein V3-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the low gray scale, the data voltage of the second node is reduced from V3 to V1, and the potential of the first node is reduced by (V3-V1) C2/(C1+ C2) to [ (V3-V2) C2/(C1+ C2) ] + V3- [ (V3-V1) C2/(C1+ C2) ].
Therefore, the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the purpose of reducing the total power consumption.
The embodiment of the present application further provides a display device, which includes the display panel, where the display panel includes a pixel driving circuit, and the pixel driving circuit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor, and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source thereof is electrically connected to the anode of the organic light emitting diode, and the drain thereof is electrically connected to a positive power supply Voltage (VDD); the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node; the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with a power supply negative Voltage (VSS), and the drain electrode of the third thin film transistor is connected to a second node; a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal; one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node; the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire; the second row of scanning signals and the first row of scanning signals have different time sequences, but the number of peripheral driving signals is not increased additionally, and only one of the wires is pulled to control the time sequence of the driving signals through individual switches from the wires of the scanning signals of the previous row when pixel wiring is carried out.
In some embodiments, the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor of the display device are low-temperature polysilicon thin film transistors, and the low-temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
In some embodiments, the operation of switching the pixel driving circuit of the display device from a low gray scale to a high gray scale is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V1 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V1, at this time, the potential of the first node is raised by (V1-V2) × C2/(C1+ C2), becoming: v1+ [ (V1-V2) × C2/(C1+ C2) ], wherein V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the high gray scale, the data voltage of the second node is increased from V1 to V3, and the potential of the first node is increased by (V3-V1) C2/(C1+ C2) to become V1+ [ (V1-V2) C2/(C1+ C2) ] + [ (V3-V1) C2/(C1+ C2) ].
In some embodiments, the operation of switching the pixel driving circuit of the display device from a high gray scale to a low gray scale is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V3 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V3, at this time, the potential of the first node is raised by (V3-V2) × C2/(C1+ C2), and becomes: [ (V3-V2) × C2/(C1+ C2) ] + V3, wherein V3-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the low gray scale, the data voltage of the second node is reduced from V3 to V1, and the potential of the first node is reduced by (V3-V1) C2/(C1+ C2) to [ (V3-V2) C2/(C1+ C2) ] + V3- [ (V3-V1) C2/(C1+ C2) ].
Therefore, the pixel design structure can reduce the dynamic power consumption of the pixel driving circuit, and finally achieve the purpose of reducing the total power consumption.
The embodiment of the application provides a pixel driving circuit, which comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source thereof is electrically connected to the anode of the organic light emitting diode, and the drain thereof is electrically connected to a positive power supply Voltage (VDD); the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node; the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with a power supply negative Voltage (VSS), and the drain electrode of the third thin film transistor is electrically connected to a second node; a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal; one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node; the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire; the second line scanning signal has a different timing from the first line scanning signal. According to the embodiment of the application, the data voltage of the OLED panel can be remarkably reduced through the 4T2C pixel driving circuit structure, so that the dynamic power consumption is reduced, and the purpose of reducing the total power consumption is finally achieved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram illustrating a working process of the pixel driving circuit structure of the present application when the low gray scale is switched to the high gray scale.
Fig. 3 is a schematic diagram illustrating a working process of the pixel driving circuit structure of the present application when the high gray scale is switched to the low gray scale.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
Specifically, referring to fig. 1, in the pixel driving circuit provided in the embodiment of the present application, each pixel has a 4T2C pixel structure, and the 4T2C pixel structure includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first storage capacitor C1, a second storage capacitor C2, and an organic light emitting diode OLED.
The first thin film transistor T1 has a gate electrically connected to the first node G, a source electrically connected to the anode S of the organic light emitting diode OLED, and a drain electrically connected to the positive power voltage VDD.
The gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second Data signal line Data2, and the drain thereof is electrically connected to the first node G.
The third thin film transistor T3 has a gate connected to the first row scanning signal WR1, a source connected to VSS, and a drain connected to the second node M.
The gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, the source thereof is electrically connected to the second node M, and the drain thereof is connected to the first Data signal line Data 1.
One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND 1.
One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end thereof is electrically connected to the first node G.
The anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND 2.
The timing sequence of the second row scanning signal WR2 is different from that of the first row scanning signal WR1, but the number of peripheral driving signals is not increased, and only one of the lines is pulled from the previous row scanning signal line to control the timing sequence of the driving signals through individual switches when the pixel wiring is performed.
During driving, first, the first row scanning signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to be turned on, the second Data signal Data2 enters the gate of the first thin film transistor T1, the first storage capacitor C1 and the second storage capacitor C2 through the second thin film transistor T2, and then the first thin film transistor T1 is turned on, and the organic light emitting diode OLED emits light. Secondly, when the first row scanning signal WR1 is turned off, the second thin film transistor T2 and the third thin film transistor T3 are turned off, and simultaneously, the second row scanning signal WR2 is turned on, the fourth thin film transistor T4 is turned on, the first Data signal Data1 is written into the second node M, and due to the storage function of the first storage capacitor C1 and the second storage capacitor C2, the gate voltage of the first thin film transistor T1 can still keep the Data signal voltage, so that the first thin film transistor T1 is in a conducting state, and the driving current enters the organic light emitting diode OLED through the first thin film transistor T1 to drive the organic light emitting diode OLED to emit light.
In the structure of the present application, the first storage capacitor C1 is electrically connected to the second storage capacitor C2 at the first node G, which is beneficial to keep the voltage at the first node G balanced and stably supply the data signal to T1.
As shown in fig. 2, the process of switching the pixel from the low gray level to the high gray level is as follows:
in stage 1, the first row scan signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, the voltage of the second Data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset to 1 volt and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 to 1 volt, at this time, the potential of the first node G is raised by 11 × C2/(C1+ C2), and therefore, the potential of the first node G is 1+11 × C2/(C1+ C2);
in stage 3, the second line scan signal WR2 keeps high, the frame is switched from low to high gray, the data signal is raised from 1 volt to 10 volts, and at this time, the potential of the first node G is raised by 9 × C2/(C1+ C2), so the potential of the first node G is 1+20 × C2/(C1+ C2), and the current of the organic light emitting diode OLED is 1.5 μ a.
As shown in FIG. 3, the process of switching the pixel from the high gray level to the low gray level is as follows:
in stage 1, the first row scanning signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 volts to 10 volts, at this time, the potential of the first node G is raised by 20 × C2/(C1+ C2), and therefore, the potential of the first node G is [20 × C2/(C1+ C2) ] -10;
in stage 3, the second line scan signal WR2 keeps maintaining high level, the frame is switched from high level to low level, the data signal is decreased from 10 v to 1 v, and the potential of the first node G is decreased by 9 × C2/(C1+ C2), so the potential of the first node G is [11 × C2/(C1+ C2) ] -10, the current of the organic light emitting diode OLED is 200nA, and the frame displays low level.
And the dynamic power consumption I of the data line is fcVdata 2And the dynamic power consumption of the panel is reduced by more than half.
In some embodiments, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
The embodiment of the application also provides an OLED display panel, which includes a pixel driving circuit, referring to fig. 1, in the pixel driving circuit, each pixel has a 4T2C pixel structure, and the 4T2C pixel structure includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first storage capacitor C1, a second storage capacitor C2, and an organic light emitting diode OLED.
The first thin film transistor T1 has a gate electrically connected to the first node G, a source electrically connected to the anode S of the organic light emitting diode OLED, and a drain electrically connected to the positive power voltage VDD.
The gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second Data signal line Data2, and the drain thereof is electrically connected to the first node G.
The gate of the third tft T3 is connected to the first row scanning signal WR1, the source thereof is connected to the power negative voltage VSS, and the drain thereof is connected to the second node M.
The gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, the source thereof is electrically connected to the second node M, and the drain thereof is connected to the first Data signal line Data 1.
One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND 1.
One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end thereof is electrically connected to the first node G.
The anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND 2.
The timing sequence of the second row scanning signal WR2 is different from that of the first row scanning signal WR1, but the number of peripheral driving signals is not increased, and only one of the lines is pulled from the previous row scanning signal line to control the timing sequence of the driving signals through individual switches when the pixel wiring is performed.
During driving, first, the first row scanning signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to be turned on, the second Data signal Data2 enters the gate of the first thin film transistor T1, the first storage capacitor C1 and the second storage capacitor C2 through the second thin film transistor T2, then the first thin film transistor T1 is turned on, and the organic light emitting diode OLED emits light. Secondly, when the first row scanning signal WR1 is turned off, the second thin film transistor T2 and the third thin film transistor T3 are turned off, and at the same time, when the second row scanning signal WR2 is turned on, the fourth thin film transistor T4 is turned on, the first Data signal Data1 is written into the second node M, due to the storage function of the first storage capacitor C1 and the second storage capacitor C2, the gate voltage of the first thin film transistor T1 can still keep the Data signal voltage, so that the first thin film transistor T1 is in a conducting state, and the driving current enters the organic light emitting diode OLED through the first thin film transistor T1 to drive the organic light emitting diode OLED to emit light.
In the structure of the present application, the first storage capacitor C1 is electrically connected to the second storage capacitor C2 at the first node G, which is beneficial to keep the voltage at the first node G balanced and stably supply the data signal to T1.
As shown in fig. 2, the process of switching the pixel from the low gray level to the high gray level is as follows:
in stage 1, the first row scan signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, the voltage of the second Data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset to 1 volt and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 volts to 1 volt, at this time, the potential of the first node G is raised by 11 × C2/(C1+ C2), and therefore, the potential of the first node G is 1+11 × C2/(C1+ C2);
in stage 3, the second line scan signal WR2 keeps high, the frame is switched from low to high gray, the data signal is raised from 1 volt to 10 volts, and at this time, the potential of the first node G is raised by 9 × C2/(C1+ C2), so the potential of the first node G is 1+20 × C2/(C1+ C2), and the current of the organic light emitting diode OLED is 1.5 μ a.
As shown in FIG. 3, the process of switching the pixel from the high gray level to the low gray level is as follows:
in stage 1, the first row scanning signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 volts to 10 volts, at this time, the potential of the first node G is raised by 20 × C2/(C1+ C2), and therefore, the potential of the first node G is [20 × C2/(C1+ C2) ] -10;
in stage 3, the second line scan signal WR2 keeps maintaining high level, the frame is switched from high level to low level, the data signal is decreased from 10 v to 1 v, and the potential of the first node G is decreased by 9 × C2/(C1+ C2), so the potential of the first node G is [11 × C2/(C1+ C2) ] -10, the current of the organic light emitting diode OLED is 200nA, and the frame displays low level.
And, the dynamic power consumption I of the data line is fCVdata 2Here, f is the refresh rate of the panel, and C is the capacitance of the panel, and it can be seen that the dynamic power consumption of the panel is reduced by more than half.
In some embodiments, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
An embodiment of the present application further provides a display device, including the above display panel, where the display panel includes a pixel driving circuit, referring to fig. 1, in the pixel driving circuit, each pixel has a 4T2C pixel structure, and the 4T2C pixel structure includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a first storage capacitor C1, a second storage capacitor C2, and an organic light emitting diode OLED.
The first thin film transistor T1 has a gate electrically connected to the first node G, a source electrically connected to the anode S of the organic light emitting diode OLED, and a drain electrically connected to the positive power voltage VDD.
The gate of the second thin film transistor T2 is connected to the first row scan signal WR1, the source thereof is connected to the second Data signal line Data2, and the drain thereof is electrically connected to the first node G.
The gate of the third tft T3 is connected to the first row scanning signal WR1, the source thereof is connected to the power negative voltage VSS, and the drain thereof is connected to the second node M.
The gate of the fourth thin film transistor T4 is connected to the second row scan signal WR2, the source thereof is electrically connected to the second node M, and the drain thereof is connected to the first Data signal line Data 1.
One end of the first storage capacitor C1 is electrically connected to the first node G, and the other end thereof is electrically connected to the first ground line GND 1.
One end of the second storage capacitor C2 is electrically connected to the second node M, and the other end thereof is electrically connected to the first node G.
The anode S of the organic light emitting diode OLED is electrically connected to the source of the first thin film transistor T1, and the cathode thereof is electrically connected to the second ground line GND 2.
WR2 is different from the timing of the first row scanning signal WR1, but the number of peripheral driving signals is not increased, and only one of the wirings is pulled from the previous row scanning signal wiring to control the timing of the driving signals by individual switches when the pixel wiring is performed.
During driving, first, the first row scanning signal WR1 controls the third thin film transistor T3 and the second thin film transistor T2 to be turned on, the second Data signal Data2 enters the gate of the first thin film transistor T1, the first storage capacitor C1 and the second storage capacitor C2 through the second thin film transistor T2, then the first thin film transistor T1 is turned on, and the organic light emitting diode OLED emits light. Secondly, when the first row scanning signal WR1 is turned off, the second thin film transistor T2 and the third thin film transistor T3 are turned off, and at the same time, when the second row scanning signal WR2 is turned on, the fourth thin film transistor T4 is turned on, the first Data signal Data1 is written into the second node M, due to the storage function of the first storage capacitor C1 and the second storage capacitor C2, the gate voltage of the first thin film transistor T1 can still keep the Data signal voltage, so that the first thin film transistor T1 is in a conducting state, and the driving current enters the organic light emitting diode OLED through the first thin film transistor T1 to drive the organic light emitting diode OLED to emit light.
In the structure of the present application, the first storage capacitor C1 is electrically connected to the second storage capacitor C2 at the first node G, which is beneficial to keep the voltage at the first node G balanced and stably supply the data signal to T1.
As shown in fig. 2, the process of switching the pixel from the low gray level to the high gray level is as follows:
in stage 1, the first row scan signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, the voltage of the second Data signal Data2 is 15 volts, and the potentials of the first node G and the second node M are reset to 1 volt and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 volts to 1 volt, at this time, the potential of the first node G is raised by 11 × C2/(C1+ C2), and therefore, the potential of the first node G is 1+11 × C2/(C1+ C2);
in stage 3, the second line scan signal WR2 keeps high, the frame is switched from low to high gray, the data signal is raised from 1 volt to 10 volts, and at this time, the potential of the first node G is raised by 9 × C2/(C1+ C2), so the potential of the first node G is 1+20 × C2/(C1+ C2), and the current of the organic light emitting diode OLED is 1.5 μ a.
As shown in FIG. 3, the process of switching the pixel from the high gray level to the low gray level is as follows:
in stage 1, the first row scanning signal WR1 is raised to a high level, the third tft T3 and the second tft T2 are turned on, and the potentials of the first node G and the second node M are reset to 10 volts and-10 volts, respectively;
stage 2, the second row scan signal WR2 is raised to high potential, the first row scan signal WR1 is lowered to low potential, the first Data signal Data1 is written into the second node M, the potential of the second node M is raised from-10 volts to 10 volts, at this time, the potential of the first node G is raised by 20 × C2/(C1+ C2), and therefore, the potential of the first node G is [20 × C2/(C1+ C2) ] -10;
in stage 3, the second line scan signal WR2 keeps maintaining high level, the frame is switched from high level to low level, the data signal is decreased from 10 v to 1 v, and the potential of the first node G is decreased by 9 × C2/(C1+ C2), so the potential of the first node G is [11 × C2/(C1+ C2) ] -10, the current of the organic light emitting diode OLED is 200nA, and the frame displays low level.
And, the dynamic power consumption I of the data line is fCVdata 2Here, f is the refresh rate of the panel, and C is the capacitance of the panel, and it can be seen that the dynamic power consumption of the panel is reduced by more than half.
In some embodiments, the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3, and the fourth thin film transistor T4 are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are all P-type thin film transistors; or the first thin film transistor T1, the second thin film transistor T2, the third thin film transistor T3 and the fourth thin film transistor T4 are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
The embodiment of the application provides a pixel driving circuit, an OLED display panel and a display device, wherein the pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode; wherein the gate of the first thin film transistor is electrically connected to the first node, the source thereof is electrically connected to the anode of the organic light emitting diode, and the drain thereof is electrically connected to a positive power supply Voltage (VDD); the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node; the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with a power supply negative Voltage (VSS), and the drain electrode of the third thin film transistor is electrically connected to a second node; a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal; one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire; one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node; the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire; the second line scanning signal borrows the first line scanning signal. According to the embodiment of the application, the data voltage of the AMOLED panel can be remarkably reduced through the 4T2C pixel driving circuit structure, so that the dynamic power consumption is reduced, and the purpose of reducing the total power consumption is finally achieved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The pixel driving circuit, the OLED display panel, and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and implementations of the present application, and the description of the embodiments above is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A pixel driving circuit is characterized by comprising a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode;
the grid electrode of the first thin film transistor is electrically connected to a first node, the source electrode of the first thin film transistor is electrically connected to the anode of the organic light emitting diode, and the drain electrode of the first thin film transistor is electrically connected to VDD;
the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal, and the drain electrode of the second thin film transistor is electrically connected to the first node;
the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with VSS, and the drain electrode of the third thin film transistor is electrically connected to a second node;
a grid electrode of the fourth thin film transistor is connected with a second row scanning signal, a source electrode of the fourth thin film transistor is electrically connected to the second node, and a drain electrode of the fourth thin film transistor is connected with a first data signal;
one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire;
one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node;
the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire.
2. The pixel driving circuit according to claim 1, wherein a timing of the second row scan signal is different from a timing of the first row scan signal.
3. The pixel driving circuit according to claim 1, wherein the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are P-type thin film transistors; or the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
4. The pixel driving circuit as claimed in claim 2, wherein the switching from the low gray level to the high gray level is performed by:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V1 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V1, at this time, the potential of the first node is raised by (V1-V2) × C2/(C1+ C2), becoming: v1+ [ (V1-V2) × C2/(C1+ C2) ], wherein V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the high gray scale, the data voltage of the second node is increased from V1 to V3, and the potential of the first node is increased by (V3-V1) C2/(C1+ C2) to become V1+ [ (V1-V2) C2/(C1+ C2) ] + [ (V3-V1) C2/(C1+ C2) ].
5. The pixel driving circuit according to claim 4, wherein the operation of switching from the high gray level to the low gray level is as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V3 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V3, at this time, the potential of the first node is raised by (V3-V2) × C2/(C1+ C2), becoming: [ (V3-V2) × C2/(C1+ C2) ] + V3, wherein V3-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the low gray scale, the data voltage of the second node is reduced from V3 to V1, and the potential of the first node is reduced by (V3-V1) C2/(C1+ C2) to [ (V3-V2) C2/(C1+ C2) ] + V3- [ (V3-V1) C2/(C1+ C2) ].
6. An OLED display panel comprises a pixel driving circuit, and is characterized in that the pixel driving circuit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a first storage capacitor, a second storage capacitor and an organic light emitting diode;
the grid electrode of the first thin film transistor is electrically connected to a first node, the source electrode of the first thin film transistor is electrically connected to the anode of the organic light emitting diode, and the drain electrode of the first thin film transistor is electrically connected to VDD;
the grid electrode of the second thin film transistor is connected with a first row scanning signal, the source electrode of the second thin film transistor is connected with a second data signal line, and the drain electrode of the second thin film transistor is electrically connected to the first node;
the grid electrode of the third thin film transistor is connected with the first row scanning signal, the source electrode of the third thin film transistor is connected with VSS, and the drain electrode of the third thin film transistor is electrically connected to a second node;
the grid electrode of the fourth thin film transistor is connected with a second row scanning signal, the source electrode of the fourth thin film transistor is electrically connected to the second node, and the drain electrode of the fourth thin film transistor is connected with a first data signal line;
one end of the first storage capacitor is electrically connected to the first node, and the other end of the first storage capacitor is electrically connected to a first grounding wire;
one end of the second storage capacitor is electrically connected to the second node, and the other end of the second storage capacitor is electrically connected to the first node;
the anode of the organic light emitting diode is electrically connected to the source electrode of the first thin film transistor, and the cathode of the organic light emitting diode is electrically connected to a second grounding wire;
the second line scanning signal has a different timing from the first line scanning signal.
7. The OLED display panel of claim 6, wherein the first, second, third and fourth thin film transistors are low temperature polysilicon thin film transistors, and the low temperature polysilicon thin film transistors are P-type thin film transistors; or the first thin film transistor, the second thin film transistor, the third thin film transistor and the fourth thin film transistor are oxide thin film transistors, and the oxide thin film transistors are all N-type oxide thin film transistors.
8. The OLED display panel of claim 6, wherein the switching of the pixel driving circuit from a low gray level to a high gray level is performed by:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V1 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V1, at this time, the potential of the first node is raised by (V1-V2) × C2/(C1+ C2), becoming: v1+ [ (V1-V2) × C2/(C1+ C2) ], wherein V1-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the high gray scale, the data voltage of the second node is increased from V1 to V3, and the potential of the first node is increased by (V3-V1) C2/(C1+ C2) to become V1+ [ (V1-V2) C2/(C1+ C2) ] + [ (V3-V1) C2/(C1+ C2) ].
9. The OLED display panel of claim 8, wherein the switching of the pixel driving circuit from the high gray level to the low gray level is performed as follows:
when the pixel driving circuit works, when the first row scanning signal is at a high potential, the second thin film transistor and the third thin film transistor are turned on, and the potentials of the first node and the second node are respectively reset to be V3 and V2;
when the second row scanning signal is at high potential, the first row scanning signal is lowered to low potential, the first data signal is written into the second node, and the second node is raised from low potential V2 to high potential V3, at this time, the potential of the first node is raised by (V3-V2) × C2/(C1+ C2), becoming: [ (V3-V2) × C2/(C1+ C2) ] + V3, wherein V3-V2 is the potential difference of the second node, C2 is the capacitance value of the second storage capacitor, and C1 is the capacitance value of the first storage capacitor;
when the second row scanning signal is maintained at the high potential, the pixel driving circuit is switched from the low gray scale to the low gray scale, the data voltage of the second node is reduced from V3 to V1, and the potential of the first node is reduced by (V3-V1) C2/(C1+ C2) to [ (V3-V2) C2/(C1+ C2) ] + V3- [ (V3-V1) C2/(C1+ C2) ].
10. A display device comprising the OLED display panel according to any one of claims 6 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010135394.7A CN111312171B (en) | 2020-03-02 | 2020-03-02 | Pixel driving circuit, OLED display panel and display device |
| PCT/CN2020/084244 WO2021174643A1 (en) | 2020-03-02 | 2020-04-10 | Pixel driving circuit, oled display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010135394.7A CN111312171B (en) | 2020-03-02 | 2020-03-02 | Pixel driving circuit, OLED display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111312171A CN111312171A (en) | 2020-06-19 |
| CN111312171B true CN111312171B (en) | 2021-03-16 |
Family
ID=71162846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010135394.7A Active CN111312171B (en) | 2020-03-02 | 2020-03-02 | Pixel driving circuit, OLED display panel and display device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN111312171B (en) |
| WO (1) | WO2021174643A1 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342052A (en) * | 2017-08-18 | 2017-11-10 | 深圳市华星光电半导体显示技术有限公司 | Pixel-driving circuit for OLED display devices |
| CN109785800A (en) * | 2019-03-05 | 2019-05-21 | 北京大学深圳研究生院 | A microdisplay pixel circuit |
| TW201923726A (en) * | 2017-11-09 | 2019-06-16 | 日商半導體能源研究所股份有限公司 | Display device and working method thereof, and electronic device |
| CN110085161A (en) * | 2018-04-18 | 2019-08-02 | 友达光电股份有限公司 | Display panel and pixel circuit |
| CN110556076A (en) * | 2019-09-29 | 2019-12-10 | 福州京东方光电科技有限公司 | Pixel circuit, driving method and display device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101282996B1 (en) * | 2008-11-15 | 2013-07-04 | 엘지디스플레이 주식회사 | Organic electro-luminescent display device and driving method thereof |
| CN103150991A (en) * | 2013-03-14 | 2013-06-12 | 友达光电股份有限公司 | A pixel compensation circuit for AMOLED display |
| CN104050917B (en) * | 2014-06-09 | 2018-02-23 | 上海天马有机发光显示技术有限公司 | A kind of image element circuit, organic EL display panel and display device |
| CN104575389A (en) * | 2015-01-29 | 2015-04-29 | 京东方科技集团股份有限公司 | Pixel circuit, driving method of pixel circuit, display panel and display device |
| CN104821150B (en) * | 2015-04-24 | 2018-01-16 | 北京大学深圳研究生院 | Image element circuit and its driving method and display device |
| KR102390374B1 (en) * | 2015-06-24 | 2022-04-25 | 삼성전자주식회사 | pixel circuit, Method for driving the pixel circuit and Organic light emitting display |
-
2020
- 2020-03-02 CN CN202010135394.7A patent/CN111312171B/en active Active
- 2020-04-10 WO PCT/CN2020/084244 patent/WO2021174643A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107342052A (en) * | 2017-08-18 | 2017-11-10 | 深圳市华星光电半导体显示技术有限公司 | Pixel-driving circuit for OLED display devices |
| TW201923726A (en) * | 2017-11-09 | 2019-06-16 | 日商半導體能源研究所股份有限公司 | Display device and working method thereof, and electronic device |
| CN110085161A (en) * | 2018-04-18 | 2019-08-02 | 友达光电股份有限公司 | Display panel and pixel circuit |
| CN109785800A (en) * | 2019-03-05 | 2019-05-21 | 北京大学深圳研究生院 | A microdisplay pixel circuit |
| CN110556076A (en) * | 2019-09-29 | 2019-12-10 | 福州京东方光电科技有限公司 | Pixel circuit, driving method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2021174643A1 (en) | 2021-09-10 |
| CN111312171A (en) | 2020-06-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108364982B (en) | OLED display device | |
| CN107799062B (en) | A kind of pixel circuit and its driving method, display device | |
| EP3588480B1 (en) | Pixel driving circuit and driving method thereof, and layout structure of transistor | |
| CN109308872B (en) | Pixel circuit and display substrate | |
| CN111986612A (en) | Pixel driving circuit, driving method of pixel driving circuit and display panel | |
| CN107871471B (en) | Pixel driving circuit, driving method thereof and display device | |
| CN103988247B (en) | Display device and control method thereof | |
| CN105096818B (en) | Display device and its image element circuit, driving method | |
| CN113327556A (en) | Pixel circuit, driving method thereof and display panel | |
| CN111402814B (en) | Display panel, driving method of display panel and display device | |
| CN106128362B (en) | A kind of pixel circuit and display device | |
| TW201314656A (en) | Pixel circuit and driving method thereof | |
| CN111627976B (en) | Organic light emitting display device | |
| US11538405B2 (en) | Pixel driving circuit, pixel driving method, display panel and display device | |
| CN114023267A (en) | Display panel, driving method thereof and display device | |
| CN113611248B (en) | Display panel, driving method of switch circuit of display panel and display device | |
| CN111312171B (en) | Pixel driving circuit, OLED display panel and display device | |
| CN111625133B (en) | OLED display panel | |
| CN209785530U (en) | Pixel compensation circuit | |
| CN110910835B (en) | Pixel driving circuit and pixel driving method | |
| CN111883060B (en) | Display panel and display device | |
| CN114360440A (en) | Pixel circuit, driving method thereof and light-emitting device | |
| CN114283738A (en) | Pixel circuit, driving method thereof and display device | |
| CN114582291B (en) | Display substrate, manufacturing method and display device | |
| CN114512086B (en) | Pixel circuit, driving method thereof and electronic equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |