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CN111243947A - 半导体设备的制造方法及半导体设备 - Google Patents

半导体设备的制造方法及半导体设备 Download PDF

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Publication number
CN111243947A
CN111243947A CN201911171440.2A CN201911171440A CN111243947A CN 111243947 A CN111243947 A CN 111243947A CN 201911171440 A CN201911171440 A CN 201911171440A CN 111243947 A CN111243947 A CN 111243947A
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chip
electrode
semiconductor device
convex portion
manufacturing
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CN111243947B (zh
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齐藤达也
角田隆行
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Canon Inc
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Canon Inc
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Abstract

本公开涉及半导体设备的制造方法及半导体设备。半导体设备的制造方法顺序地包括使用粘合剂将第一芯片和第二芯片接合在一起。第一芯片包括第一电极并具有凸部，并且第二芯片具有凹部。在接合中，第一芯片和第二芯片以使得凸部定位到凹部中的方式接合在一起。此外，该方法包括：在第二芯片中形成通孔以暴露第一电极，第一表面与具有凹部的第二表面相反；以及在通孔中形成电连接至第一电极的第二电极。

Description

半导体设备的制造方法及半导体设备
技术领域
本公开涉及半导体设备的制造方法及半导体设备。
背景技术
近年来，通过将多个衬底堆叠并接合在一起而获得的半导体设备受到关注。对于这种半导体设备，需要减少接合中的未对准。日本专利申请特许公开No.2005-347513讨论了一种设置有半导体衬底和电路衬底的半导体设备。半导体衬底包括凸状电极。电路衬底包括凹状电极。日本专利申请特许公开No.2005-347513讨论了一种技术，该技术可以通过用凸状电极插入到凹状电极中以将半导体衬底和电路衬底接合来减少未对准。日本专利申请特许公开No.2005-347513进一步讨论了一种技术，该技术使用含有导电填料的树脂来接合在一起并在凸状电极和其中插入有凸状电极的凹状电极之间建立导电。
然而，根据日本专利申请特许公开No.2005-347513，当按压包括凸状电极的半导体衬底以使其接合时，含有导电填料的树脂可能散布到周围，这可能会在非预期位置处引起导电并产生泄漏电流。当发生泄漏电流时，半导体设备可能不充当半导体设备，并且半导体设备的可靠性降低。
发明内容
根据本公开的一方面，一种半导体设备的制造方法包括：使用粘合剂将包括第一电极的第一芯片与第二芯片接合在一起；形成通孔；以及在通孔中形成第二电极。第一芯片包括凹部和凸部中的一个。第二芯片具有凹部和凸部中的另一个。第一芯片和第二芯片以使得凸部定位到凹部中的方式接合。从第二芯片的第一表面形成通孔以暴露第一电极。第二芯片的第一表面与其具有凸部或凹部的第二表面相反。第二电极电连接到第一电极。
根据本公开的实施例的半导体设备包括第一芯片、第二芯片、粘合剂、通孔和第二电极。第一芯片包括第一电极并且具有凹部和凸部中的一个。第二芯片具有凹部和凸部中的另一个。凸部定位到凹部中。粘合剂布置在第一芯片和第二芯片之间。通孔形成于在平面图中与第一电极重叠的区域中并且穿透第二芯片。第二电极形成在通孔中并且电连接到第一电极。
通过以下参考附图对示例性实施例的描述，本发明的其它特征将变得清楚。
附图说明
图1A和图1B是示出根据第一示例性实施例的半导体设备的示意图。
图2A至图2D是示出图1A和图1B中所示的半导体设备的制造方法的示例的示意图。
图3示出了根据第一示例性实施例的半导体设备的变型例。
图4是示出根据第一示例性实施例的半导体设备的另一变型例的示意图。
图5是示出根据第一示例性实施例的半导体设备的又另一变型例的示意图。
图6A、图6B和图6C是示出根据示例的太赫兹波传感器的示意图。
图7A至图7G示出了根据示例的太赫兹波传感器的制造方法。
图8A至图8E是图7A和图7G中所示的制造方法中的互锁结构及其附近的放大图。
图9示出了通过互锁结构减少了接合未对准的状态。
具体实施方式
下面参考附图描述了用于实施本发明的方式。然而，以下描述的方式仅是用于体现本发明的技术概念的示例，而无意于限制本发明。为了图示清楚，每个附图可以包括其中构件的尺寸或构件之间的位置关系被放大的部分。
图1A是示意性地示出根据第一示例性实施例的半导体设备的一部分的透视图。图1B是沿着图1A中的线A-A’截取的截面图。
如图1A和图1B中所示，在本示例性实施例中，在第一芯片10的面对第二芯片11的表面上设置有凹部20，并且在第二芯片11的面对第一芯片10的表面(第二表面)上设置有凸部15。第一芯片10和第二芯片11经由粘合剂12接合在一起，以使得凸部15可以定位到由凹部20的内壁20b围绕的区域中。第二芯片11具有形成于在平面图中与电极13(第一电极)重叠的区域中的通孔。在通孔中形成电连接到电极13的电极17(第二电极)。
根据本示例性实施例，可以获得高度可靠的半导体设备，同时可以减少多个芯片的接合期间的未对准。下面详细说明本示例性实施例。
在日本专利申请特许公开No.2005-347513中，为了减少在凸状电极和凹状电极的接合期间的未对准并且在它们之间建立导电，将凸状电极插入到凹状电极中，并且通过使用含有导电填料的树脂将凸状电极和凹状电极接合在一起。换句话说，虽然凹状电极和凸状电极确保对准精度，但是含有导电填料的树脂确保接合强度和导电状态。然而，根据日本专利申请特许公开No.2005-347513，当将凸状电极和凹状电极接合在一起时，布置在凹部和凸部之间的树脂可能散布到附近的凹状电极和附近的凸状电极，这可能会在非预期位置处引起导电并产生泄漏电流。特别是，与使凸状电极和凹状电极彼此直接接触的情况相比，在使用含有导电填料的树脂时导电性更容易降低。因此，当将对应的芯片接合在一起时，凸部和凹部朝向彼此被挤压，使得它们之间的距离变得尽可能小。这增加了含有导电填料的树脂散布的可能性，从而使泄漏的可能性更大。
相反，本示例性实施例以以下方式确保导电性：在接合之后，形成通孔以使得第一电极13可以被暴露，并且在通孔中形成电连接到第一电极13的第二电极17。即，通过形成在通孔中的电极而不是含有导电填料的粘合剂或凸状电极来实现导电。因此可以减少否则会在电极和附近的电极之间流动的泄漏电流。另外，采用了其中凸部和凹部彼此啮合的互锁结构。即使在发生接合未对准的情况下，该结构也使得凸部能够停留在被凹部的内壁围绕的区域内。因此，接合未对准变得小于凹部的宽度。如上所述，根据本示例性实施例，可以制造减少了多个芯片的接合期间的未对准的高度可靠的半导体设备。
以下描述详细描述了根据第一示例性实施例的半导体设备的构件。
第一芯片10包括衬底60和电极13。衬底60由例如硅衬底制成。如图6C中所示，第一芯片10还可以包括在电极13和衬底60之间的布线层67。布线层67包括布线65和层间电介质膜66。
如上所述，第一芯片10设置有凹部20。凹部20由第一芯片10的面对第二芯片11的表面(上表面20a)、底表面20c以及将第一芯片10的底表面20c和上表面20a彼此连接的内壁20b组成。在图1B中，凹部20由电极13和绝缘层14形成。具体地，绝缘层14形成凹部20的上表面20a和内壁20b，而电极13形成凹部20的底表面20c。如图1B中所示，由于凹部20的整个底表面20c由电极13形成，因此即使在凸部15在凹部20的内壁20b内移动的情况下，也能确保电极13可以布置于在平面图中与凸部15重叠的区域中。
第二芯片11在面对第一芯片10的一侧设置有凸部15。凸部15构成与凹部20互锁的互锁结构。凸部15可以采取例如矩形柱、圆柱或圆锥的形状。
在本示例性实施例中，第二芯片11由衬底61形成，并且凸部15也由衬底61形成。具体地，衬底61包括硅衬底，并且凸部15也由硅衬底形成。在凸部15由不同于硅的材料形成的情况下，在下面描述的形成通孔的过程中，需要在硅衬底和不同材料之间改变蚀刻条件。相反，当凸部15由硅衬底形成时，可以在形成通孔的过程中不改变蚀刻条件的情况下形成通孔。凸部15例如通过蚀刻衬底61而形成。
如图1B中所示，期望凸部15和凹部20形成为在它们之间具有一一对应的关系。这是因为从有效利用晶片的区域的方面来看，存在不与对方互锁的任何这样的凸部15或凹部20是不优选的。然而，只要不存在布局问题，这种凸部15的数量可以小于这种凹部20的数量。即使在那种情况下，也可以获得减少接合期间第一芯片10和第二芯片11之间的未对准的效果。
第二芯片11可以采用芯片11设置在第二芯片11的与第一芯片10相反的表面上的装置结构。装置结构是例如包括能够检测电磁波的光电二极管的检测单元。
第一芯片10和第二芯片11彼此堆叠。在第二芯片11设置有装置结构的情况下，第二芯片检测单元和电极13经由下述的电极17彼此电连接。
如上所述，在第二芯片11中设置通孔。电极17形成在通孔的侧表面上。在第二芯片11在第二芯片的第一表面的一侧设置有装置结构的情况下，第一表面与第一芯片10的一侧相反。优选地，电极17从电极13到在其上具有装置结构的第一表面上连续地形成。在将硅衬底用作衬底61并且在硅衬底中形成通孔的情况下，在硅衬底与电极17之间布置绝缘层18。
在第一芯片10与第二芯片11之间布置有粘合剂12。为了降低接合所需的温度，优选使用在250℃或更低硬化的粘合剂12并且更优选使用在200℃或更低硬化的粘合剂12作为粘合剂12。作为结果，不需要过多地考虑加热期间的耐热性，并且可以增加用于第一芯片10和第二芯片11的材料的选项数量。例如，热固性树脂用于粘合剂12。优选的是，粘合剂12也设置在凹部20的上表面20a上。以这种方式，即使在衬底61不能形成为具有足够厚度的情况下，也可以更容易地防止衬底61由于其上的应力导致的翘曲，并且衬底61可以不易破损。
接下来，参考图2A至图2D，描述图1A至图1B中所示的半导体设备的制造方法的示例。
首先，如图2A中所示，制备包括电极13并设置有凹部20的第一芯片10和设置有凸部15的第二芯片11。如上所述，可以通过例如蚀刻第二芯片11来形成凸部15。在该过程中，第一芯片10和第二芯片11优选地被制备为凸部15的高度22大于凹部20的高度23。随后，通过诸如旋涂的方法，将粘合剂12施加到第二芯片11的具有凸部15的一侧的表面。尽管在图2A中将粘合剂12施加到第二芯片11，但是可以将粘合剂12施加到第一芯片10的具有凹部20的一侧的表面。可替换地，可以将粘合剂12施加到第一芯片10和第二芯片11两者。
随后，如图2B中所示，将第一芯片10和第二芯片11接合在一起，其中第一芯片10的具有凹部20的一侧的表面与第二芯片11的具有凸部15的一侧的表面彼此面对。
在接合中，通过使用预先在这两个芯片上设置的对准标记将第一芯片10和第二芯片11彼此对准，使得第二芯片11的凸部15与第一芯片10的凹部20啮合。即，如图2B中所示，第一芯片10和第二芯片11经由粘合剂12接合在一起，以使得凸部15可以定位到由凹部20的内壁20b围绕的区域内。
在使用热固性树脂作为粘合剂12的情况下，在两个芯片彼此对准之后，当粘合剂12在施加有载荷的情况下加热一定时间段或更长时间段并且变得硬化时，完成接合。在粘合剂12变得硬化之前，粘合剂12以液态形式存在于第一芯片10和第二芯片11之间。因此，两个芯片之间的防滑性小，并且有可能发生未对准。在本示例性实施例中，如上所述，采用了使第二芯片11的凸部15与第一芯片10的凹部20互锁的互锁结构，使得接合未对准小于凹部的宽度。换句话说，可以将接合未对准减少到凹部20的宽度的范围内。
如图2C中所示，从第二芯片11的与第一芯片10相反的第二表面侧形成通孔21。通孔21可以通过例如蚀刻形成。在平面图中与电极13重叠的区域中形成通孔21，并且去除第二芯片11的一部分，使得可以暴露电极13。
在本示例性实施例中，通孔21形成于在平面图中与凸部15重叠的区域中。在本示例性实施例中，如上所述，凸部15的高度22大于凹部20的高度23。在这种情况下，在两个芯片的接合期间，布置于在平面图中与凸部15重叠的区域中的粘合剂12可能被推出到围绕凸部15的区域中。因此，可以在平面图中与凸部15重叠的区域中消除粘合剂12或者可以使在该区域中粘合剂12的厚度非常小。因此，当通过干法蚀刻形成通孔21时，可以对粘合剂12的薄区域施加蚀刻。与粘合剂12整体上具有均一的厚度的情况相比，可以使粘合剂12蚀刻得更快。尽管担心减小粘合剂12的厚度可能降低第一芯片10和第二芯片11之间的接合强度，但是在本示例性实施例中，在除了在平面图中与凸部15重叠的区域之外的区域中，粘合剂12的厚度被充分地确保。因此，在平面图中与凸部15重叠的区域之外的区域中，可以维持接合强度。
接下来，如图2D中所示，在通孔21的侧表面上形成电连接到电极13的电极17(贯通电极)。在本示例性实施例中，为了确保电极17和第二芯片11中包括的硅衬底之间的绝缘性，在设置电极17之前设置绝缘层18。绝缘层18由通过例如等离子体化学气相沉积(CVD)形成的氧化物形成。电极17由通过例如溅射或镀敷形成的金属制成。在图2D中，在通孔21的侧表面上沿着通孔21形成电极17。然而，代替该示例，也可以形成填充通孔21的电极17。
根据本示例性实施例，接合未对准限于由凹部20的内壁20b围绕的区域，这可以减小电极17和电极13之间不导电的可能性，并且可以确保接合在一起的芯片彼此电连接。此外，树脂被用作粘合剂12，这可以减小由热引起的装置破裂的可能性。另外，即使在平面图中与凸部15重叠的区域中粘合剂12的厚度小，在平面图中不与凸部15重叠的区域中，即在平面图中围绕凸部15的区域中，也充分确保粘合剂12的厚度。因此，由于应力引起的衬底61的翘曲不太可能发生，并且可以获得确保可靠性的半导体设备。
<变型例>
下面描述上述示例性实施例的变型例。在以下的每个变型例中，如上述示例性实施例中那样，可以获得减少接合未对准的效果。
尽管在图1B中凸部15仅由用于第二芯片11的硅衬底形成，但是如图3中所示，凸部15可以可替换地由绝缘层40和硅衬底形成，其中绝缘层40设置在由硅衬底形成的凸部15上。设置在第一芯片10和第二芯片11之间的绝缘层40可以防止第一芯片10和第二芯片11之间的短路。例如，在芯片的接合期间，在凸部15与凹部20的底表面20c之间的粘合剂12中可能出现空隙。在电极17进入该空隙并形成于其中的情况下，在其上布置有凸部15的衬底和其上具有凹部20的衬底之间发生短路。为了解决该不便，如图3中所示，绝缘层40布置在凸部15中，这使得可以防止衬底之间的短路并增强可靠性。
可替换地，如图4中所示，可以将硅衬底的一个表面形成为平坦表面，并且可以通过将绝缘层30接合到平坦表面来形成凸部15。在图4中，衬底61的面对第一芯片的表面是平坦表面，并且绝缘层30设置在平坦表面上。凸部15由衬底61和绝缘层30形成。
如图3和图4中所示，在将绝缘层14或绝缘层30布置在凸部15与电极13之间的情况下，在形成通孔的过程中，去除绝缘层14或绝缘层30直到电极13被暴露为止。
在另一个示例中，如图5中所示，可以在第一芯片10上设置凸部15，并且可以在第二芯片11上设置凹部20。如果在第一芯片10上设置凸部15和凹部20中的一个并且在第二芯片11上设置凸部15和凹部20中的另一个，可以获得减少两个芯片在其接合期间的接合未对准的效果。在凸部15设置在第一芯片10上的情况下，第一芯片10包括凸部15、绝缘层54和形成在凸部15上的电极13。在这种结构中，凸部15被配置成与设置在第二芯片11上的凹部20互锁。但是，在这种情况下，可能的是，如果发生接合未对准从而凸部15的位置已经在与设置在第二芯片11上的凹部20相对应的范围内移位，取决于凸部15、电极13和凹部20的尺寸，电极17可能形成在与电极13未对准的位置。因此，优选地，如图1B中所示，凹部20形成在第一芯片10上，而凸部15形成在第二芯片11上，在第二芯片11中形成通孔。在第一芯片10上形成凸部15的情况下，优选使凹部20的区域变窄，这使得接合未对准较小并且因此减小电极17形成在未对准位置中的可能性。
<示例>
本示例是这样的示例，其中如图3中所示，制造半导体设备以使形成衬底61和绝缘层40的凸部15，并且在彼此上堆叠第一芯片10和第二芯片11。具体地，本示例中的半导体设备被形成为图6A中所示的检测太赫兹波的检测器。参考图6A至图6C，描述根据示例的半导体设备。
如图6A至图6C中所示，半导体设备包括第一芯片10和第二芯片11。第一芯片10包括衬底(在本示例中为读出电路衬底)60和布线层67。第二芯片11包括衬底(在本示例中为接收天线衬底)61。具体地，将厚度为60μm的接收天线衬底61层压在厚度为725μm的读出电路衬底60上。在接收天线衬底61的与读出电路衬底60相反的表面上布置检测太赫兹波63的天线64。读出电路衬底60包括设置为读出电路的互补金属氧化物半导体(CMOS)晶体管。考虑到太赫兹波的检测效率，将接收天线衬底61的厚度设定为60μm，但这是可以适当地改变的设计事项。
图6B是接收天线衬底61的形成在天线64侧的表面(以下称为“感光表面62”)的一部分的放大图。图6C是沿着线B-B’截取的截面图。如图6B和图6C中所示，使用肖特基势垒二极管19的环形天线64以二维阵列布置。一个像素包括天线64、阳极侧电极17和阴极侧电极17。在本示例中，用于每个像素的区域被设定为500μm乘以500μm，并且使用各自具有140μm的直径的环形天线64。
读出电路衬底60的电极13和包括在布线层67中的布线65经由天线64、阳极侧电极17和阴极侧电极17彼此电连接。
参考图7A至图7G描述根据本示例的太赫兹波传感器的制造方法。图8A至图8E是图7A至图7G中的虚线框的内部的各个放大图。图8A和图8B对应于图7C中的虚线框的内部。图8C对应于图7D中的虚线框的内部。图8D对应于图7E中的虚线框的内部，并且图8E对应于图7F中的虚线框的内部。
作为图7A中所示的接收天线衬底61，使用直径为200mm且厚度为725μm的硅衬底。在接收天线衬底61上，至少布置二维排列的肖特基二极管19以及用于图案化和与读出电路衬底60接合的对准标记72。肖特基二极管19和对准标记72布置在接收天线衬底61的光接收表面(元件表面71)上。
如图7B中所示，使用临时接合粘合剂73将接收天线衬底61的感光表面和支撑衬底74接合在一起。作为支撑衬底74，使用直径为200mm且厚度为500μm的支撑玻璃。作为临时接合粘合剂73，使用3M公司制造的LC-5320。
剥离层涂布在支撑衬底74上。在本示例中，将3M公司制造的光热转换(LTHC)用于剥离层。可以在下述过程中通过激光照射来分离支撑衬底74。然后，通过旋涂将临时接合粘合剂73施加到支撑衬底74。
接下来，如图7C中所示，将接收天线衬底61的与光接收表面相反的表面(接合读出电路衬底60的表面侧)研磨。在该过程中，优选地，将第二芯片11的厚度减小到100μm或更小。这是因为可以减少形成通孔所需的时间。具体地，在本示例中，通过使用背面研磨设备来研磨接收天线衬底61的接合读出电路衬底60的表面侧，并且将接收天线衬底61的厚度减小到60μm。
接下来，在接收天线衬底61的研磨的表面(接合读出电路衬底60的表面侧)上形成凸部15。图8A是一个凸部15及其附近的放大图。在形成凸部15的过程中，需要将凸部15形成为与要形成通孔的位置相对应。在本示例中，使用双面掩模对准器通过使用对准标记72来形成光致抗蚀剂图案，并且对接收天线衬底61本身进行干法蚀刻。由此形成各自直径为60μm且高度为1μm的凸部15。
然后，如图8B中所示，通过等离子体CVD在接收天线衬底61的具有凸部15的一侧的表面上沉积厚度为100nm且充当绝缘层40的SiO2膜。
然后，如图7D中所示，在接收天线衬底61的具有凸部15的一侧的表面上形成苯并环丁烯(BCB)层作为粘合剂12。作为BCB层，通过旋涂施加(Dow Chemical Company制造的)CYCLOTENE 3022-35以使具有1.3μm的厚度。
然后，通过粘合剂12将接收天线衬底61和读出电路衬底60接合在一起。首先，将这些材料在加热到140℃的加热板上烘烤三分钟，此后，接收天线衬底61和读出电路衬底60接合在一起。作为读出电路衬底60，使用直径为200mm且厚度为725μm的硅衬底。
包括布线65和层间电介质膜66的布线层67接合到用作读出电路衬底60的硅衬底的一个表面。在布线65和CMOS晶体管之间，建立了导电。在与接收天线衬底61接合期间要使用的对准标记79布置在用作读出电路衬底60的硅衬底上。读出电路衬底60形成为能够在像素至像素的基础上读出来自布置在接收天线衬底61上的肖特基二极管19的各个信号的电路衬底。因此，像素电路以500μm的间距形成在读出电路衬底60上，以使对应于二维排列的肖特基二极管19。
图8C是布置在读出电路衬底60的一个凹部20及其附近的放大图。如图8C中所示，凹部20由绝缘层14和对应的电极13形成，以使与对应的凸部15构成互锁结构，并且电极13的一部分暴露于凹部20的底表面20c。凹部20的形状形成为像直径为120μm且深度为0.9μm的圆柱。
接下来，如图7D中所示，通过使用接收天线衬底61上的对准标记72和读出电路衬底60上的对准标记79来实现接合对准。此后，使用晶片接合机(EVG520IS)将接收天线衬底61和读出电路衬底60接合在一起。具体地，在向其施加3kN的载荷的情况下将接收天线衬底61和读出电路衬底60在200℃的温度下保持2小时。由此用作粘合剂12的BCB层硬化，并且完成了它们之间的接合。作为接合对准的结果，可以在图8D中所示的接收天线衬底61上的凸部15和读出电路衬底60上的凹部20构成互锁结构的状态下实现接合。
可能存在由于接收天线衬底61和读出电路衬底60在粘合剂12硬化之前相互滑动而发生接合未对准的情况。使用多种材料尝试进行接合。结果，确认了本示例中的互锁结构起到了将接合未对准减小到凹部20的范围内的作用，并且凸部15停留在凹部20的内壁20b内部而没有未对准。如图9中所示，即使在发生接合未对准时，凸部15也停在凹部20的内壁20b处。由此，确认可以获得互锁结构的效果。
然后，如图7E中所示，将支撑衬底74与接收天线衬底61分离。具体地，用激光照射支撑衬底74的与接合接收天线衬底61的一侧相反的表面。由此，对上述的LTHC进行加热，从而将支撑衬底74与临时接合粘合剂73分离。此后，使用剥落带和溶剂将残留在接收天线衬底61上的临时接合粘合剂73去除。
随后，如图7F中所示，从接收天线衬底61的元件表面71形成通孔，直到暴露出电极13为止。具体地，通过干法蚀刻去除接收天线衬底61以及布置在凸部15与读出电路衬底60之间的绝缘层40和粘合剂12。由此，电极13从接收天线衬底61暴露。
随后，从电极13到肖特基二极管19的电极连续地形成电极17。电极17将肖特基二极管19电连接到布置在读出电路衬底60和接收天线衬底61之间的布线层67中包括的布线65。天线64包括对应的电极17的部分。如图8E中所示，电极17在平面图中与凸部15重叠的区域中连接到电极13。
为了形成电极17，首先，通过干法蚀刻去除接收天线衬底61以及布置在凸部15和接收天线衬底61之间的绝缘层40和粘合剂12。随后，在接收天线衬底61中形成通孔，直到电极13从读出电路衬底60暴露。随后，通过等离子体CVD在通孔的侧表面上形成作为用于绝缘层18的材料的膜，以确保电极17和接收天线衬底61之间的绝缘性。作为用于绝缘层18的材料，具体地，使用了四乙氧基硅烷(TEOS)。然后通过镀敷方法形成由Cu制成的电极17。
随后，如图7G中所示，通过切割切出具有接合在一起的接收天线衬底61和读出电路衬底60的芯片。因此，获得了图6A中所示的太赫兹波传感器。
描述第二示例。前述示例中描述的半导体设备可以适当地应用于例如图像形成设备(图像捕获设备或相机)。具体地，通过图像形成设备外部的振荡器用太赫兹波照射要捕获其图像的目标对象。随后，由于前述太赫兹波在目标对象上的反射，图像形成设备接收入射到其上的太赫兹波。然后，图像处理单元获取经由输出端子从图像形成设备中的输出电路输出的电信号，并且图像处理单元基于电信号形成图像。在这种情况下，根据前述示例性实施例和前述示例，电信号基于接收器接收(检测)的太赫兹波。因此，那些信号包含低水平的噪声并且包括高度敏感的信息。因此，图像形成设备能够形成(捕获)包含低水平的噪声且高度敏感的图像。
上面描述了本发明的示例性实施例和示例。然而，本发明不限于示例性实施例和那些示例，而是可以在本发明的主旨内进行各种修改和改变。
以上采取太赫兹波传感器作为示例。然而，本发明不限于该示例。例如，除了太赫兹波传感器之外，本发明还可应用于电磁波传感器，诸如红外辐射传感器。
根据本发明，可以提供一种半导体设备的制造方法和半导体设备，该制造方法和半导体设备减少多个芯片的接合期间的位置偏移(未对准)并且可靠性高。
尽管已经参考示例性实施例描述了本发明，但是应当理解，本发明不限于所公开的示例性实施例。所附权利要求的范围应被赋予最宽泛的解释，以涵盖所有这样的修改以及等同的结构和功能。

Claims (21)

1.一种半导体设备的制造方法，其特征在于，所述制造方法包括：
使用粘合剂将包括第一电极的第一芯片与第二芯片接合在一起，所述第一芯片具有凹部和凸部中的一个并且所述第二芯片具有所述凸部或所述凹部中的另一个，其中，所述第一芯片和第二芯片被限制为使得所述凸部定位到所述凹部中；
从所述第二芯片的第一表面在所述第二芯片中形成通孔以暴露所述第一电极，所述第一表面与所述第二芯片的具有所述凸部或所述凹部的第二表面相反；以及
在所述通孔中形成第二电极，所述第二电极电连接到所述第一电极。
2.根据权利要求1所述的半导体设备的制造方法，
其中，在所述第一芯片中设置所述凹部，
其中，所述凹部具有内壁和底表面，
其中，所述第一电极从所述凹部的底表面暴露，以及
其中，所述通孔形成于在平面图中与所述第一电极和所述凸部重叠的区域中。
3.根据权利要求2所述的半导体设备的制造方法，
其中，所述第一芯片包括绝缘层，以及
其中，所述凹部由所述第一电极和所述绝缘层形成。
4.根据权利要求1所述的半导体设备的制造方法，其中，所述第二电极从所述第一电极到所述第二芯片的所述第一表面连续地形成。
5.根据权利要求1所述的半导体设备的制造方法，
其中，所述第二芯片包括硅衬底，以及
其中，在所述硅衬底中形成所述凹部或所述凸部。
6.根据权利要求1所述的半导体设备的制造方法，
其中，所述第二芯片包括硅衬底和绝缘体，以及
其中，所述凹部或所述凸部由所述硅衬底和所述绝缘体形成。
7.根据权利要求2所述的半导体设备的制造方法，其中，所述凸部的高度比所述凹部的高度高。
8.根据权利要求7所述的半导体设备的制造方法，其中，所述第一芯片包括读出电路。
9.根据权利要求1所述的半导体设备的制造方法，其中，所述粘合剂为热固性树脂，并且被加热以在所述接合中实现接合。
10.根据权利要求1所述的半导体设备的制造方法，还包括在所述接合之前，通过去除所述第二芯片的一部分来将所述第二芯片的厚度减小至100μm或更小。
11.根据权利要求9所述的半导体设备的制造方法，其中，所述第一芯片和所述第二芯片以所述粘合剂在平面图中与所述凸部重叠的区域中的厚度比在平面图中不与所述凸部重叠的区域中的厚度小的方式而接合在一起。
12.根据权利要求1至11中的任一项所述的半导体设备的制造方法，
其中，所述第二芯片包括硅衬底和被配置为检测电磁波的检测单元，
其中，所述硅衬底布置在所述检测单元与所述第一芯片之间，以及
其中，在形成所述第二电极时，形成从所述第一电极连续到所述检测单元的所述第二电极。
13.一种半导体设备，其特征在于，所述半导体设备包括：
第一芯片，包括第一电极并且具有凹部和凸部中的一个；
第二芯片，具有所述凹部和所述凸部中的另一个，所述凸部被定位到所述凹部中；
粘合剂，布置在所述第一芯片和所述第二芯片之间；
通孔，形成于在平面图中与所述第一电极重叠的区域中并穿透所述第二芯片；以及
第二电极，形成在所述通孔中并电连接到所述第一电极。
14.根据权利要求13所述的半导体设备，
其中，所述凹部设置在所述第一芯片中，
其中，所述凹部具有内壁和底表面，
其中，所述第一电极从所述凹部的底表面暴露，以及
其中，所述通孔形成于在平面图中与所述第一电极和所述凸部重叠的区域中。
15.根据权利要求14所述的半导体设备，
其中，所述第一芯片包括绝缘层，以及
其中，所述凹部由所述第一电极和所述绝缘层形成。
16.根据权利要求13所述的半导体设备，其中，所述第二电极从所述第一电极到所述第二芯片的第一表面连续地形成，所述第一表面与所述第二芯片的具有所述凹部或所述凸部的第二表面相反。
17.根据权利要求13所述的半导体设备，其中，所述凸部的高度高于所述凹部的高度。
18.根据权利要求13所述的半导体设备，其中，所述粘合剂在平面图中与所述凸部重叠的区域中的厚度比在平面图中不与所述凸部重叠的区域中的厚度小。
19.根据权利要求13至18中的任一项所述的半导体设备，
其中，所述第二芯片包括硅衬底和被配置为检测电磁波的检测单元，
其中，所述硅衬底布置在所述检测单元与所述第一芯片之间，以及
其中，所述第二电极从所述第一电极到所述检测单元连续地形成。
20.根据权利要求19所述的半导体设备，其中，所述第二芯片还包括输出电路，所述输出电路被配置为向外部输出电信号，所述电信号基于由包括所述第二电极的天线接收的太赫兹波。
21.一种图像形成设备，其特征在于，所述图像形成设备包括：
根据权利要求20所述的半导体设备；以及
图像处理单元，被配置为基于所述电信号形成图像。
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