CN111239476A

CN111239476A - Signal detector and signal detection method

Info

Publication number: CN111239476A
Application number: CN201811443296.9A
Authority: CN
Inventors: 董明辉; 陈韦旗
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-11-29
Filing date: 2018-11-29
Publication date: 2020-06-05
Anticipated expiration: 2038-11-29
Also published as: CN111239476B

Abstract

A signal detector and a signal detection method. The signal detector comprises a plurality of oversampling circuits and a detection circuit. The plurality of over-sampling circuit systems are used for receiving a first signal and a second signal from a channel, sequentially sampling the first signal and the second signal according to a plurality of clock signals to generate a plurality of signal difference values, and comparing the signal difference values with a reference difference value to generate a plurality of detection signals. The detection circuit system is used for generating a noise indicating signal according to the detection signals so as to indicate whether the first signal and the second signal are noise or not.

Description

Signal detector and signal detection method

Technical Field

The present disclosure relates to a signal detector and a signal detection method, and more particularly, to a signal detector and a signal detection method for discriminating a signal transmitted through a channel.

Background

In high-speed transmission applications, Inter Symbol Interference (ISI) is a common phenomenon. ISI may degrade the accuracy of the data and may cause portions of the circuitry in the system to misjudge the data and perform incorrect operations.

Disclosure of Invention

To solve the above problem, some embodiments of the present disclosure provide a signal detector including a complex oversampling circuit system and a detection circuit system. The plurality of over-sampling circuit systems are used for receiving a first signal and a second signal from a channel, sequentially sampling the first signal and the second signal according to a plurality of clock signals to generate a plurality of signal difference values, and comparing the signal difference values with a reference difference value to generate a plurality of detection signals. The detection circuit system is used for generating a noise indicating signal according to the detection signals so as to indicate whether the first signal and the second signal are noise or not.

A method of signal detection, comprising the operations of: sequentially sampling a first signal and a second signal transmitted from a channel according to a plurality of clock signals to generate a plurality of signal differences, and comparing the signal differences with a reference difference to generate a plurality of detection signals; and generating a noise indication signal according to the detection signals to indicate whether the first signal and the second signal are noise or not.

In summary, the signal detector and the signal detecting method provided by the embodiment of the disclosure can identify the signal received from the channel by an oversampling manner, so as to avoid misjudging the signal as noise due to the influence of the inter-symbol interference.

Drawings

The drawings of the disclosure are illustrated as follows:

FIG. 1 is a schematic diagram of a signal detector shown in accordance with some embodiments of the present disclosure;

FIG. 2 is a circuit schematic of a plurality of oversampling circuitry, as depicted in FIG. 1, in accordance with some embodiments of the present disclosure;

FIG. 3 is a waveform diagram of a plurality of signals and a plurality of clock signals as in FIG. 1, according to some embodiments of the present disclosure; and

fig. 4 is a flow chart illustrating a method of signal detection according to some embodiments of the present disclosure.

Description of reference numerals:

100: the signal detector 120: oversampling circuit system

140: detection circuitry 100A: channel

SI1, SI 2: signals DT0 to DT 2: detecting the signal

P0-P2: clock signal Δ VREF: reference difference

140: detection circuitry 142: OR gate circuit

SND: noise indication signal 160: synchronous output circuit system

162: d-type flip-flop circuit FE 1: falling edge

222. 224: the sampling circuit 226: arithmetic circuit

SD 0-SD 2: signal difference 228: comparator circuit

VCM: common mode voltage VREF +, VREF-: reference voltage

TP 1-TP 3: bit periods 310, 320: wave form

330: waveforms PD1, PD 2: phase difference

TPD: total period 400: signal detection method

S410 and S420: operations V1, V2: signal value

Detailed Description

All terms used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries, any use of the words discussed herein in the context of this specification is by way of example only and should not be construed as limiting the scope or meaning of the present disclosure. Likewise, the present disclosure is not limited to the various embodiments shown in this specification.

It will be understood that the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections. These elements, components, regions, layers and/or regions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. As used herein, "and/or" includes any and all combinations of one or more of the associated items.

As used herein, coupled or connected means that two or more elements are in direct or indirect physical or electrical contact with each other, and that two or more elements are in operation or act with each other.

As used herein, the term "circuit system" generally refers to a single system comprising one or more circuits (circuits). The term "circuit" broadly refers to an object connected in some manner by one or more transistors and/or one or more primary passive components to process a signal.

Referring to fig. 1, fig. 1 is a schematic diagram of a signal detector 100 shown in accordance with some embodiments of the present disclosure. In some embodiments, the signal detector 100 may be applied to a high speed transmission system to determine whether the received signal is data or noise, but the disclosure is not limited thereto.

In some embodiments, the signal detector 100 includes a plurality of oversampling circuits 120 and detection circuits 140. The over-sampling circuitry 120 receives signals SI1 and SI2 from channel 100A. In some embodiments, the signals SI1 and SI2 may be differential signals and carry a specific data. In some embodiments, the channel 100A is a signal path between circuit boards or may be a signal cable connecting a serial transmission system, but the disclosure is not limited thereto.

The over-sampling circuits 120 sample the signal SI1 and the signal SI2 according to the clock signals P0-P2 to generate a plurality of signal differences (e.g., SD 0-SD 2 in FIG. 2). The over-sampling circuits 120 compare a plurality of signal differences with the reference difference Δ VREF to generate a plurality of detection signals DT 0-DT 2.

The detection circuitry 140 is coupled to the oversampling circuitry 120 to receive the detection signals DT 0-DT 2. The detection circuit system 140 is configured to generate a noise indication signal SND according to the detection signals DT 0-DT 2 to indicate whether the received signals SI1 and SI2 are noise. In some embodiments, the detection circuitry 140 may be implemented by the or gate 142, but the disclosure is not limited thereto. In some embodiments, the noise indication signal SND may be used to determine whether to activate a power saving mechanism of the system.

In some embodiments, the signal detector 100 may further include a plurality of synchronous output circuitry 160. The plurality of synchronous output circuitry 160 is coupled between the plurality of oversampling circuitry 120 and the detection circuitry 140. The synchronous output circuitry 160 receives the detection signals DT 0-DT 2, respectively, and outputs the received detection signals DT 0-DT 2 to the detection circuitry 140 according to the last clock signal P2 of the clock signals P0-P2. In some embodiments, the synchronous output circuitry 160 may be implemented by a D-type flip-flop circuit 162. In some embodiments, the D-type flip-flop circuit 162 may be configured as a negative edge flip-flop to output the received detection signals DT 0-DT 2 to the detection circuitry 140 in response to the falling edge of the clock signal P2 (e.g., the falling edge FE1 of FIG. 3). The above description of the synchronous output circuitry 160 is provided for purposes of example and the disclosure is not limited thereto. Various types of synchronous output circuitry 160 are within the scope of the present disclosure.

The following paragraphs will describe embodiments of the above-described circuits, but the present disclosure is not limited to the following embodiments.

Referring to fig. 2, fig. 2 is a circuit schematic of a plurality of oversampling circuitry 120, as depicted in fig. 1, according to some embodiments of the present disclosure. For ease of understanding, like elements in FIGS. 1-2 will be designated with like numerals.

Each oversampling circuitry 120 includes a plurality of

sampling circuits

222 and 224, an arithmetic circuit 226, and a comparator circuit 228. For ease of description, the following paragraphs describe the oversampling circuitry 120 operating according to the clock signal P0 in fig. 2 as an example, and it should be understood that the following related operations and setting manners can be analogized to other oversampling circuitry 120, and thus, the description is not repeated.

The sampling circuit 222 samples the signal SI1 according to a corresponding clock signal P0 of the plurality of clock signals P0-P2 to generate a signal value V1. The sampling circuit 224 samples the signal SI2 according to the corresponding clock signal P0 to generate the signal value V2. In some embodiments, the

sampling circuits

222 and 224 may be implemented by capacitance switching circuits, but the disclosure is not limited thereto.

The operation circuit 226 is coupled to the

sampling circuits

222 and 224 to receive the signal values V1 and V2. In some embodiments, the operation circuit 226 is configured to calculate a difference between the signal values V1 and V2 to generate a corresponding signal difference SD0 of the signal differences SD0 SD 2. In some embodiments, the operation circuit 226 may be implemented by a subtractor, but the disclosure is not limited thereto.

The comparator circuit 228 is coupled to the operation circuit 226 for receiving the corresponding signal difference SD 0. In some embodiments, the comparator circuit 228 compares the corresponding signal difference SD0 with the reference difference Δ VREF to generate a corresponding detection signal DT0 of the detection signals DT 0-DT 2, which is transmitted to the corresponding synchronization output circuitry 160 of fig. 1. For example, when the signal difference SD0 is greater than the reference difference Δ VREF, the comparator circuit 228 outputs the detection signal DT0 having a logic value 1. Under this condition, the signals SI1 and SI2 sampled according to the clock signal P0 can be determined as data. On the contrary, when the signal difference SD0 is less than or equal to the reference difference Δ VREF, the comparator circuit 228 outputs the detection signal DT0 having a logic value 0.

Referring to fig. 3, fig. 3 is a waveform diagram of signals SI1 and SI2 and clock signals P0-P2 of fig. 1 according to some embodiments of the present disclosure. For ease of understanding, similar elements in fig. 1 and 3 will be designated with the same reference numerals.

In fig. 3, the voltage difference between the reference voltage VREF + and the reference voltage VREF-is the reference difference Δ VREF, and the common-mode voltage VCM is the common-mode voltage between the signals SI1 and SI2, wherein when the difference between the signals SI1 and SI2 is greater than the reference difference Δ VREF, the signals SI1 and SI2 are considered to carry specific data; conversely, when the difference between the signals SI1 and SI2 is smaller than the reference difference Δ VREF, the signals SI1 and SI2 are considered as no data, in which case the signals SI1 and SI2 are considered as noise.

For example, if sampling is performed at the center of the bit period (e.g., sampling is performed by using the rising edge of the clock P1 in the bit period TP2), as shown by the waveform 310, since the difference between the signals SI1 and SI2 is greater than the reference difference Δ VREF, the signals SI1 and SI2 carry specific data, which are sequentially 1, 0, 1 in the bits of the bit periods TP1, TP2, and TP 3. Conversely, as shown by the waveform 320, if the difference between the signals SI1 and SI2 is significantly smaller than or equal to the reference difference Δ VREF, the signals SI1 and SI2 are determined as noise.

In some cases, as shown by waveform 330, signals SI1 and SI2 are distorted during bit period TP2 due to Inter Symbol Interference (ISI) introduced by channel 100A. In some related arts, a single sampling (e.g. a single sampling with the clock P1) is performed only during a single bit period (e.g. the bit period TP2) of the signals to be detected (e.g. the signals SI1 and SI2), and the signals SI1 and SI2 may be erroneously determined as noise in the case of the waveform 330.

In some embodiments, a plurality of phase differences PD1 and PD2 are sequentially set between the plurality of clock signals P0-P2. In some embodiments, the total duration TPD of the phase differences PD1 and PD2 is set to be less than or equal to one bit duration (e.g., the bit duration TP2) of the SI1 or SI 2. In some embodiments, the number of phase differences between the clock signals P0-P2 is greater than or equal to 1 during a single bit of the signals SI1 or SI 2. In other words, the signals SI1 or SI2 are sampled at least twice in sequence during each bit. For example, as shown in fig. 3, the sampling circuits 222 in the oversampling circuits 120 can sample the signal SI1 in sequence according to the rising edges of the clock signals P0, P1, and P2.

In contrast to the related art, by the above arrangement, the signals SI1 or SI2 are sampled at least twice in sequence during each bit. Thus, the detection circuitry 140 can determine whether the signal SI1 or SI2 is noise according to the sampled signal values at different time points. Thus, the signals SI1 and SI2 are prevented from being misjudged as noise due to the influence of ISI.

For example, if the detection signals DT 0-DT 2 are all logic values 0, it means that the signal differences SD 0-SD 2 sampled at different time points are all smaller than the reference difference Δ VREF. Under this condition, the detection circuitry 140 outputs the noise indication signal SND having a logic value of 0, indicating that the signal SI1 or SI2 is noise. On the contrary, if one of the detection signals DT 0-DT 2 is not at logic value 0, the detection circuitry 140 outputs the noise indication signal SND with logic value 1, and the indication signals SI1 and SI2 are data.

The above example is described by taking 3 clock signals P0-P2 as an example, but the disclosure is not limited thereto. In various embodiments, the signal detector 100 may be configured to perform correlation operations according to 2 or more than 2 clock signals.

Referring to fig. 4, fig. 4 is a flow chart illustrating a signal detection method 400 according to some embodiments of the present disclosure. For ease of understanding, the following description will refer collectively to the signal detector 100 of fig. 1.

In operation S410, the channel 100A receives the signal SI1 and the signal SI2, sequentially samples the signal SI1 and the signal SI2 according to the clock signals P0-P2 to generate a plurality of signal differences SD 0-SD 2, and compares the signal differences SD 0-SD 2 with the reference difference Δ VREF to generate a plurality of detection signals DT 0-DT 2.

In operation S420, a noise indication signal SND is generated according to the detection signals DT 0-DT 2 to indicate whether the signals SI1 and SI2 are noise or not.

The above two operations can be described with reference to the descriptions of fig. 1 to 3, and thus, the description thereof is not repeated herein. The operations of the signal detection method 400 are merely examples and are not limited to the sequential execution of the above examples. Various operations under the signal detection method 400 may be suitably added, substituted, omitted, or performed in a different order without departing from the manner of operation and scope of various embodiments of the present disclosure.

In summary, the signal detector and the signal detecting method provided by the embodiment of the disclosure can identify the signal received from the channel by an oversampling manner, so as to avoid misjudging the signal as noise due to the ISI.

Although the present disclosure has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the disclosure, and therefore, the scope of the disclosure should be determined by that of the appended claims.

Claims

1. A signal detector, comprising:

the system comprises a plurality of oversampling circuit systems, a plurality of detection circuit systems and a plurality of clock signal generating circuit systems, wherein the oversampling circuit systems are used for receiving a first signal and a second signal from a channel, sampling the first signal and the second signal in sequence according to a plurality of clock signals to generate a plurality of signal difference values, and comparing the signal difference values with a reference difference value to generate a plurality of detection signals; and

the detection circuit system is used for generating a noise indicating signal according to the detection signals so as to indicate whether the first signal and the second signal are noise or not.

2. The signal detector of claim 1, wherein the plurality of complex oversampling circuitry each comprises:

a first sampling circuit for sampling the first signal according to a corresponding clock signal of the clock signals to generate a first signal value;

a second sampling circuit for sampling the second signal according to the corresponding clock signal to generate a second signal value;

an arithmetic circuit for calculating a difference between the first signal value and the second signal value to generate a corresponding one of the signal differences; and

a comparator circuit for comparing the corresponding signal difference with the reference difference to generate a corresponding detection signal of the detection signals.

3. The signal detector of claim 1, wherein the detection circuitry comprises:

an OR gate circuit for generating the noise indication signal according to the detection signals.

4. The signal detector of claim 1, further comprising:

and a plurality of synchronous output circuit systems respectively coupled to the oversampling circuit systems to receive the detection signals and output the detection signals to the detection circuit system according to a last clock signal of the clock signals.

5. The signal detector of claim 1, wherein the clock signals have a plurality of phase differences, and a total duration of the phase differences is less than or equal to a bit duration of the first signal or the second signal.

6. A method of signal detection, comprising:

sequentially sampling a first signal and a second signal transmitted from a channel according to a plurality of clock signals to generate a plurality of signal differences, and comparing the signal differences with a reference difference to generate a plurality of detection signals; and

a noise indication signal is generated according to the detection signals to indicate whether the first signal and the second signal are noise or not.

7. The signal detection method of claim 6, wherein generating the detection signals comprises:

sampling the first signal according to a corresponding clock signal in the clock signals to generate a first signal value;

sampling the second signal according to the corresponding clock signal to generate a second signal value;

calculating a difference between the first signal value and the second signal value to generate a corresponding signal difference of the signal differences; and

comparing the corresponding signal difference value with the reference difference value to generate a corresponding detection signal in the detection signals.

8. The signal detection method of claim 6, wherein generating the noise indication signal comprises:

the noise indication signal is generated by an OR gate circuit according to the detection signals.

9. The signal detection method of claim 6, further comprising:

the detection signals are output according to a last clock signal in the clock signals.

10. The signal detecting method of claim 6, wherein the clock signals have a plurality of phase differences therebetween, and a total period of the phase differences is less than or equal to a bit period of the first signal or the second signal.