Disclosure of Invention
The embodiment of the application aims to provide a signal sampling circuit, a detection device and an imaging system, which are used for solving at least one technical problem in the prior art.
In order to solve the above technical problem, an embodiment of the present application provides a signal sampling circuit, which includes a plurality of comparators and a time-to-digital converter that are connected to each other, wherein two input terminals of a first comparator of the plurality of comparators are respectively connected to a signal input terminal and a reference amplitude supply terminal of the signal sampling circuit, and the signal sampling circuit further includes:
The input end of the delay unit is connected with the signal input end, and the output end of the delay unit is connected with the first input ends of the second comparator and the third comparator in the plurality of comparators;
an amplitude holding unit having an input connected to the signal input and an output connected to the second input of the third comparator, and
A processing unit connected to the outputs of the time-to-digital converter and the amplitude holding unit to determine a time corresponding to the amplitude output by the amplitude holding unit by processing the time data output by the time-to-digital converter,
Wherein a second input of the second comparator is connected with the reference amplitude supply.
Optionally, the amplitude holding unit is a voltage holding circuit including a capacitor, a diode and an inductor, wherein one end of the capacitor is connected to the ground in parallel with one end of the inductor, the other end of the capacitor is connected to the second input end of the third comparator and the processing unit in parallel with one end of the diode, and the other end of the diode is connected in series with the other end of the inductor.
Optionally, the diode is turned on before the amplitude of the electrical signal under test received through the signal input reaches a peak value, and turned off after the amplitude of the electrical signal under test reaches a peak value.
Optionally, the signal sampling circuit further includes:
a clock source configured to provide a clock signal to the time to digital converter.
Optionally, the processing unit includes:
An analog-to-digital converter configured to convert an analog signal output by the amplitude holding unit into a digital signal.
Optionally, the signal sampling circuit further includes:
A memory configured to store data output by the processing unit.
The embodiment of the application also provides a detection device, which comprises a detector and the signal sampling circuit, wherein the detector is configured to detect radioactive rays and send generated electric signals to the signal sampling circuit.
Optionally, the detector comprises a scintillation crystal and a photoelectric converter coupled to each other.
Optionally, the photoelectric converter comprises a silicon photomultiplier, a photomultiplier tube, a charge coupled device, or an avalanche photodiode.
The embodiment of the application also provides an imaging system which comprises the detection device and an image reconstruction device, wherein the image reconstruction device is configured to reconstruct images of sampling points acquired by the signal sampling circuit.
As can be seen from the technical solutions provided in the embodiments of the present application, the third comparator and the time-to-digital converter are used to collect the first sampling point of the electrical signal to be measured, and the delay unit, the amplitude holding unit, the second comparator, the third comparator, the time-to-digital converter, the processing unit, and the like are used to collect the second sampling point of the electrical signal to be measured, which increases the number of points of the collected sampling points, so that the signal sampling precision and the accuracy of the subsequent signal recovery can be improved.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present application, and it is apparent that the described embodiments are only for explaining a part of the embodiments of the present application, not all the embodiments, and are not intended to limit the scope of the present application or the claims. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, shall fall within the scope of the application.
It will be understood that when an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected/coupled" to another element, it can be directly connected/coupled to the other element or intervening elements may also be present. The term "connected/coupled" as used herein may include electrically and/or mechanically physical connections/couplings. The term "comprising" as used herein refers to the presence of a feature, step or element, but does not exclude the presence or addition of one or more other features, steps or elements. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
In addition, in the description of the present application, the terms "first," "second," "third," etc. are used merely for descriptive purposes and distinguishing between similar objects, and not necessarily for describing a sequential or chronological order, nor are they to be construed as indicating or implying relative importance. Furthermore, in the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.
The signal sampling circuit, the detection device and the imaging system provided by the embodiment of the application are described in detail below with reference to the accompanying drawings.
As shown in fig. 2, an embodiment of the present application provides a signal sampling circuit 100, which may include a signal input terminal for receiving a signal from the outside and a reference amplitude supply terminal for providing a reference amplitude or presetting the reference amplitude therethrough, and a plurality of comparators (e.g., n first comparators 110, second comparators 120, third comparators 130, n being positive integers) and a time-to-digital converter (TDC) 140 connected to each other, and may further include a delay unit 150, an amplitude holding unit 160, and a processing unit 170. Wherein an input terminal of the delay unit 150 is connected to a signal input terminal, an output terminal thereof is connected to first input terminals of the second comparator 120 and the third comparator 130 of the plurality of comparators, an input terminal of the amplitude holding unit 160 is connected to a signal input terminal, an output terminal thereof is connected to a second input terminal of the third comparator 130, and the processing unit 170 is connected to output terminals of the time-to-digital converter 140 and the amplitude holding unit 160.
In an embodiment, two input terminals (i.e., a non-inverting input terminal and an inverting input terminal) of the first comparator 110 may be respectively connected to a signal input terminal (e.g., a V (t) input terminal) of the signal sampling circuit and a reference amplitude supply terminal (e.g., a V 1~Vn supply terminal) to receive the electrical signal to be measured and the reference amplitude, and an output terminal thereof may be connected to the TDC 140 to transmit the level signal thereto.
Each of the first comparators 110 may be a voltage comparator, and may be configured to compare the amplitude of the electric signal to be measured received through the signal input terminal with the reference amplitude received from the reference amplitude supply terminal, and output a corresponding level signal to the TDC 140 according to the comparison result. For example, when the amplitude of the electrical signal to be measured is greater than or equal to the reference amplitude, it may output a high level signal, and when the amplitude of the electrical signal to be measured is less than the reference amplitude, it may output a low level signal. Accordingly, the time-to-digital converter 140 may record a first time when the amplitude of the electrical signal under test reaches each reference amplitude according to the level signal received from each first comparator 110, thereby obtaining a first sampling point. Each first sampling point may be characterized by a reference amplitude and a corresponding first time, e.g., (T 1,V1)、(T2,V2)、(T3,V2) or (T 4,V1), and the reference amplitude may be recorded as the first amplitude.
It should be noted that, the reference amplitudes received by the n first comparators 110 are different from each other, and specific values of the reference amplitudes may be preset according to the characteristics of the electrical signal to be measured.
The second comparator 120 may also be a voltage comparator, which may be connected to one of the plurality of reference amplitude supply terminals, and may be used to compare the voltage of the delay signal received from the delay unit 150 with the reference amplitude received from the reference amplitude supply terminal connected thereto, and output a corresponding level signal to the TDC 160 according to the comparison result. For example, when the voltage of the delay signal is greater than or equal to the reference amplitude, it may output a high level signal, and when the voltage of the delay signal is less than the reference amplitude, it may output a low level signal. Accordingly, the time-to-digital converter 160 may record a first delay time when the voltage of the delay signal reaches the reference amplitude according to the received level signal.
The third comparator 130 may also be a voltage comparator that may be used to compare the amplitude of the delay signal received from the delay unit 150 with the second amplitude of the output signal of the amplitude holding unit 160 and output a corresponding level signal to the TDC 140 according to the comparison result. For example, when the amplitude of the delay signal is greater than or equal to the second amplitude of the output signal of the amplitude holding unit 160, it may output a high level signal, and when the amplitude of the delay signal is less than the second amplitude of the output signal of the amplitude holding unit 160, it may output a low level signal. Accordingly, the time-to-digital converter 160 may record a second delay time when the amplitude of the delay signal reaches the second amplitude of the output signal of the amplitude holding unit 160 according to the received level signal.
The TDC 140 may be configured to output a corresponding digital signal representing time according to the level signals received from the first, second and third comparators 110, 120 and 130. In a specific embodiment, the TDCs 140 may be flexibly set according to actual requirements, for example, two TDCs 160 may be set for each first comparator 110 to record two first times corresponding to each reference amplitude respectively, one TDC 140 may be set for each first comparator 110, second comparator 120 and third comparator 130 respectively, or only one TDC 140 may be set for all comparators, so as to reduce the volume and cost of the signal sampling circuit. For a detailed description of the TDC, reference may be made to related descriptions in the related art, and a detailed description thereof will be omitted.
The delay unit 150 may be configured to delay the received electrical signal to be measured for a period of time and transmit the delayed signal (i.e., the delayed signal) to the second comparator 120 and the third comparator 130, and the specific delay time of the electrical signal to be measured may be preset according to actual requirements or controlled in real time according to the received instruction. The delay unit 150 may be a delay line, and its length may be determined according to a delay time, or may be other delay elements or circuit structures.
The amplitude holding unit 160 may be designed or selected in advance according to actual demands or experience, and may be used to perform an amplitude holding process on the received electrical signal to be measured, so that a signal whose output amplitude is a certain value (i.e., the second amplitude) can be held for a certain period of time after the amplitude of the electrical signal to be measured reaches the certain value. For example, the amplitude holding unit 160 may hold a signal whose output amplitude is an amplitude threshold after the amplitude of the electric signal to be measured reaches the amplitude threshold set inside thereof, or may hold a signal whose output amplitude is a peak after the voltage of the electric signal to be measured reaches a peak (i.e., the maximum amplitude or the minimum amplitude of the electric signal to be measured), as shown in fig. 3. The second amplitude is different from the reference amplitude.
In one embodiment, as shown in fig. 4, the amplitude holding unit 160 may be a voltage holding circuit including elements such as a capacitor, a diode, and an inductor. In the voltage holding circuit, one end of the capacitor may be coupled to the one end of the inductor in parallel, the other end of the capacitor and one end of the diode may be connected to the second input of the second comparator 120 and the processing unit 170 in parallel, and the other end of the diode may be connected to the other end of the inductor in series. The diode can be conducted before the amplitude of the electric signal to be detected received through the signal input end reaches a peak value, and can be cut off after the amplitude of the electric signal to be detected reaches the peak value, so that the voltage of the capacitor can be stabilized for a period of time. In the measurement process, when the voltage across the capacitor suddenly changes, for example, from V i to V j (where i and j are different positive integers), the voltage of the electrical signal to be measured can be considered to reach a peak value, and the peak value is recorded.
The amplitude holding unit 160 may be any other element or circuit structure for holding a voltage, and is not limited thereto.
The processing unit 170 may be configured to process the time data output by the TDC 140 to determine a second time when the amplitude of the electrical signal under test reaches a second amplitude to obtain a second sampling point, for example, (T j,Vj). Specifically, the processing unit 170 may calculate a difference between the first delay time and the second delay time, and may calculate a second time corresponding to the second amplitude using the difference and the first time corresponding to the reference amplitude received by the second comparator from the reference amplitude supply terminal. The calculation process can be formulated as follows:
Tj=Ti+△T=Ti+(T'j-T'i)
In the above formula, T j represents a second time, preferably a time corresponding to the maximum amplitude or the minimum amplitude of the electrical signal to be measured, T i represents a first time, which may be any one of two first times corresponding to the reference amplitude received by the second comparator, T 'j represents a second delay time, and T' i may be a first delay time corresponding to the first time T i.
The processing unit 170 may be any device capable of data processing, for example, may be an FPGA chip or may be a processor integrated on the FPGA chip.
In another embodiment, as shown in FIG. 5, the signal sampling circuit 100 described above may further include a clock source 180 that may be coupled to the TDCs 140 to provide a clock signal (preferably, a synchronous clock signal) to each TDC 140 such that all of the TDCs 140 may operate in accordance with the received clock signal.
In another embodiment, the processing unit 170 may include an analog-to-digital converter (not shown) that may be connected to the amplitude maintaining unit 160 to convert the analog signal output from the amplitude maintaining unit 160 into a digital signal.
In another embodiment, as shown in fig. 6, the signal sampling circuit 100 may further include a memory 190, which may be connected to the processing unit 170 and may be used to store data output by the processing unit 170.
In the above embodiment, the first amplitude (i.e., the reference amplitude) and the second amplitude may each be a voltage or a current, or may be other physical quantities for representing the amplitude.
As can be seen from the above description, the signal sampling circuit provided by the embodiment of the present application collects the first sampling point of the electrical signal to be measured by using the first comparator and the TDC, and collects the second sampling point of the electrical signal to be measured by using the second comparator, the third comparator, the delay unit, the amplitude holding circuit, the processing unit, and the like, which increases the number of collected sampling points, thereby improving the sampling precision and the accuracy of the subsequent signal restoration. Moreover, by utilizing the technical scheme of the application, the amplitude point (namely, the wave crest or the wave trough) of the electric signal can be acquired in a self-adaptive manner, which is more beneficial to improving the accuracy of subsequent signal restoration, thereby improving the energy resolution.
The embodiment of the present application also provides a detection apparatus 1000, as shown in fig. 7, the detection apparatus 1000 may include the signal sampling circuit 100 described in the above embodiment and the detector 200 connected to the signal sampling circuit 100. The detector 200 may specifically be connected to a signal input terminal in the signal sampling circuit 100 to send an electrical signal to be measured to the signal sampling circuit 100. The detector 200 may be any detector capable of detecting a radioactive ray and generating a corresponding electrical signal, preferably a PET detector, in which case it may comprise a scintillation crystal 210 and a photoelectric converter 220 coupled to each other, as shown in fig. 8. The photoelectric converter 220 may include a silicon photomultiplier, a photomultiplier tube, a charge coupled device, an avalanche photodiode, or the like. The details of the scintillation crystal and the photoelectric converter can be referred to the related description in the prior art, and will not be described in detail herein.
By the detection device provided by the embodiment of the application, the digital sampling of the electric signal detected by the PET detector can be realized, and the amplitude point of the electric signal can be acquired in a self-adaptive manner, so that the accuracy of subsequent signal recovery can be improved.
The embodiment of the present application further provides an imaging system, as shown in fig. 9, where the imaging system may include the above-mentioned detecting device 1000 and an image reconstruction device 2000 connected to the detecting device 1000, where the image reconstruction device 2000 may be configured to perform image reconstruction processing on sampling points acquired by a signal sampling circuit in the detecting device 1000 to restore waveforms of electrical signals output by a detector in the detecting device 1000. The image reconstruction device 2000 may be any device capable of performing image reconstruction processing on the sampling points.
By utilizing the imaging system provided by the embodiment of the application, the accuracy of signal recovery can be improved.
The systems, devices, units, etc. described in the above embodiments may be implemented by a semiconductor chip, a computer chip, and/or an entity, or by a product having a certain function. For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of the units may be implemented in the same chip or chips when implementing the application.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. The embodiments described above are described in order to facilitate the understanding and use of the present application by those of ordinary skill in the art. It will be apparent to those skilled in the art that various modifications can be made to these embodiments and that the general principles described herein may be applied to other embodiments without the need for inventive faculty. Therefore, the present application is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications without departing from the scope of the present application.