CN110989919B

CN110989919B - Log recording mechanism for memory systems

Info

Publication number: CN110989919B
Application number: CN201910933263.0A
Authority: CN
Inventors: 安德瑞·蔻南; 亚历山大·扎波特洛克
Original assignee: SK Hynix Inc
Current assignee: SK Hynix Inc
Priority date: 2018-10-03
Filing date: 2019-09-29
Publication date: 2023-06-27
Anticipated expiration: 2039-09-29
Also published as: CN110989919A; US20200110652A1; US11599403B2

Abstract

The present invention relates to a method and system that can more easily identify problems associated with memory systems and simplify the analysis process. The method includes generating a detailed activity log having respective start and stop transmission events to facilitate identifying a problem in the memory device. Each event registered in the log contains a number of pieces of information. Such information helps identify the source of a particular problem, including the time and location of the problem, thereby making Fault Analysis (FA) easier and faster.

Description

Log recording mechanism for memory systems

Cross Reference to Related Applications

The present application claims priority from U.S. provisional application Ser. No. 62/740,772 filed on 3/10/2018, the entire contents of which are incorporated herein by reference.

Technical Field

Embodiments of the present disclosure relate to a logging mechanism for a memory system that is capable of narrowing the time span for a particular failure of the memory system.

Background

Computer environment paradigms have transformed into ubiquitous computing systems that are usable anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has been rapidly increasing. These portable electronic devices typically use a memory system with a memory device, i.e., a data storage device. The data storage device serves as a main memory device or a secondary memory device of the portable electronic device.

Since data storage devices using memory devices do not have moving parts, they provide excellent stability, durability, high information access speed, and low power consumption. Examples of data storage devices having these advantages include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, and Solid State Drives (SSDs).

An SSD may include a flash memory component and a controller including electronics to bridge the flash memory component to an input/output (I/O) interface of the SSD. The SSD controller may include an embedded microprocessor running functional components such as firmware. SSD function components are typically device specific and can be updated in most cases.

Two main types of flash memories are named NAND logic gates and NOR logic gates. Individual flash memory cells exhibit intrinsic characteristics similar to those of their respective gates. NAND-type flash memory can be written to and read from in blocks (or pages), which are typically much smaller than the entire memory space. NOR flash memory allows a single machine word (byte) to be written to an erase location or read independently. NAND-type flash memories mainly operate in memory cards, USB flash drives, SSDs, and the like for general data storage and transmission.

Debug information that accompanies abnormal behavior occurring in a memory system, such as an SSD, is typically continuously collected while it is in the user's field during the lifetime of the system. Such information is expected to help reduce problems or provide some clues in the event of a failure. However, because the log covers a period of time that may be up to five years (possibly the entire warranty period) and the log itself contains millions of entries, it may be difficult to determine when and where the problem occurred after the log was received from the user.

In this context, embodiments of the present invention are presented.

Disclosure of Invention

Embodiments of the present invention relate to a logging mechanism for a memory system that can narrow the time span over which a particular failure occurs to more easily identify when and where the particular failure occurred.

Accordingly, one aspect of the invention includes a method of operating a memory controller for detecting activity in a memory device associated with the memory controller. The method comprises the following steps: detecting a start transmission event defining a start of receiving a command group from a host; registering the transmission starting event in an activity log; detecting a specific period of time when no command is received after the transmission event is started; and after a certain period of time has elapsed, a stop transmission event is posted to the activity log.

Another aspect of the invention relates to a memory system that includes a memory device and a memory controller configured to detect activity in the memory device associated with the memory controller. The memory controller includes: a log logger detecting a start transmission event defining a start of a command group received from a host; registering the transmission starting event in an activity log; detecting a specific period of time when no command is received after the transmission event is started; and after a certain period of time has elapsed, a stop transmission event is posted to the activity log.

According to another aspect of the invention, a method of operating a memory controller that detects activity in a memory device associated with the memory controller. The method comprises the following steps: detecting a plurality of start transmission events, each of the plurality of start transmission events defining a start of receiving a respective command group from the host; registering each of a plurality of start transmission events in an activity log; detecting a specific period of time after each start transmission event when no command is received; and registering a plurality of stop transmission events in an activity log, each of the stop transmission events being registered after a corresponding one of the specific time periods has elapsed.

Other aspects of the invention will become apparent from the description that follows.

Drawings

Fig. 1 is a diagram illustrating a memory system according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a memory system according to an embodiment of the invention.

Fig. 3 is a circuit diagram illustrating a memory block of a memory device of a memory system according to an embodiment of the present invention.

Fig. 4 is a diagram illustrating a layout of a log recorder or log according to an embodiment of the present invention.

Fig. 5A and 5B are flowcharts illustrating the flow of host activity life log recording according to an embodiment of the present invention.

FIG. 6 is a flow chart illustrating a process of detecting activity in a memory device of a memory system according to an embodiment of the invention.

Detailed Description

Various embodiments are described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Furthermore, references herein to "an embodiment," "another embodiment," etc., are not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment. Throughout this disclosure, like reference numerals designate like parts throughout the drawings and embodiments of the present invention.

The invention can be implemented in numerous ways, including as a process, an apparatus, a system, a combination of objects, a computer program product embodied on a computer readable storage medium, and/or a processor such as one adapted to execute instructions stored on and/or provided by a memory coupled to the processor. In this specification, these embodiments, or any other form that the disclosure may take, may be referred to as solutions. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless otherwise indicated, components such as processors or memories described as suitable for performing the tasks may be implemented as general-purpose components temporarily configured to perform the tasks at a given time or as specific components manufactured to perform the tasks. As used herein, the term "processor" or the like refers to one or more devices, circuits, and/or processing cores adapted to process data, such as computer program instructions.

The following provides a detailed description of embodiments of the invention, along with accompanying figures that illustrate aspects of the invention. The invention will be described in connection with these embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims. The invention is intended to cover alternatives, modifications and equivalents, which may be included within the scope of the claims. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. These details are provided for the purpose of illustration; the present invention may be practiced according to the claims without some or all of these specific details. For the sake of clarity, technical material that is known in the technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

Fig. 1 is a block diagram schematically illustrating a memory system according to an embodiment of the present invention.

Referring to fig. 1, a memory system 10 may include a memory controller 100 and a semiconductor memory device 200, and the semiconductor memory device 200 may represent more than one such device. The semiconductor memory device 200 is preferably a flash memory device, particularly a NAND flash memory device.

The memory controller 100 may control the overall operation of the semiconductor memory device 200. For simplicity, the memory controller 100 and the semiconductor memory device 200 may hereinafter be sometimes simply referred to as the controller 100 and the memory device 200, respectively.

The semiconductor memory device 200 may perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 may receive a command CMD, an address ADDR, and DATA through input/output (I/O) lines. The semiconductor memory device 200 may receive the power PWR through a power line and the control signal CTRL through a control line. The control signal CTRL may include a Command Latch Enable (CLE) signal, an Address Latch Enable (ALE) signal, a Chip Enable (CE) signal, a Write Enable (WE) signal, a Read Enable (RE) signal, and the like.

The memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a Solid State Drive (SSD). The SSD may include a storage device for storing data therein. When the memory system 10 is used in an SSD, the operation speed of the host device 5 coupled to the memory system 10 can be significantly increased.

The memory controller 100 and the semiconductor memory device 200 may be integrated in a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 may be so integrated as to be configured to: personal Computer Memory Card International Association (PCMCIA) PC cards, compact Flash (CF) cards, smart Media (SM) cards, memory sticks, multimedia cards (MMC), reduced-size multimedia cards (RS-MMC), micro-sized versions MMC (MMC micro), secure Digital (SD) cards, mini secure digital (mini SD) cards, micro secure digital (micro SD) cards, secure Digital High Capacity (SDHC) cards, and/or Universal Flash (UFS).

In another embodiment, the memory system 10 may be provided as one of various components in an electronic device such as: a computer, an Ultra Mobile PC (UMPC), a workstation, a netbook computer, a Personal Digital Assistant (PDA), a portable computer, a web tablet PC, a wireless telephone, a mobile telephone, a smart phone, an electronic book reader, a Portable Multimedia Player (PMP), a portable gaming device, a navigation device, a black box, a digital camera, a Digital Multimedia Broadcasting (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device for a data center, a device capable of receiving and transmitting information in a wireless environment, a Radio Frequency Identification (RFID) device, and one of various electronic devices of a home network, one of various electronic devices of a computer network, one of various electronic devices of a telematics network, or one of various components of a computing system.

FIG. 2 is a detailed block diagram illustrating a memory system according to an embodiment of the invention. For example, the memory system of FIG. 2 may describe the memory system 10 shown in FIG. 1.

Referring to fig. 2, the memory system 10 may include a memory controller 100 and a semiconductor memory device 200. The memory system 10 may operate in response to a request from the host device 5, in particular, store data to be accessed by the host device 5.

The host device 5 may be implemented using any of a variety of electronic devices. In some embodiments, the host device 5 may include electronic devices such as the following: desktop computers, workstations, three-dimensional (3D) televisions, smart televisions, digital audio recorders, digital audio players, digital picture recorders, digital picture players, and/or digital video recorders, and digital video players. In some embodiments, the host device 5 may comprise a portable electronic device such as the following: mobile phones, smart phones, electronic books, MP3 players, portable Multimedia Players (PMPs), and/or portable gaming machines.

The memory device 200 may store data to be accessed by the host device 5.

The memory device 200 may be implemented with volatile memory devices such as Dynamic Random Access Memory (DRAM) and/or Static Random Access Memory (SRAM) or non-volatile memory devices such as the following: read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), ferroelectric Random Access Memory (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), and/or Resistive RAM (RRAM).

The controller 100 may control the storage of data in the memory device 200. For example, the controller 100 may control the memory device 200 in response to a request from the host device 5. The controller 100 may provide data read from the memory device 200 to the host device 5, and may store the data provided from the host device 5 in the memory device 200.

The controller 100 may include a storage 110, a control component 120, an Error Correction Code (ECC) component 130, a host interface (I/F) 140, and a memory interface (I/F) 150 coupled by a bus 160, where the control component 120 may be implemented as a processor such as a Central Processing Unit (CPU).

The storage device 110 may be used as a working memory of the memory system 10 and the controller 100, and stores data for driving the memory system 10 and the controller 100. When the controller 100 controls the operation of the memory device 200, the storage device 110 may store data used by the controller 100 and the memory device 200 for operations such as a read operation, a write operation, a program operation, and an erase operation.

The storage 110 may be implemented using volatile memory such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). As described above, the storage device 110 may store data used by the host device 5 in the memory device 200 for read operations and write operations. For storing data, the storage 110 may include program memory, data memory, write buffers, read buffers, map buffers, and the like. The storage 110 may include a hash table.

The control component 120 may control the general operation of the memory system 10 and control the write operation or read operation of the memory device 200 in response to a write request or read request from the host device 5. The control component 120 may drive firmware, referred to as a Flash Translation Layer (FTL) 125, to control the general operation of the memory system 10. For example, FTL 125 may perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage Collection (GC), and/or bad block processing. FTL 125 may be implemented as firmware in controller 100 and, more specifically, in control component 120. L2P mapping is referred to as logical block addressing.

During a read operation, the ECC component 130 can detect and correct errors in the data read from the memory device 200. When the number of error bits is greater than or equal to the threshold number of correctable error bits, the ECC component 130 may not correct the error bits, but may output an error correction failure signal indicating that the error bits have failed correction.

The ECC component 130 may perform error correction operations based on coded modulation such as: low Density Parity Check (LDPC) codes, bose-Chaudhri-Hocquenghem (BCH) codes, turbo Product Codes (TPC), reed-Solomon (RS) codes, convolutional codes, recursive Systematic Codes (RSC), trellis Coded Modulation (TCM), and Block Coded Modulation (BCM). The ECC component 130 may include any and all circuits, systems, or devices suitable for error correction operations.

The host interface 140 may communicate with the host device 5 via one or more of various interface protocols such as: universal Serial Bus (USB), multimedia card (MMC), peripheral component interconnect express (PCI-e or PCIe), small Computer System Interface (SCSI), serial SCSI (SAS), serial Advanced Technology Attachment (SATA), parallel Advanced Technology Attachment (PATA), nonvolatile memory express (NVMe), enhanced compact disc interface (ESDI), and integrated electronics drive (IDE).

The memory interface 150 may provide an interface between the controller 100 and the memory device 200 to allow the controller 100 to control the memory device 200 in response to a request from the host device 5. The memory interface 150 may generate control signals for the memory device 200 and process data under the control of the control component (or CPU) 120. When the memory device 200 is a flash memory such as a NAND flash memory, the memory interface 150 may generate a control signal for the memory and process data under the control of the CPU 120.

Memory device 200 may include an array of memory cells 210, control circuitry 220, voltage generation circuitry 230, row decoder 240, page buffer (array) 250, which may be in the form of a page buffer array, column decoder 260, and input/output circuitry 270. The memory cell array 210 may include a plurality of memory blocks 211 that may store data. Subsets of the memory blocks may be grouped into individual superblocks for certain operations.

The voltage generation circuit 230, the row decoder 240, the page buffer (array) 250, the column decoder 260, and the input/output circuit 270 may form peripheral circuits of the memory cell array 210. The peripheral circuits may perform a program operation, a read operation, or an erase operation of the memory cell array 210. The control circuit 220 may control peripheral circuits.

The voltage generation circuit 230 may generate various levels of operating voltages. For example, in the erase operation, the voltage generation circuit 230 may generate operation voltages of various levels such as an erase voltage and a pass voltage.

The row decoder 240 may be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 may select at least one memory block among the plurality of memory blocks 211 in response to the row address RADD generated by the control circuit 220 and transmit the operation voltage supplied from the voltage generation circuit 230 to the selected memory block.

The page buffer (array) 250 may be in electrical communication with the memory cell array 210 (shown in FIG. 3) via bit lines BL. The page buffer (array) 250 may precharge the bit lines BL with a positive voltage in response to a page buffer control signal generated by the control circuit 220, transfer data to a selected memory block in a program operation, and receive data from the selected memory block in a read operation, or temporarily store the transferred data.

The column decoder 260 may transfer data to and receive data from the page buffer (array) 250, and may also exchange data with the input/output circuit 270.

The input/output circuit 270 may transfer a command and an address received from an external device (e.g., the memory controller 100) to the control circuit 220, and transfer data from the external device to the column decoder 260 or output data from the column decoder 260 to the external device through the input/output circuit 270.

The control circuit 220 may control peripheral circuits in response to commands and addresses.

Fig. 3 is a circuit diagram showing a memory block of a semiconductor memory device according to an embodiment of the present invention. For example, the memory block of fig. 3 may be any one of the plurality of memory blocks 211 of the memory cell array 200 shown in fig. 2.

Referring to fig. 3, the exemplary memory block 211 may include a plurality of word lines WL0 to WLn-1, a drain select line DSL, and a source select line SSL coupled to the row decoder 240. These lines may be arranged in parallel, with multiple word lines between DSL and SSL.

The exemplary memory block 211 may further include a plurality of cell strings 221 coupled to the bit lines BL0 to BLm-1, respectively. The cell string 340 of each column may include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 through MCn-1 may be serially coupled between the selection transistors DST and SST. Each of the plurality of memory cells may be formed as a multi-level cell (MLC) that stores multi-bit data information.

The source of the SST in each cell string may be coupled to a common source line CSL, and the drain of each DST may be coupled to a corresponding bit line. The gates of the SSTs in the cell strings may be coupled to SSL and the gates of the DSTs in the cell strings may be coupled to DSL. The gates of the memory cells across the cell string may be coupled to respective word lines. That is, the gate of the memory cell MC0 is coupled to the corresponding word line WL0, the gate of the memory cell MC1 is coupled to the corresponding word line WL1, and the like. A group of memory cells coupled to a particular word line may be referred to as a physical page. Thus, the number of physical pages in the memory block 211 may correspond to the number of word lines.

As previously described, the page buffer (array) 250 may be in the form of a page buffer array including a plurality of page buffers 251 coupled to bit lines BL0 to BLm-1. The page buffer 251 may operate in response to a page buffer control signal. For example, during a read operation or a verify operation, the page buffer 251 may temporarily store data received through the bit lines BL0 to BLm-1 or sense a voltage or current of the bit lines.

In some embodiments, the memory block 211 may include NAND-type flash memory cells. However, the memory block 211 is not limited to this cell type, but may include NOR-type flash memory cells. The memory cell array 210 may be implemented as a hybrid flash memory combining two or more types of memory cells, or as a single NAND (one-NAND) flash memory with a controller embedded within a memory chip.

As previously mentioned, memory systems experience various problems during their entire life, some of which require a degree of analysis. While information about these problems is continually collected and recorded, it is difficult to find information about a particular problem, such as a fault, because there are so many entries that span a relatively long period of time.

Embodiments of the present invention provide an improved logging mechanism, such as a logger, that improves upon the above by facilitating locating information related to a particular problem of interest, and a method of detecting and logging activity in a memory system.

Referring to fig. 4, a layout of a log logger (or log) 41 according to an embodiment of the present invention is shown. The log logger 41 contains data that can be saved or cleared to a memory device 200, such as a NAND. The transfer start (traffic) event and the transfer stop event are registered in the log logger 41 for read commands, write commands, and other commands received from the host 5. For each event, there is one start record and one end record, and each record is time stamped.

More specifically, a given start transmission event 42 includes the following information: a time stamp 43a indicating a time at which the registration start transmission event is registered; a transmission start Identification (ID) 44a indicating a transmission start event; an operation code (Opcode) 45 indicating an operation performed by the command group associated with the start transmission event; a Logical Block Address (LBA) 46, indicating where operations are performed in the memory device 200, and a Length (Length) 47 of the command, may represent the number of sectors of the command.

For each start transmission event, there is a corresponding stop transmission event. In fig. 4, the stop transmission event 48 corresponds to the start transmission event 42 described above. The stop transmission event 48 includes a time stamp 43b indicating the time at which the stop transmission event was registered, a stop transmission ID 44b, and identifies the stop transmission event. The transmission stop event further includes the following information in common with the corresponding transmission start event: an operation code (Opcode) 45, an LBA 46, and a Length (Length) 47 of the command set.

An error log ID49 may exist between the start transmission event 42 and the stop transmission event 48.

In operation, the host device 5 transmits a command group, and at some point, stops transmitting commands. Typically, there is a period of time during which no command is sent. The intermittent period is used to register a stall event registered for the command group just sent. For example, once the firmware of memory controller 100 obtains the last command of the command group, a stop transfer event 48 may be registered. At the time of registering the stop transmission event 48, all of the relevant information described above is also registered.

In embodiments, the commands associated with a particular pair of start and stop events may be the same type of read command, write command, or other type of command that is acquired by the firmware. Separate timers may be used or separate time periods may be set for different types of commands.

As shown in the flowchart of fig. 5A, after the device starts or previously stops transmitting events, a start transmission event is recorded due to a first command in step 502. That is, the corresponding opcodes, arguments, time stamps, etc. are stored in RAM, e.g., storage 110. Then in step 503, the type of first command after expiration of a specific or set period of time is determined. The set period of time may be maintained by a timer, such as an ISR (interrupt service routine) timer, which may be set in the controller 100. The type of command refers to whether the command is a write command, a read command, or other command, as shown in step 504. Then, in step 505, the recorded start transfer event is cleared to the NAND, such as memory device 200.

Referring to the flowchart of fig. 5B, the ISR timer operates to measure a set period of time after the last command. Each type of command may have its own set period of time, as shown in step 506. After a time set for a specific type of command, a stop transmission event is detected and recorded. Typically, the set period of time may be about 10 minutes. Thereafter, in step 507, the recorded transfer stop event is cleared to NAND.

Although the exact location where the problem occurs over a longer period of time is not known, various commands sent by the user may be acquired. Such commands include test logs, windows activities, etc. The key is to establish a connection between host activity and drive activity. For example, events are sent from the memory system and host activity is introduced. Thus, intersections on the time axis can be found, i.e. between cells where the fault is located, in a log with millions of entries.

FIG. 6 is a flowchart 600 describing steps in the process of detecting activity in a memory device of a memory system, according to an embodiment of the present invention. The steps shown in flowchart 600 are exemplary. It will be appreciated by those of skill in the art that additional steps and/or alternative steps may be performed or the order of steps may be altered to practice aspects of the invention without departing from the inventive concepts disclosed herein.

In step 601, a start transmission event defining a start of receiving a command group from a host is detected. In step 602, a start transmission event is registered in an activity log. After the start of the transmission event, a specific period of time during which no command is received is detected in step 603. After a certain period of time, a stop transmission event is posted in the activity log in step 604. Then, as shown in

steps

605 and 606, the start transmission event and the stop transmission event are cleared to the NAND at appropriate times.

This process continues to create a detailed activity log of events that can be used to identify and resolve events or problems that occur in the operation of the memory system.

As previously described, embodiments of the present invention provide a mechanism to more quickly identify problems in memory devices. The mechanisms provided herein help identify the origin of a particular problem, including when and where the problem occurs, which is often difficult to do even with tracers and analyzers. Thus, embodiments of the present invention simplify these studies and make Fault Analysis (FA) easier and faster.

Although the foregoing embodiments have been illustrated and described in some detail for purposes of clarity and understanding, the invention is not limited to the details provided. As will be appreciated by those skilled in the art in light of the foregoing disclosure, there are many alternatives for practicing the invention. The disclosed embodiments are therefore illustrative and not restrictive.

Claims

1. A method of operating a memory controller that detects activity in a memory device associated with the memory controller, the method comprising:

detecting a start transmission event defining a start of receiving a command set from a host;

registering the transmission starting event in an activity log;

detecting a specific period of time when no command is received after the memory controller acquires a last command of the command group after the start transmission event; and

after the certain period of time has elapsed, a stop transmission event is registered in the activity log.

2. The method of claim 1, wherein the registering of the start transmission event comprises: a time stamp indicating the time at which the start transfer event was registered, a start transfer identification, an opcode indicating the operation performed by the command set, a logical block address indicating the location in the memory device at which the operation was performed, i.e., LBA, and the length of the command set are registered.

3. The method of claim 2, wherein the registering of the stop transmission event comprises: a time stamp indicating the time at which the stall event was registered, a stall identification, the opcode indicating the operation performed by the command set, the logical block address indicating the location in the memory device at which the operation was performed, the LBA, and the length of the command set are registered.

4. The method of claim 1, wherein the command sets are each of a particular type.

5. The method of claim 4, wherein the particular type is read or write.

6. The method of claim 1, wherein the detection of the start transmission event is based on the elapse of the particular time period since the host received a last command of an immediately preceding command set.

7. The method of claim 1, further comprising:

after registering the start transmission event, the start transmission event is stored in the memory device.

8. The method of claim 1, further comprising:

after registering the stall event, the stall event is stored in the memory device.

9. A memory system, comprising:

a memory device; and

a memory controller that detects activity in the memory device associated with the memory controller, the memory controller comprising: a log logger, the log logger:

registering the transmission starting event in an activity log;

10. The memory system of claim 9, wherein the memory controller comprises a timer for counting down the particular period of time.

11. The memory system of claim 10, wherein the memory controller comprises different timers for different types of commands.

12. The memory system of claim 9, wherein each of the start transmission event and the stop transmission event includes a respective timestamp and transmission identification.

13. A method of operating a memory controller that detects activity in a memory device associated with the memory controller, the method comprising:

detecting a plurality of start transmission events, each of the plurality of start transmission events defining a start of receiving a command set from a host;

registering each of the plurality of start transmission events in an activity log;

after each start transmission event, detecting a specific period of time when no command is received after the memory controller acquires a last command of the command group; and

registering a plurality of stop transmission events in said activity log, each of said stop transmission events being registered after a corresponding said specific period of time has elapsed.

14. The method of claim 13, further comprising:

each of the registered start transmission events is cleared to the memory device.

15. The method of claim 13, further comprising:

each of the registered stall events is cleared to the memory device.